1 /* $NetBSD: wd33c93.c,v 1.38 2026/01/11 06:23:27 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Changes Copyright (c) 2001 Wayne Knowles 39 * Changes Copyright (c) 1996 Steve Woodford 40 * Original Copyright (c) 1994 Christian E. Hopps 41 * 42 * This code is derived from software contributed to Berkeley by 43 * Van Jacobson of Lawrence Berkeley Laboratory. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 74 */ 75 76 /* 77 * This version of the driver is pretty well generic, so should work with 78 * any flavour of WD33C93 chip. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.38 2026/01/11 06:23:27 tsutsui Exp $"); 83 84 #include "opt_ddb.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> /* For hz */ 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsiconf.h> 96 #include <dev/scsipi/scsi_message.h> 97 98 #include <sys/bus.h> 99 100 #include <dev/ic/wd33c93reg.h> 101 #include <dev/ic/wd33c93var.h> 102 103 /* 104 * SCSI delays 105 * In u-seconds, primarily for state changes on the SPC. 106 */ 107 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 108 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 109 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 110 111 #define STATUS_UNKNOWN 0xff /* uninitialized status */ 112 113 /* 114 * Convenience macro for waiting for a particular wd33c93 event 115 */ 116 #define SBIC_WAIT(regs, until, timeo) wd33c93_wait(regs, until, timeo, __LINE__) 117 118 void wd33c93_init (struct wd33c93_softc *); 119 void wd33c93_reset (struct wd33c93_softc *); 120 int wd33c93_go (struct wd33c93_softc *, struct wd33c93_acb *); 121 int wd33c93_dmaok (struct wd33c93_softc *, struct scsipi_xfer *); 122 int wd33c93_wait (struct wd33c93_softc *, u_char, int , int); 123 u_char wd33c93_selectbus (struct wd33c93_softc *, struct wd33c93_acb *); 124 int wd33c93_xfout (struct wd33c93_softc *, int, void *); 125 int wd33c93_xfin (struct wd33c93_softc *, int, void *); 126 int wd33c93_poll (struct wd33c93_softc *, struct wd33c93_acb *); 127 int wd33c93_nextstate (struct wd33c93_softc *, struct wd33c93_acb *, 128 u_char, u_char); 129 int wd33c93_abort (struct wd33c93_softc *, struct wd33c93_acb *, 130 const char *); 131 void wd33c93_xferdone (struct wd33c93_softc *); 132 void wd33c93_error (struct wd33c93_softc *, struct wd33c93_acb *, 133 const char *); 134 void wd33c93_scsidone (struct wd33c93_softc *, struct wd33c93_acb *, int); 135 void wd33c93_sched (struct wd33c93_softc *); 136 void wd33c93_dequeue (struct wd33c93_softc *, struct wd33c93_acb *); 137 void wd33c93_dma_stop (struct wd33c93_softc *); 138 void wd33c93_dma_setup (struct wd33c93_softc *, int); 139 int wd33c93_msgin_phase (struct wd33c93_softc *, int); 140 void wd33c93_msgin (struct wd33c93_softc *, u_char *, int); 141 void wd33c93_reselect (struct wd33c93_softc *, int, int, int, int); 142 void wd33c93_sched_msgout (struct wd33c93_softc *, u_short); 143 void wd33c93_msgout (struct wd33c93_softc *); 144 void wd33c93_timeout_callout (void *arg); 145 int wd33c93_timeout (struct wd33c93_acb *); 146 void wd33c93_watchdog (void *arg); 147 u_char wd33c93_stp2syn (struct wd33c93_softc *, struct wd33c93_tinfo *); 148 void wd33c93_setsync (struct wd33c93_softc *, struct wd33c93_tinfo *); 149 void wd33c93_update_xfer_mode (struct wd33c93_softc *, int); 150 151 static struct pool wd33c93_pool; /* Adapter Control Blocks */ 152 static int wd33c93_pool_initialized = 0; 153 154 /* 155 * Timeouts 156 */ 157 int wd33c93_cmd_wait = SBIC_CMD_WAIT; 158 int wd33c93_data_wait = SBIC_DATA_WAIT; 159 int wd33c93_init_wait = SBIC_INIT_WAIT; 160 161 int wd33c93_nodma = 0; /* Use polled IO transfers */ 162 int wd33c93_nodisc = 0; /* Allow command queues */ 163 int wd33c93_notags = 0; /* No Tags */ 164 165 /* 166 * Some useful stuff for debugging purposes 167 */ 168 #ifdef DEBUG 169 170 #define QPRINTF(a) SBIC_DEBUG(MISC, a) 171 172 int wd33c93_debug = 0; /* Debug flags */ 173 174 void wd33c93_print_csr (u_char); 175 void wd33c93_hexdump (u_char *, int); 176 177 #else 178 #define QPRINTF(a) /* */ 179 #endif 180 181 static const char *wd33c93_chip_names[] = SBIC_CHIP_LIST; 182 183 /* 184 * Attach instance of driver and probe for sub devices 185 */ 186 void 187 wd33c93_attach(struct wd33c93_softc *sc) 188 { 189 struct scsipi_adapter *adapt = &sc->sc_adapter; 190 struct scsipi_channel *chan = &sc->sc_channel; 191 192 adapt->adapt_dev = sc->sc_dev; 193 adapt->adapt_nchannels = 1; 194 adapt->adapt_openings = 256; 195 adapt->adapt_max_periph = 256; /* Max tags per device */ 196 adapt->adapt_ioctl = NULL; 197 /* adapt_request initialized by MD interface */ 198 /* adapt_minphys initialized by MD interface */ 199 200 memset(chan, 0, sizeof(*chan)); 201 chan->chan_adapter = &sc->sc_adapter; 202 chan->chan_bustype = &scsi_bustype; 203 chan->chan_channel = 0; 204 chan->chan_ntargets = SBIC_NTARG; 205 chan->chan_nluns = SBIC_NLUN; 206 chan->chan_id = sc->sc_id; 207 208 callout_init(&sc->sc_watchdog, 0); 209 210 /* 211 * Add reference to adapter so that we drop the reference after 212 * config_found() to make sure the adapter is disabled. 213 */ 214 if (scsipi_adapter_addref(&sc->sc_adapter) != 0) { 215 aprint_error_dev(sc->sc_dev, "unable to enable controller\n"); 216 return; 217 } 218 219 sc->sc_cfflags = device_cfdata(sc->sc_dev)->cf_flags; 220 wd33c93_init(sc); 221 222 aprint_normal(": %s (%d.%d MHz clock, %s, SCSI ID %d)\n", 223 wd33c93_chip_names[sc->sc_chip], 224 sc->sc_clkfreq / 10, sc->sc_clkfreq % 10, 225 (sc->sc_dmamode == SBIC_CTL_DMA) ? "DMA" : 226 (sc->sc_dmamode == SBIC_CTL_DBA_DMA) ? "DBA" : 227 (sc->sc_dmamode == SBIC_CTL_BURST_DMA) ? "BURST DMA" : "PIO", 228 sc->sc_channel.chan_id); 229 if (sc->sc_chip == SBIC_CHIP_WD33C93B) { 230 aprint_normal_dev(sc->sc_dev, "microcode revision 0x%02x", 231 sc->sc_rev); 232 if (sc->sc_minsyncperiod < 50) 233 aprint_normal(", Fast SCSI"); 234 aprint_normal("\n"); 235 } 236 237 sc->sc_child = config_found(sc->sc_dev, &sc->sc_channel, 238 scsiprint, CFARGS_NONE); 239 scsipi_adapter_delref(&sc->sc_adapter); 240 } 241 242 /* 243 * Initialize driver-private structures 244 */ 245 void 246 wd33c93_init(struct wd33c93_softc *sc) 247 { 248 u_int i; 249 250 if (!wd33c93_pool_initialized) { 251 /* All instances share the same pool */ 252 pool_init(&wd33c93_pool, sizeof(struct wd33c93_acb), 0, 0, 0, 253 "wd33c93_acb", NULL, IPL_BIO); 254 ++wd33c93_pool_initialized; 255 } 256 257 if (sc->sc_state == 0) { 258 TAILQ_INIT(&sc->ready_list); 259 260 sc->sc_nexus = NULL; 261 sc->sc_disc = 0; 262 memset(sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 263 264 callout_reset(&sc->sc_watchdog, 60 * hz, wd33c93_watchdog, sc); 265 } else 266 panic("wd33c93: reinitializing driver!"); 267 268 sc->sc_flags = 0; 269 sc->sc_state = SBIC_IDLE; 270 wd33c93_reset(sc); 271 272 for (i = 0; i < 8; i++) { 273 struct wd33c93_tinfo *ti = &sc->sc_tinfo[i]; 274 /* 275 * cf_flags = 0xTTSSRR 276 * 277 * TT = Bitmask to disable Tagged Queues 278 * SS = Bitmask to disable Sync negotiation 279 * RR = Bitmask to disable disconnect/reselect 280 */ 281 ti->flags = T_NEED_RESET; 282 if (CFFLAGS_NOSYNC(sc->sc_cfflags, i)) 283 ti->flags |= T_NOSYNC; 284 if (CFFLAGS_NODISC(sc->sc_cfflags, i) || wd33c93_nodisc) 285 ti->flags |= T_NODISC; 286 ti->period = sc->sc_minsyncperiod; 287 ti->offset = 0; 288 } 289 } 290 291 void 292 wd33c93_reset(struct wd33c93_softc *sc) 293 { 294 u_int my_id, s, div, i; 295 u_char csr, reg; 296 297 SET_SBIC_cmd(sc, SBIC_CMD_ABORT); 298 WAIT_CIP(sc); 299 300 s = splbio(); 301 302 if (sc->sc_reset != NULL) 303 (*sc->sc_reset)(sc); 304 305 my_id = sc->sc_channel.chan_id & SBIC_ID_MASK; 306 307 /* Enable advanced features and really(!) advanced features */ 308 #if 1 309 my_id |= (SBIC_ID_EAF | SBIC_ID_RAF); /* XXX - MD Layer */ 310 #endif 311 312 SET_SBIC_myid(sc, my_id); 313 314 /* Reset the chip */ 315 SET_SBIC_cmd(sc, SBIC_CMD_RESET); 316 DELAY(25); 317 SBIC_WAIT(sc, SBIC_ASR_INT, 0); 318 319 /* Set up various chip parameters */ 320 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 321 322 GET_SBIC_csr(sc, csr); /* clears interrupt also */ 323 GET_SBIC_cdb1(sc, sc->sc_rev); /* valid with RAF on wd33c93b */ 324 325 switch (csr) { 326 case SBIC_CSR_RESET: 327 sc->sc_chip = SBIC_CHIP_WD33C93; 328 break; 329 case SBIC_CSR_RESET_AM: 330 SET_SBIC_queue_tag(sc, 0x55); 331 GET_SBIC_queue_tag(sc, reg); 332 sc->sc_chip = (reg == 0x55) ? 333 SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A; 334 SET_SBIC_queue_tag(sc, 0x0); 335 break; 336 default: 337 sc->sc_chip = SBIC_CHIP_UNKNOWN; 338 } 339 340 /* 341 * Choose a suitable clock divisor and work out the resulting 342 * sync transfer periods in 4ns units. 343 */ 344 if (sc->sc_clkfreq < 110) { 345 my_id |= SBIC_ID_FS_8_10; 346 div = 2; 347 } else if (sc->sc_clkfreq < 160) { 348 my_id |= SBIC_ID_FS_12_15; 349 div = 3; 350 } else if (sc->sc_clkfreq < 210) { 351 my_id |= SBIC_ID_FS_16_20; 352 div = 4; 353 } else 354 panic("wd33c93: invalid clock speed %d", sc->sc_clkfreq); 355 356 for (i = 0; i < 7; i++) 357 sc->sc_syncperiods[i] = 358 (i + 2) * div * 1250 / sc->sc_clkfreq; 359 sc->sc_minsyncperiod = sc->sc_syncperiods[0]; 360 SBIC_DEBUG(SYNC, ("available sync periods: %d %d %d %d %d %d %d\n", 361 sc->sc_syncperiods[0], sc->sc_syncperiods[1], 362 sc->sc_syncperiods[2], sc->sc_syncperiods[3], 363 sc->sc_syncperiods[4], sc->sc_syncperiods[5], 364 sc->sc_syncperiods[6])); 365 366 if (sc->sc_clkfreq >= 160 && sc->sc_chip == SBIC_CHIP_WD33C93B) { 367 for (i = 0; i < 3; i++) 368 sc->sc_fsyncperiods[i] = 369 (i + 2) * 2 * 1250 / sc->sc_clkfreq; 370 SBIC_DEBUG(SYNC, ("available fast sync periods: %d %d %d\n", 371 sc->sc_fsyncperiods[0], sc->sc_fsyncperiods[1], 372 sc->sc_fsyncperiods[2])); 373 sc->sc_minsyncperiod = sc->sc_fsyncperiods[0]; 374 } 375 376 /* Max Sync Offset */ 377 if (sc->sc_chip == SBIC_CHIP_WD33C93A || 378 sc->sc_chip == SBIC_CHIP_WD33C93B) 379 sc->sc_maxoffset = SBIC_SYN_93AB_MAX_OFFSET; 380 else 381 sc->sc_maxoffset = SBIC_SYN_93_MAX_OFFSET; 382 383 /* 384 * don't allow Selection (SBIC_RID_ES) 385 * until we can handle target mode!! 386 */ 387 SET_SBIC_rselid(sc, SBIC_RID_ER); 388 389 /* Asynchronous for now */ 390 SET_SBIC_syn(sc, 0); 391 392 sc->sc_flags = 0; 393 sc->sc_state = SBIC_IDLE; 394 395 splx(s); 396 } 397 398 void 399 wd33c93_error(struct wd33c93_softc *sc, struct wd33c93_acb *acb, 400 const char *str) 401 { 402 struct scsipi_xfer *xs = acb->xs; 403 404 KASSERT(xs); 405 406 if (xs->xs_control & XS_CTL_SILENT) 407 return; 408 409 scsipi_printaddr(xs->xs_periph); 410 printf("SCSI Error (%s)\n", str); 411 } 412 413 /* 414 * Determine an appropriate value for the synchronous transfer register 415 * given the period and offset values in *ti. 416 */ 417 u_char 418 wd33c93_stp2syn(struct wd33c93_softc *sc, struct wd33c93_tinfo *ti) 419 { 420 unsigned i; 421 422 /* see if we can handle fast scsi (100-200ns) first */ 423 if (ti->period < 50 && sc->sc_minsyncperiod < 50) { 424 for (i = 0; i < 3; i++) 425 if (sc->sc_fsyncperiods[i] >= ti->period) 426 return (SBIC_SYN(ti->offset, i + 2, 1)); 427 } 428 429 for (i = 0; i < 7; i++) { 430 if (sc->sc_syncperiods[i] >= ti->period) { 431 if (i == 6) 432 return (SBIC_SYN(0, 0, 0)); 433 else 434 return (SBIC_SYN(ti->offset, i + 2, 0)); 435 } 436 } 437 438 /* XXX - can't handle it; do async */ 439 return (SBIC_SYN(0, 0, 0)); 440 } 441 442 /* 443 * Setup sync mode for given target 444 */ 445 void 446 wd33c93_setsync(struct wd33c93_softc *sc, struct wd33c93_tinfo *ti) 447 { 448 u_char syncreg; 449 450 if (ti->flags & T_SYNCMODE) 451 syncreg = wd33c93_stp2syn(sc, ti); 452 else 453 syncreg = SBIC_SYN(0, 0, 0); 454 455 SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n", syncreg)); 456 SET_SBIC_syn(sc, syncreg); 457 } 458 459 /* 460 * Check if current operation can be done using DMA 461 * 462 * returns 1 if DMA OK, 0 for polled I/O transfer 463 */ 464 int 465 wd33c93_dmaok(struct wd33c93_softc *sc, struct scsipi_xfer *xs) 466 { 467 if (wd33c93_nodma || sc->sc_dmamode == SBIC_CTL_NO_DMA || 468 (xs->xs_control & XS_CTL_POLL) || xs->datalen == 0) 469 return (0); 470 return(1); 471 } 472 473 /* 474 * Setup for DMA transfer 475 */ 476 void 477 wd33c93_dma_setup(struct wd33c93_softc *sc, int datain) 478 { 479 struct wd33c93_acb *acb = sc->sc_nexus; 480 int s; 481 482 sc->sc_daddr = acb->daddr; 483 sc->sc_dleft = acb->dleft; 484 485 s = splbio(); 486 /* Indicate that we're in DMA mode */ 487 if (sc->sc_dleft) { 488 sc->sc_dmasetup(sc, &sc->sc_daddr, &sc->sc_dleft, 489 datain, &sc->sc_dleft); 490 } 491 splx(s); 492 return; 493 } 494 495 496 /* 497 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 498 */ 499 void 500 wd33c93_dma_stop(struct wd33c93_softc *sc) 501 { 502 size_t count; 503 int asr; 504 505 /* Wait until WD chip is idle */ 506 do { 507 GET_SBIC_asr(sc, asr); /* XXX */ 508 if (asr & SBIC_ASR_DBR) { 509 printf("wd33c93_dma_stop: asr %02x canceled!\n", asr); 510 break; 511 } 512 } while (asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 513 514 /* Only need to save pointers if DMA was active */ 515 if (sc->sc_flags & SBICF_INDMA) { 516 int s = splbio(); 517 518 /* Shut down DMA and flush FIFO's */ 519 sc->sc_dmastop(sc); 520 521 /* Fetch the residual count */ 522 SBIC_TC_GET(sc, count); 523 524 /* Work out how many bytes were actually transferred */ 525 count = sc->sc_tcnt - count; 526 527 if (sc->sc_dleft < count) 528 printf("xfer too large: dleft=%zu resid=%zu\n", 529 sc->sc_dleft, count); 530 531 /* Fixup partial xfers */ 532 sc->sc_daddr = (char *)sc->sc_daddr + count; 533 sc->sc_dleft -= count; 534 sc->sc_tcnt = 0; 535 sc->sc_flags &= ~SBICF_INDMA; 536 splx(s); 537 SBIC_DEBUG(DMA, ("dma_stop\n")); 538 } 539 /* 540 * Ensure the WD chip is back in polled I/O mode, with nothing to 541 * transfer. 542 */ 543 SBIC_TC_PUT(sc, 0); 544 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 545 } 546 547 548 /* 549 * Handle new request from scsipi layer 550 */ 551 void 552 wd33c93_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 553 { 554 struct wd33c93_softc *sc = 555 device_private(chan->chan_adapter->adapt_dev); 556 struct scsipi_xfer *xs; 557 struct scsipi_periph *periph; 558 struct wd33c93_acb *acb; 559 int flags, s; 560 561 SBIC_DEBUG(SCSIREQ, ("%s: req 0x%x\n", __func__, (int)req)); 562 563 switch (req) { 564 case ADAPTER_REQ_RUN_XFER: 565 xs = arg; 566 periph = xs->xs_periph; 567 flags = xs->xs_control; 568 569 if (flags & XS_CTL_DATA_UIO) 570 panic("wd33c93: scsi data uio requested"); 571 572 if (sc->sc_nexus && (flags & XS_CTL_POLL)) 573 panic("wd33c93_scsicmd: busy"); 574 575 s = splbio(); 576 acb = pool_get(&wd33c93_pool, PR_NOWAIT); 577 splx(s); 578 579 if (acb == NULL) { 580 scsipi_printaddr(periph); 581 printf("cannot allocate acb\n"); 582 xs->error = XS_RESOURCE_SHORTAGE; 583 scsipi_done(xs); 584 return; 585 } 586 587 SBIC_DEBUG(SCSIREQ, 588 ("wd33c93_scsi_request: RUN_XFER: acb %p\n", acb)); 589 590 acb->flags = ACB_ACTIVE; 591 acb->xs = xs; 592 acb->clen = xs->cmdlen; 593 acb->daddr = xs->data; 594 acb->dleft = xs->datalen; 595 acb->timeout = xs->timeout; 596 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 597 598 if (flags & XS_CTL_POLL) { 599 /* 600 * Complete currently active command(s) before 601 * issuing an immediate command 602 */ 603 while (sc->sc_nexus) 604 wd33c93_poll(sc, sc->sc_nexus); 605 } 606 607 s = splbio(); 608 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 609 acb->flags |= ACB_READY; 610 611 /* If nothing is active, try to start it now. */ 612 if (sc->sc_state == SBIC_IDLE) 613 wd33c93_sched(sc); 614 splx(s); 615 616 if ((flags & XS_CTL_POLL) == 0) 617 return; 618 619 if (wd33c93_poll(sc, acb)) { 620 wd33c93_timeout(acb); 621 if (wd33c93_poll(sc, acb)) /* 2nd retry for ABORT */ 622 wd33c93_timeout(acb); 623 } 624 return; 625 626 case ADAPTER_REQ_GROW_RESOURCES: 627 SBIC_DEBUG(SCSIREQ, ("%s: GROW_RESOURCES, UNSUPPORTED\n", 628 __func__)); 629 /* XXX Not supported. */ 630 /* XXX TODO: should fail the request */ 631 return; 632 633 case ADAPTER_REQ_SET_XFER_MODE: 634 { 635 struct wd33c93_tinfo *ti; 636 struct scsipi_xfer_mode *xm = arg; 637 638 ti = &sc->sc_tinfo[xm->xm_target]; 639 ti->flags &= ~T_WANTSYNC; 640 641 SBIC_DEBUG(SCSIREQ, ("%s: REQ_SET_XFER_MODE\n", __func__)); 642 643 if ((CFFLAGS_NOTAGS(sc->sc_cfflags, xm->xm_target) == 0) && 644 (xm->xm_mode & PERIPH_CAP_TQING) && !wd33c93_notags) 645 ti->flags |= T_TAG; 646 else 647 ti->flags &= ~T_TAG; 648 649 SBIC_DEBUG(SYNC, ("wd33c93_scsi_request: " 650 "target %d: scsipi requested %s\n", xm->xm_target, 651 (xm->xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 652 653 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 654 (ti->flags & T_NOSYNC) == 0) 655 ti->flags |= T_WANTSYNC; 656 /* 657 * If we're not going to negotiate, send the notification 658 * now, since it won't happen later. 659 */ 660 if (!(ti->flags & T_WANTSYNC) == !(ti->flags & T_SYNCMODE)) 661 wd33c93_update_xfer_mode(sc, xm->xm_target); 662 else 663 ti->flags |= T_NEGOTIATE; 664 return; 665 } 666 667 } 668 } 669 670 /* 671 * attempt to start the next available command 672 */ 673 void 674 wd33c93_sched(struct wd33c93_softc *sc) 675 { 676 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 677 struct wd33c93_acb *acb; 678 struct wd33c93_tinfo *ti; 679 struct wd33c93_linfo *li; 680 int lun, tag, flags; 681 682 if (sc->sc_state != SBIC_IDLE) 683 return; 684 685 KASSERT(sc->sc_nexus == NULL); 686 687 /* Loop through the ready list looking for work to do... */ 688 TAILQ_FOREACH(acb, &sc->ready_list, chain) { 689 periph = acb->xs->xs_periph; 690 lun = periph->periph_lun; 691 ti = &sc->sc_tinfo[periph->periph_target]; 692 li = TINFO_LUN(ti, lun); 693 694 KASSERT(acb->flags & ACB_READY); 695 696 /* Select type of tag for this command */ 697 if ((ti->flags & T_NODISC) != 0) 698 tag = 0; 699 else if ((ti->flags & T_TAG) == 0) 700 tag = 0; 701 else if ((acb->flags & ACB_SENSE) != 0) 702 tag = 0; 703 else if (acb->xs->xs_control & XS_CTL_POLL) 704 tag = 0; /* No tags for polled commands */ 705 else 706 tag = acb->xs->xs_tag_type; 707 708 if (li == NULL) { 709 /* Initialize LUN info and add to list. */ 710 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT); 711 if (li == NULL) 712 continue; 713 memset(li, 0, sizeof(*li)); 714 li->lun = lun; 715 if (lun < SBIC_NLUN) 716 ti->lun[lun] = li; 717 } 718 li->last_used = time_second; 719 720 /* 721 * We've found a potential command, but is the target/lun busy? 722 */ 723 724 if (tag == 0 && li->untagged == NULL) 725 li->untagged = acb; /* Issue untagged */ 726 727 if (li->untagged != NULL) { 728 tag = 0; 729 if ((li->state != L_STATE_BUSY) && li->used == 0) { 730 /* Issue this untagged command now */ 731 acb = li->untagged; 732 periph = acb->xs->xs_periph; 733 } else /* Not ready yet */ 734 continue; 735 } 736 737 acb->tag_type = tag; 738 if (tag != 0) { 739 if (li->queued[acb->xs->xs_tag_id]) 740 printf("queueing to active tag\n"); 741 li->queued[acb->xs->xs_tag_id] = acb; 742 acb->tag_id = acb->xs->xs_tag_id; 743 li->used++; 744 break; 745 } 746 if (li->untagged != NULL && (li->state != L_STATE_BUSY)) { 747 li->state = L_STATE_BUSY; 748 break; 749 } 750 if (li->untagged == NULL && tag != 0) { 751 break; 752 } else 753 printf("%d:%d busy\n", periph->periph_target, 754 periph->periph_lun); 755 } 756 757 if (acb == NULL) { 758 SBIC_DEBUG(ACBS, ("wd33c93sched: no work\n")); 759 return; /* did not find an available command */ 760 } 761 762 SBIC_DEBUG(ACBS, ("wd33c93_sched(%d,%d)\n", periph->periph_target, 763 periph->periph_lun)); 764 765 TAILQ_REMOVE(&sc->ready_list, acb, chain); 766 acb->flags &= ~ACB_READY; 767 768 flags = acb->xs->xs_control; 769 if (flags & XS_CTL_RESET) 770 wd33c93_reset(sc); 771 772 /* XXX - Implicitly call scsidone on select timeout */ 773 if (wd33c93_go(sc, acb) != 0 || acb->xs->error == XS_SELTIMEOUT) { 774 acb->dleft = sc->sc_dleft; 775 wd33c93_scsidone(sc, acb, sc->sc_status); 776 return; 777 } 778 779 return; 780 } 781 782 void 783 wd33c93_scsidone(struct wd33c93_softc *sc, struct wd33c93_acb *acb, int status) 784 { 785 struct scsipi_xfer *xs = acb->xs; 786 struct wd33c93_tinfo *ti; 787 struct wd33c93_linfo *li; 788 int s; 789 790 #ifdef DIAGNOSTIC 791 KASSERT(sc->target == xs->xs_periph->periph_target); 792 KASSERT(sc->lun == xs->xs_periph->periph_lun); 793 if (acb == NULL || xs == NULL) { 794 panic("wd33c93_scsidone -- (%d,%d) no scsipi_xfer", 795 sc->target, sc->lun); 796 } 797 KASSERT(acb->flags != ACB_FREE); 798 #endif 799 800 SBIC_DEBUG(ACBS, ("scsidone: (%d,%d)->(%d,%d)%02x\n", 801 xs->xs_periph->periph_target, xs->xs_periph->periph_lun, 802 sc->target, sc->lun, status)); 803 callout_stop(&xs->xs_callout); 804 805 xs->status = status & SCSI_STATUS_MASK; 806 xs->resid = acb->dleft; 807 808 if (xs->error == XS_NOERROR) { 809 switch (xs->status) { 810 case SCSI_CHECK: 811 case SCSI_TERMINATED: 812 /* XXX Need to read sense - return busy for now */ 813 /*FALLTHROUGH*/ 814 case SCSI_QUEUE_FULL: 815 case SCSI_BUSY: 816 xs->error = XS_BUSY; 817 break; 818 } 819 } 820 821 ti = &sc->sc_tinfo[sc->target]; 822 li = TINFO_LUN(ti, sc->lun); 823 ti->cmds++; 824 if (xs->error == XS_SELTIMEOUT) { 825 /* Selection timeout -- discard this LUN if empty */ 826 if (li->untagged == NULL && li->used == 0) { 827 if (sc->lun < SBIC_NLUN) 828 ti->lun[sc->lun] = NULL; 829 free(li, M_DEVBUF); 830 } 831 } 832 833 wd33c93_dequeue(sc, acb); 834 if (sc->sc_nexus == acb) { 835 sc->sc_state = SBIC_IDLE; 836 sc->sc_nexus = NULL; 837 sc->sc_flags = 0; 838 839 if (!TAILQ_EMPTY(&sc->ready_list)) 840 wd33c93_sched(sc); 841 } 842 843 /* place control block back on free list. */ 844 s = splbio(); 845 acb->flags = ACB_FREE; 846 pool_put(&wd33c93_pool, acb); 847 splx(s); 848 849 scsipi_done(xs); 850 } 851 852 void 853 wd33c93_dequeue(struct wd33c93_softc *sc, struct wd33c93_acb *acb) 854 { 855 struct wd33c93_tinfo *ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 856 struct wd33c93_linfo *li; 857 int lun = acb->xs->xs_periph->periph_lun; 858 859 li = TINFO_LUN(ti, lun); 860 #ifdef DIAGNOSTIC 861 if (li == NULL || li->lun != lun) 862 panic("wd33c93_dequeue: lun %d for ecb %p does not exist", 863 lun, acb); 864 #endif 865 if (li->untagged == acb) { 866 li->state = L_STATE_IDLE; 867 li->untagged = NULL; 868 } 869 if (acb->tag_type && li->queued[acb->tag_id] != NULL) { 870 #ifdef DIAGNOSTIC 871 if (li->queued[acb->tag_id] != NULL && 872 (li->queued[acb->tag_id] != acb)) 873 panic("wd33c93_dequeue: slot %d for lun %d has %p " 874 "instead of acb %p\n", acb->tag_id, 875 lun, li->queued[acb->tag_id], acb); 876 #endif 877 li->queued[acb->tag_id] = NULL; 878 li->used--; 879 } 880 } 881 882 883 int 884 wd33c93_wait(struct wd33c93_softc *sc, u_char until, int timeo, int line) 885 { 886 u_char val; 887 888 if (timeo == 0) 889 timeo = 1000000; /* some large value.. */ 890 GET_SBIC_asr(sc, val); 891 while ((val & until) == 0) { 892 if (timeo-- == 0) { 893 int csr; 894 GET_SBIC_csr(sc, csr); 895 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n", 896 line, val, csr); 897 #if defined(DDB) && defined(DEBUG) 898 Debugger(); 899 #endif 900 return(val); /* Maybe I should abort */ 901 break; 902 } 903 DELAY(1); 904 GET_SBIC_asr(sc, val); 905 } 906 return(val); 907 } 908 909 int 910 wd33c93_abort(struct wd33c93_softc *sc, struct wd33c93_acb *acb, 911 const char *where) 912 { 913 u_char csr, asr; 914 915 GET_SBIC_asr(sc, asr); 916 GET_SBIC_csr(sc, csr); 917 918 scsipi_printaddr(acb->xs->xs_periph); 919 printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr); 920 921 acb->timeout = SBIC_ABORT_TIMEOUT; 922 acb->flags |= ACB_ABORT; 923 924 /* 925 * Clean up chip itself 926 */ 927 if (sc->sc_nexus == acb) { 928 /* Reschedule timeout. */ 929 callout_reset(&acb->xs->xs_callout, mstohz(acb->timeout), 930 wd33c93_timeout_callout, acb); 931 932 while (asr & SBIC_ASR_DBR) { 933 /* 934 * wd33c93 is jammed w/data. need to clear it 935 * But we don't know what direction it needs to go 936 */ 937 GET_SBIC_data(sc, asr); 938 printf("abort %s: clearing data buffer 0x%02x\n", 939 where, asr); 940 GET_SBIC_asr(sc, asr); 941 if (asr & SBIC_ASR_DBR) /* Not the read direction */ 942 SET_SBIC_data(sc, asr); 943 GET_SBIC_asr(sc, asr); 944 } 945 946 scsipi_printaddr(acb->xs->xs_periph); 947 printf("sending ABORT command\n"); 948 949 WAIT_CIP(sc); 950 SET_SBIC_cmd(sc, SBIC_CMD_ABORT); 951 WAIT_CIP(sc); 952 953 GET_SBIC_asr(sc, asr); 954 955 scsipi_printaddr(acb->xs->xs_periph); 956 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 957 /* 958 * ok, get more drastic.. 959 */ 960 printf("Resetting bus\n"); 961 wd33c93_reset(sc); 962 } else { 963 printf("sending DISCONNECT to target\n"); 964 SET_SBIC_cmd(sc, SBIC_CMD_DISC); 965 WAIT_CIP(sc); 966 967 do { 968 SBIC_WAIT (sc, SBIC_ASR_INT, 0); 969 GET_SBIC_asr(sc, asr); 970 GET_SBIC_csr(sc, csr); 971 SBIC_DEBUG(MISC, ("csr: 0x%02x, asr: 0x%02x\n", 972 csr, asr)); 973 } while ((csr != SBIC_CSR_DISC) && 974 (csr != SBIC_CSR_DISC_1) && 975 (csr != SBIC_CSR_CMD_INVALID)); 976 } 977 sc->sc_state = SBIC_ERROR; 978 sc->sc_flags = 0; 979 } 980 return SBIC_STATE_ERROR; 981 } 982 983 984 /* 985 * select the bus, return when selected or error. 986 * 987 * Returns the current CSR following selection and optionally MSG out phase. 988 * i.e. the returned CSR *should* indicate CMD phase... 989 * If the return value is 0, some error happened. 990 */ 991 u_char 992 wd33c93_selectbus(struct wd33c93_softc *sc, struct wd33c93_acb *acb) 993 { 994 struct scsipi_xfer *xs = acb->xs; 995 struct wd33c93_tinfo *ti; 996 u_char target, lun, asr, csr, id; 997 998 KASSERT(sc->sc_state == SBIC_IDLE); 999 1000 target = xs->xs_periph->periph_target; 1001 lun = xs->xs_periph->periph_lun; 1002 ti = &sc->sc_tinfo[target]; 1003 1004 sc->sc_state = SBIC_SELECTING; 1005 sc->target = target; 1006 sc->lun = lun; 1007 1008 SBIC_DEBUG(PHASE, ("wd33c93_selectbus %d: ", target)); 1009 1010 if ((xs->xs_control & XS_CTL_POLL) == 0) 1011 callout_reset(&xs->xs_callout, mstohz(acb->timeout), 1012 wd33c93_timeout_callout, acb); 1013 1014 /* 1015 * issue select 1016 */ 1017 SBIC_TC_PUT(sc, 0); 1018 SET_SBIC_selid(sc, target); 1019 SET_SBIC_timeo(sc, SBIC_TIMEOUT(250, sc->sc_clkfreq)); 1020 1021 GET_SBIC_asr(sc, asr); 1022 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 1023 /* This means we got ourselves reselected upon */ 1024 SBIC_DEBUG(PHASE, ("WD busy (reselect?) ASR=%02x\n", asr)); 1025 return 0; 1026 } 1027 1028 SET_SBIC_cmd(sc, SBIC_CMD_SEL_ATN); 1029 WAIT_CIP(sc); 1030 1031 /* 1032 * wait for select (merged from separate function may need 1033 * cleanup) 1034 */ 1035 do { 1036 asr = SBIC_WAIT(sc, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1037 if (asr & SBIC_ASR_LCI) { 1038 QPRINTF(("late LCI: asr %02x\n", asr)); 1039 return 0; 1040 } 1041 1042 /* Clear interrupt */ 1043 GET_SBIC_csr (sc, csr); 1044 1045 /* Reselected from under our feet? */ 1046 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1047 SBIC_DEBUG(PHASE, ("got reselected, asr %02x\n", asr)); 1048 /* 1049 * We need to handle this now so we don't lock up later 1050 */ 1051 wd33c93_nextstate(sc, acb, csr, asr); 1052 return 0; 1053 } 1054 1055 /* Whoops! */ 1056 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1057 panic("wd33c93_selectbus: target issued select!"); 1058 return 0; 1059 } 1060 1061 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1062 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1063 csr != SBIC_CSR_SEL_TIMEO); 1064 1065 /* Anyone at home? */ 1066 if (csr == SBIC_CSR_SEL_TIMEO) { 1067 xs->error = XS_SELTIMEOUT; 1068 SBIC_DEBUG(PHASE, ("-- Selection Timeout\n")); 1069 return 0; 1070 } 1071 1072 SBIC_DEBUG(PHASE, ("Selection Complete\n")); 1073 1074 /* Assume we're now selected */ 1075 GET_SBIC_selid(sc, id); 1076 if (id != target) { 1077 /* Something went wrong - wrong target was select */ 1078 printf("wd33c93_selectbus: wrong target selected;" 1079 " WANTED %d GOT %d", target, id); 1080 return 0; /* XXX: Need to call nexstate to handle? */ 1081 } 1082 1083 sc->sc_flags |= SBICF_SELECTED; 1084 sc->sc_state = SBIC_CONNECTED; 1085 1086 /* setup correct sync mode for this target */ 1087 wd33c93_setsync(sc, ti); 1088 1089 if (ti->flags & T_NODISC && sc->sc_disc == 0) 1090 SET_SBIC_rselid (sc, 0); /* Not expecting a reselect */ 1091 else 1092 SET_SBIC_rselid (sc, SBIC_RID_ER); 1093 1094 /* 1095 * We only really need to do anything when the target goes to MSG out 1096 * If the device ignored ATN, it's probably old and brain-dead, 1097 * but we'll try to support it anyhow. 1098 * If it doesn't support message out, it definitely doesn't 1099 * support synchronous transfers, so no point in even asking... 1100 */ 1101 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1102 if (ti->flags & T_NEGOTIATE) { 1103 /* Initiate a SDTR message */ 1104 SBIC_DEBUG(SYNC, ("Sending SDTR to target %d\n", id)); 1105 if (ti->flags & T_WANTSYNC) { 1106 ti->period = sc->sc_minsyncperiod; 1107 ti->offset = sc->sc_maxoffset; 1108 } else { 1109 ti->period = 0; 1110 ti->offset = 0; 1111 } 1112 /* Send Sync negotiation message */ 1113 sc->sc_omsg[0] = MSG_IDENTIFY(lun, 0); /* No Disc */ 1114 sc->sc_omsg[1] = MSG_EXTENDED; 1115 sc->sc_omsg[2] = MSG_EXT_SDTR_LEN; 1116 sc->sc_omsg[3] = MSG_EXT_SDTR; 1117 if (ti->flags & T_WANTSYNC) { 1118 sc->sc_omsg[4] = sc->sc_minsyncperiod; 1119 sc->sc_omsg[5] = sc->sc_maxoffset; 1120 } else { 1121 sc->sc_omsg[4] = 0; 1122 sc->sc_omsg[5] = 0; 1123 } 1124 wd33c93_xfout(sc, 6, sc->sc_omsg); 1125 sc->sc_msgout |= SEND_SDTR; /* may be rejected */ 1126 sc->sc_flags |= SBICF_SYNCNEGO; 1127 } else { 1128 if (sc->sc_nexus->tag_type != 0) { 1129 /* Use TAGS */ 1130 SBIC_DEBUG(TAGS, ("<select %d:%d TAG=%x>\n", 1131 sc->target, sc->lun, 1132 sc->sc_nexus->tag_id)); 1133 sc->sc_omsg[0] = MSG_IDENTIFY(lun, 1); 1134 sc->sc_omsg[1] = sc->sc_nexus->tag_type; 1135 sc->sc_omsg[2] = sc->sc_nexus->tag_id; 1136 wd33c93_xfout(sc, 3, sc->sc_omsg); 1137 sc->sc_msgout |= SEND_TAG; 1138 } else { 1139 int no_disc; 1140 1141 /* Setup LUN nexus and disconnect privilege */ 1142 no_disc = xs->xs_control & XS_CTL_POLL || 1143 ti->flags & T_NODISC; 1144 SEND_BYTE(sc, MSG_IDENTIFY(lun, !no_disc)); 1145 } 1146 } 1147 /* 1148 * There's one interrupt still to come: 1149 * the change to CMD phase... 1150 */ 1151 SBIC_WAIT(sc, SBIC_ASR_INT , 0); 1152 GET_SBIC_csr(sc, csr); 1153 } 1154 1155 return csr; 1156 } 1157 1158 /* 1159 * Information Transfer *to* a SCSI Target. 1160 * 1161 * Note: Don't expect there to be an interrupt immediately after all 1162 * the data is transferred out. The WD spec sheet says that the Transfer- 1163 * Info command for non-MSG_IN phases only completes when the target 1164 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1165 * 1166 * This can have a nasty effect on commands which take a relatively long 1167 * time to complete, for example a START/STOP unit command may remain in 1168 * CMD phase until the disk has spun up. Only then will the target change 1169 * to STATUS phase. This is really only a problem for immediate commands 1170 * since we don't allow disconnection for them (yet). 1171 */ 1172 int 1173 wd33c93_xfout(struct wd33c93_softc *sc, int len, void *bp) 1174 { 1175 int wait = wd33c93_data_wait; 1176 u_char asr, *buf = bp; 1177 1178 QPRINTF(("wd33c93_xfout {%d} %02x %02x %02x %02x %02x " 1179 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1180 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1181 1182 /* 1183 * sigh.. WD-PROTO strikes again.. sending the command in one go 1184 * causes the chip to lock up if talking to certain (misbehaving?) 1185 * targets. Anyway, this procedure should work for all targets, but 1186 * it's slightly slower due to the overhead 1187 */ 1188 1189 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 1190 SBIC_TC_PUT (sc, (unsigned)len); 1191 1192 WAIT_CIP (sc); 1193 SET_SBIC_cmd (sc, SBIC_CMD_XFER_INFO); 1194 1195 /* 1196 * Loop for each byte transferred 1197 */ 1198 do { 1199 GET_SBIC_asr (sc, asr); 1200 1201 if (asr & SBIC_ASR_DBR) { 1202 if (len) { 1203 SET_SBIC_data (sc, *buf); 1204 buf++; 1205 len--; 1206 } else { 1207 SET_SBIC_data (sc, 0); 1208 } 1209 wait = wd33c93_data_wait; 1210 } 1211 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1212 1213 QPRINTF(("wd33c93_xfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1214 1215 /* 1216 * Normally, an interrupt will be pending when this routing returns. 1217 */ 1218 return(len); 1219 } 1220 1221 /* 1222 * Information Transfer *from* a Scsi Target 1223 * returns # bytes left to read 1224 */ 1225 int 1226 wd33c93_xfin(struct wd33c93_softc *sc, int len, void *bp) 1227 { 1228 int wait = wd33c93_data_wait; 1229 u_char *buf = bp; 1230 u_char asr; 1231 #ifdef DEBUG 1232 u_char *obp = bp; 1233 #endif 1234 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 1235 SBIC_TC_PUT (sc, (unsigned)len); 1236 1237 WAIT_CIP (sc); 1238 SET_SBIC_cmd (sc, SBIC_CMD_XFER_INFO); 1239 1240 /* 1241 * Loop for each byte transferred 1242 */ 1243 do { 1244 GET_SBIC_asr (sc, asr); 1245 1246 if (asr & SBIC_ASR_DBR) { 1247 if (len) { 1248 GET_SBIC_data (sc, *buf); 1249 buf++; 1250 len--; 1251 } else { 1252 u_char foo; 1253 GET_SBIC_data (sc, foo); 1254 __USE(foo); 1255 } 1256 wait = wd33c93_data_wait; 1257 } 1258 1259 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1260 1261 QPRINTF(("wd33c93_xfin {%d} %02x %02x %02x %02x %02x %02x " 1262 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1263 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1264 1265 SBIC_TC_PUT (sc, 0); 1266 1267 /* 1268 * this leaves with one csr to be read 1269 */ 1270 return len; 1271 } 1272 1273 1274 /* 1275 * Finish SCSI xfer command: After the completion interrupt from 1276 * a read/write operation, sequence through the final phases in 1277 * programmed i/o. 1278 */ 1279 void 1280 wd33c93_xferdone(struct wd33c93_softc *sc) 1281 { 1282 u_char phase, csr; 1283 int s; 1284 1285 QPRINTF(("{")); 1286 s = splbio(); 1287 1288 /* 1289 * have the wd33c93 complete on its own 1290 */ 1291 SBIC_TC_PUT(sc, 0); 1292 SET_SBIC_cmd_phase(sc, 0x46); 1293 SET_SBIC_cmd(sc, SBIC_CMD_SEL_ATN_XFER); 1294 1295 do { 1296 SBIC_WAIT (sc, SBIC_ASR_INT, 0); 1297 GET_SBIC_csr (sc, csr); 1298 QPRINTF(("%02x:", csr)); 1299 } while ((csr != SBIC_CSR_DISC) && 1300 (csr != SBIC_CSR_DISC_1) && 1301 (csr != SBIC_CSR_S_XFERRED)); 1302 1303 sc->sc_flags &= ~SBICF_SELECTED; 1304 sc->sc_state = SBIC_DISCONNECT; 1305 1306 GET_SBIC_cmd_phase (sc, phase); 1307 QPRINTF(("}%02x", phase)); 1308 1309 if (phase == 0x60) 1310 GET_SBIC_tlun(sc, sc->sc_status); 1311 else 1312 wd33c93_error(sc, sc->sc_nexus, "unexpected phase"); 1313 1314 QPRINTF(("=STS:%02x=\n", sc->sc_status)); 1315 splx(s); 1316 } 1317 1318 1319 int 1320 wd33c93_go(struct wd33c93_softc *sc, struct wd33c93_acb *acb) 1321 { 1322 struct scsipi_xfer *xs = acb->xs; 1323 int i, dmaok; 1324 u_char csr, asr; 1325 1326 SBIC_DEBUG(ACBS, ("wd33c93_go(%d:%d)\n", sc->target, sc->lun)); 1327 1328 sc->sc_nexus = acb; 1329 1330 sc->target = xs->xs_periph->periph_target; 1331 sc->lun = xs->xs_periph->periph_lun; 1332 1333 sc->sc_status = STATUS_UNKNOWN; 1334 sc->sc_daddr = acb->daddr; 1335 sc->sc_dleft = acb->dleft; 1336 1337 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 1338 sc->sc_flags = 0; 1339 1340 dmaok = wd33c93_dmaok(sc, xs); 1341 1342 if (dmaok == 0) 1343 sc->sc_flags |= SBICF_NODMA; 1344 1345 SBIC_DEBUG(DMA, ("wd33c93_go dmago:%d(tcnt=%zx) dmaok=%dx\n", 1346 sc->target, sc->sc_tcnt, dmaok)); 1347 1348 /* select the SCSI bus (it's an error if bus isn't free) */ 1349 if ((csr = wd33c93_selectbus(sc, acb)) == 0) 1350 return(0); /* Not done: needs to be rescheduled */ 1351 1352 /* 1353 * Lets cycle a while then let the interrupt handler take over. 1354 */ 1355 GET_SBIC_asr(sc, asr); 1356 do { 1357 QPRINTF(("go[0x%x] ", csr)); 1358 1359 /* Handle the new phase */ 1360 i = wd33c93_nextstate(sc, acb, csr, asr); 1361 WAIT_CIP(sc); /* XXX */ 1362 if (sc->sc_state == SBIC_CONNECTED) { 1363 1364 GET_SBIC_asr(sc, asr); 1365 1366 if (asr & SBIC_ASR_LCI) 1367 printf("wd33c93_go: LCI asr:%02x csr:%02x\n", asr, csr); 1368 1369 if (asr & SBIC_ASR_INT) 1370 GET_SBIC_csr(sc, csr); 1371 } 1372 1373 } while (sc->sc_state == SBIC_CONNECTED && 1374 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1375 1376 QPRINTF(("> done i=%d stat=%02x\n", i, sc->sc_status)); 1377 1378 if (i == SBIC_STATE_DONE) { 1379 if (sc->sc_status == STATUS_UNKNOWN) { 1380 printf("wd33c93_go: done & stat == UNKNOWN\n"); 1381 return 1; /* Did we really finish that fast? */ 1382 } 1383 } 1384 return 0; 1385 } 1386 1387 1388 int 1389 wd33c93_intr(struct wd33c93_softc *sc) 1390 { 1391 u_char asr, csr; 1392 1393 /* 1394 * pending interrupt? 1395 */ 1396 GET_SBIC_asr (sc, asr); 1397 if ((asr & SBIC_ASR_INT) == 0) 1398 return(0); 1399 1400 GET_SBIC_csr(sc, csr); 1401 1402 do { 1403 SBIC_DEBUG(INTS, ("intr[csr=0x%x]", csr)); 1404 1405 (void)wd33c93_nextstate(sc, sc->sc_nexus, csr, asr); 1406 WAIT_CIP(sc); /* XXX */ 1407 if (sc->sc_state == SBIC_CONNECTED) { 1408 GET_SBIC_asr(sc, asr); 1409 1410 if (asr & SBIC_ASR_LCI) 1411 printf("wd33c93_intr: LCI asr:%02x csr:%02x\n", 1412 asr, csr); 1413 1414 if (asr & SBIC_ASR_INT) 1415 GET_SBIC_csr(sc, csr); 1416 } 1417 } while (sc->sc_state == SBIC_CONNECTED && 1418 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1419 1420 SBIC_DEBUG(INTS, ("intr done. state=%d, asr=0x%02x\n", 1421 sc->sc_state, asr)); 1422 1423 return(1); 1424 } 1425 1426 /* 1427 * Complete current command using polled I/O. Used when interrupt driven 1428 * I/O is not allowed (ie. during boot and shutdown) 1429 * 1430 * Polled I/O is very processor intensive 1431 */ 1432 int 1433 wd33c93_poll(struct wd33c93_softc *sc, struct wd33c93_acb *acb) 1434 { 1435 u_char asr, csr=0; 1436 int count; 1437 struct scsipi_xfer *xs = acb->xs; 1438 1439 SBIC_WAIT(sc, SBIC_ASR_INT, wd33c93_cmd_wait); 1440 for (count=acb->timeout; count;) { 1441 GET_SBIC_asr (sc, asr); 1442 if (asr & SBIC_ASR_LCI) 1443 printf("wd33c93_poll: LCI; asr:%02x csr:%02x\n", 1444 asr, csr); 1445 if (asr & SBIC_ASR_INT) { 1446 GET_SBIC_csr(sc, csr); 1447 sc->sc_flags |= SBICF_NODMA; 1448 (void)wd33c93_nextstate(sc, sc->sc_nexus, csr, asr); 1449 WAIT_CIP(sc); /* XXX */ 1450 } else { 1451 DELAY(1000); 1452 count--; 1453 } 1454 1455 if ((xs->xs_status & XS_STS_DONE) != 0) 1456 return (0); 1457 1458 if (sc->sc_state == SBIC_IDLE) { 1459 SBIC_DEBUG(ACBS, ("[poll: rescheduling] ")); 1460 wd33c93_sched(sc); 1461 } 1462 } 1463 return (1); 1464 } 1465 1466 static inline int 1467 __verify_msg_format(u_char *p, int len) 1468 { 1469 1470 if (len == 1 && MSG_IS1BYTE(p[0])) 1471 return 1; 1472 if (len == 2 && MSG_IS2BYTE(p[0])) 1473 return 1; 1474 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1475 len == p[1] + 2) 1476 return 1; 1477 return 0; 1478 } 1479 1480 /* 1481 * Handle message_in phase 1482 */ 1483 int 1484 wd33c93_msgin_phase(struct wd33c93_softc *sc, int reselect) 1485 { 1486 int len; 1487 u_char asr, csr, *msg; 1488 1489 GET_SBIC_asr(sc, asr); 1490 __USE(asr); 1491 1492 SBIC_DEBUG(MSGS, ("wd33c93msgin asr=%02x\n", asr)); 1493 1494 GET_SBIC_selid (sc, csr); 1495 SET_SBIC_selid (sc, csr | SBIC_SID_FROM_SCSI); 1496 1497 SBIC_TC_PUT(sc, 0); 1498 1499 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 1500 1501 msg = sc->sc_imsg; 1502 len = 0; 1503 1504 do { 1505 /* Fetch the next byte of the message */ 1506 RECV_BYTE(sc, *msg++); 1507 len++; 1508 1509 /* 1510 * get the command completion interrupt, or we 1511 * can't send a new command (LCI) 1512 */ 1513 SBIC_WAIT(sc, SBIC_ASR_INT, 0); 1514 GET_SBIC_csr(sc, csr); 1515 1516 if (__verify_msg_format(sc->sc_imsg, len)) 1517 break; /* Complete message received */ 1518 1519 /* 1520 * Clear ACK, and wait for the interrupt 1521 * for the next byte or phase change 1522 */ 1523 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK); 1524 SBIC_WAIT(sc, SBIC_ASR_INT, 0); 1525 1526 GET_SBIC_csr(sc, csr); 1527 } while (len < SBIC_MAX_MSGLEN); 1528 1529 if (__verify_msg_format(sc->sc_imsg, len)) 1530 wd33c93_msgin(sc, sc->sc_imsg, len); 1531 1532 /* 1533 * Clear ACK, and wait for the interrupt 1534 * for the phase change 1535 */ 1536 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK); 1537 SBIC_WAIT(sc, SBIC_ASR_INT, 0); 1538 1539 /* Should still have one CSR to read */ 1540 return SBIC_STATE_RUNNING; 1541 } 1542 1543 1544 void wd33c93_msgin(struct wd33c93_softc *sc, u_char *msgaddr, int msglen) 1545 { 1546 struct wd33c93_acb *acb = sc->sc_nexus; 1547 struct wd33c93_tinfo *ti = &sc->sc_tinfo[sc->target]; 1548 struct wd33c93_linfo *li; 1549 u_char asr; 1550 1551 switch (sc->sc_state) { 1552 case SBIC_CONNECTED: 1553 switch (msgaddr[0]) { 1554 case MSG_MESSAGE_REJECT: 1555 SBIC_DEBUG(MSGS, ("msgin: MSG_REJECT, " 1556 "last msgout=%x\n", sc->sc_msgout)); 1557 switch (sc->sc_msgout) { 1558 case SEND_TAG: 1559 printf("%s: tagged queuing rejected: " 1560 "target %d\n", 1561 device_xname(sc->sc_dev), sc->target); 1562 ti->flags &= ~T_TAG; 1563 li = TINFO_LUN(ti, sc->lun); 1564 if (acb->tag_type && 1565 li->queued[acb->tag_id] != NULL) { 1566 li->queued[acb->tag_id] = NULL; 1567 li->used--; 1568 } 1569 acb->tag_type = acb->tag_id = 0; 1570 li->untagged = acb; 1571 li->state = L_STATE_BUSY; 1572 break; 1573 1574 case SEND_SDTR: 1575 printf("%s: sync transfer rejected: target %d\n", 1576 device_xname(sc->sc_dev), sc->target); 1577 1578 sc->sc_flags &= ~SBICF_SYNCNEGO; 1579 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1580 wd33c93_update_xfer_mode(sc, 1581 acb->xs->xs_periph->periph_target); 1582 wd33c93_setsync(sc, ti); 1583 1584 case SEND_INIT_DET_ERR: 1585 goto abort; 1586 1587 default: 1588 SBIC_DEBUG(MSGS, ("Unexpected MSG_REJECT\n")); 1589 break; 1590 } 1591 sc->sc_msgout = 0; 1592 break; 1593 1594 case MSG_HEAD_OF_Q_TAG: 1595 case MSG_ORDERED_Q_TAG: 1596 case MSG_SIMPLE_Q_TAG: 1597 printf("-- Out of phase TAG;" 1598 "Nexus=%d:%d Tag=%02x/%02x\n", 1599 sc->target, sc->lun, msgaddr[0], msgaddr[1]); 1600 break; 1601 1602 case MSG_DISCONNECT: 1603 SBIC_DEBUG(MSGS, ("msgin: DISCONNECT")); 1604 /* 1605 * Mark the fact that all bytes have moved. The 1606 * target may not bother to do a SAVE POINTERS 1607 * at this stage. This flag will set the residual 1608 * count to zero on MSG COMPLETE. 1609 */ 1610 if (sc->sc_dleft == 0) 1611 acb->flags |= ACB_COMPLETE; 1612 1613 if (acb->xs->xs_control & XS_CTL_POLL) 1614 /* Don't allow disconnect in immediate mode */ 1615 goto reject; 1616 else { /* Allow disconnect */ 1617 sc->sc_flags &= ~SBICF_SELECTED; 1618 sc->sc_state = SBIC_DISCONNECT; 1619 } 1620 if ((acb->xs->xs_periph->periph_quirks & 1621 PQUIRK_AUTOSAVE) == 0) 1622 break; 1623 /*FALLTHROUGH*/ 1624 1625 case MSG_SAVEDATAPOINTER: 1626 SBIC_DEBUG(MSGS, ("msgin: SAVEDATAPTR")); 1627 acb->daddr = sc->sc_daddr; 1628 acb->dleft = sc->sc_dleft; 1629 break; 1630 1631 case MSG_RESTOREPOINTERS: 1632 SBIC_DEBUG(MSGS, ("msgin: RESTOREPTR")); 1633 sc->sc_daddr = acb->daddr; 1634 sc->sc_dleft = acb->dleft; 1635 break; 1636 1637 case MSG_CMDCOMPLETE: 1638 /* 1639 * !! KLUDGE ALERT !! quite a few drives don't seem to 1640 * really like the current way of sending the 1641 * sync-handshake together with the ident-message, and 1642 * they react by sending command-complete and 1643 * disconnecting right after returning the valid sync 1644 * handshake. So, all I can do is reselect the drive, 1645 * and hope it won't disconnect again. I don't think 1646 * this is valid behavior, but I can't help fixing a 1647 * problem that apparently exists. 1648 * 1649 * Note: we should not get here on `normal' command 1650 * completion, as that condition is handled by the 1651 * high-level sel&xfer resume command used to walk 1652 * thru status/cc-phase. 1653 */ 1654 SBIC_DEBUG(MSGS, ("msgin: CMD_COMPLETE")); 1655 SBIC_DEBUG(SYNC, ("GOT MSG %d! target %d" 1656 " acting weird.." 1657 " waiting for disconnect...\n", 1658 msgaddr[0], sc->target)); 1659 1660 /* Check to see if wd33c93 is handling this */ 1661 GET_SBIC_asr(sc, asr); 1662 if (asr & SBIC_ASR_BSY) 1663 break; 1664 1665 /* XXX: Assume it works and set status to 00 */ 1666 sc->sc_status = 0; 1667 sc->sc_state = SBIC_CMDCOMPLETE; 1668 break; 1669 1670 case MSG_EXTENDED: 1671 switch(msgaddr[2]) { 1672 case MSG_EXT_SDTR: /* Sync negotiation */ 1673 SBIC_DEBUG(MSGS, ("msgin: EXT_SDTR; " 1674 "period %d, offset %d", 1675 msgaddr[3], msgaddr[4])); 1676 if (msgaddr[1] != 3) 1677 goto reject; 1678 1679 ti->period = 1680 MAX(msgaddr[3], sc->sc_minsyncperiod); 1681 ti->offset = MIN(msgaddr[4], sc->sc_maxoffset); 1682 1683 /* 1684 * <SGI, IBM DORS-32160, WA6A> will do nothing 1685 * but attempt sync negotiation until it gets 1686 * what it wants. To avoid an infinite loop set 1687 * off by the identify request, oblige them. 1688 */ 1689 if ((sc->sc_flags&SBICF_SYNCNEGO) == 0 && 1690 msgaddr[3] != 0) 1691 ti->flags |= T_WANTSYNC; 1692 1693 if (!(ti->flags & T_WANTSYNC)) 1694 ti->period = ti->offset = 0; 1695 1696 ti->flags &= ~T_NEGOTIATE; 1697 1698 if (ti->offset == 0) 1699 ti->flags &= ~T_SYNCMODE; /* Async */ 1700 else 1701 ti->flags |= T_SYNCMODE; /* Sync */ 1702 1703 /* target initiated negotiation */ 1704 if ((sc->sc_flags&SBICF_SYNCNEGO) == 0) 1705 wd33c93_sched_msgout(sc, SEND_SDTR); 1706 sc->sc_flags &= ~SBICF_SYNCNEGO; 1707 1708 SBIC_DEBUG(SYNC, ("msgin(%d): SDTR(o=%d,p=%d)", 1709 sc->target, ti->offset, 1710 ti->period)); 1711 wd33c93_update_xfer_mode(sc, 1712 acb->xs->xs_periph->periph_target); 1713 wd33c93_setsync(sc, ti); 1714 break; 1715 1716 case MSG_EXT_WDTR: 1717 SBIC_DEBUG(MSGS, ("msgin: EXT_WDTR rejected")); 1718 goto reject; 1719 1720 default: 1721 scsipi_printaddr(acb->xs->xs_periph); 1722 printf("unrecognized MESSAGE EXTENDED;" 1723 " sending REJECT\n"); 1724 goto reject; 1725 } 1726 break; 1727 1728 default: 1729 scsipi_printaddr(acb->xs->xs_periph); 1730 printf("unrecognized MESSAGE; sending REJECT\n"); 1731 1732 reject: 1733 /* We don't support whatever this message is... */ 1734 wd33c93_sched_msgout(sc, SEND_REJECT); 1735 break; 1736 } 1737 break; 1738 1739 case SBIC_IDENTIFIED: 1740 /* 1741 * IDENTIFY message was received and queue tag is expected now 1742 */ 1743 if ((msgaddr[0]!=MSG_SIMPLE_Q_TAG) || (sc->sc_msgify==0)) { 1744 printf("%s: TAG reselect without IDENTIFY;" 1745 " MSG %x; sending DEVICE RESET\n", 1746 device_xname(sc->sc_dev), msgaddr[0]); 1747 goto reset; 1748 } 1749 SBIC_DEBUG(TAGS, ("TAG %x/%x\n", msgaddr[0], msgaddr[1])); 1750 if (sc->sc_nexus) 1751 printf("*TAG Recv with active nexus!!\n"); 1752 wd33c93_reselect(sc, sc->target, sc->lun, 1753 msgaddr[0], msgaddr[1]); 1754 break; 1755 1756 case SBIC_RESELECTED: 1757 /* 1758 * IDENTIFY message with target 1759 */ 1760 if (MSG_ISIDENTIFY(msgaddr[0])) { 1761 SBIC_DEBUG(PHASE, ("IFFY[%x] ", msgaddr[0])); 1762 sc->sc_msgify = msgaddr[0]; 1763 } else { 1764 printf("%s: reselect without IDENTIFY;" 1765 " MSG %x;" 1766 " sending DEVICE RESET\n", 1767 device_xname(sc->sc_dev), msgaddr[0]); 1768 goto reset; 1769 } 1770 break; 1771 1772 default: 1773 printf("Unexpected MESSAGE IN. State=%d - Sending RESET\n", 1774 sc->sc_state); 1775 reset: 1776 wd33c93_sched_msgout(sc, SEND_DEV_RESET); 1777 break; 1778 abort: 1779 wd33c93_sched_msgout(sc, SEND_ABORT); 1780 break; 1781 } 1782 } 1783 1784 void 1785 wd33c93_sched_msgout(struct wd33c93_softc *sc, u_short msg) 1786 { 1787 u_char asr; 1788 1789 SBIC_DEBUG(SYNC,("sched_msgout: %04x\n", msg)); 1790 sc->sc_msgpriq |= msg; 1791 1792 /* Schedule MSGOUT Phase to send message */ 1793 1794 WAIT_CIP(sc); 1795 SET_SBIC_cmd(sc, SBIC_CMD_SET_ATN); 1796 WAIT_CIP(sc); 1797 GET_SBIC_asr(sc, asr); 1798 if (asr & SBIC_ASR_LCI) { 1799 printf("MSGOUT Failed!\n"); 1800 } 1801 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK); 1802 WAIT_CIP(sc); 1803 } 1804 1805 /* 1806 * Send the highest priority, scheduled message 1807 */ 1808 void 1809 wd33c93_msgout(struct wd33c93_softc *sc) 1810 { 1811 struct wd33c93_tinfo *ti; 1812 struct wd33c93_acb *acb = sc->sc_nexus; 1813 1814 if (acb == NULL) 1815 panic("MSGOUT with no nexus"); 1816 1817 if (sc->sc_omsglen == 0) { 1818 /* Pick up highest priority message */ 1819 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 1820 sc->sc_msgoutq |= sc->sc_msgout; 1821 sc->sc_msgpriq &= ~sc->sc_msgout; 1822 sc->sc_omsglen = 1; /* "Default" message len */ 1823 switch (sc->sc_msgout) { 1824 case SEND_SDTR: 1825 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1826 sc->sc_omsg[0] = MSG_EXTENDED; 1827 sc->sc_omsg[1] = MSG_EXT_SDTR_LEN; 1828 sc->sc_omsg[2] = MSG_EXT_SDTR; 1829 if (ti->flags & T_WANTSYNC) { 1830 sc->sc_omsg[3] = ti->period; 1831 sc->sc_omsg[4] = ti->offset; 1832 } else { 1833 sc->sc_omsg[3] = 0; 1834 sc->sc_omsg[4] = 0; 1835 } 1836 sc->sc_omsglen = 5; 1837 if ((sc->sc_flags & SBICF_SYNCNEGO) == 0) { 1838 if (ti->flags & T_WANTSYNC) 1839 ti->flags |= T_SYNCMODE; 1840 else 1841 ti->flags &= ~T_SYNCMODE; 1842 wd33c93_setsync(sc, ti); 1843 } 1844 break; 1845 case SEND_IDENTIFY: 1846 if (sc->sc_state != SBIC_CONNECTED) { 1847 printf("%s at line %d: no nexus\n", 1848 device_xname(sc->sc_dev), __LINE__); 1849 } 1850 sc->sc_omsg[0] = 1851 MSG_IDENTIFY(acb->xs->xs_periph->periph_lun, 0); 1852 break; 1853 case SEND_TAG: 1854 if (sc->sc_state != SBIC_CONNECTED) { 1855 printf("%s at line %d: no nexus\n", 1856 device_xname(sc->sc_dev), __LINE__); 1857 } 1858 sc->sc_omsg[0] = acb->tag_type; 1859 sc->sc_omsg[1] = acb->tag_id; 1860 sc->sc_omsglen = 2; 1861 break; 1862 case SEND_DEV_RESET: 1863 sc->sc_omsg[0] = MSG_BUS_DEV_RESET; 1864 ti = &sc->sc_tinfo[sc->target]; 1865 ti->flags &= ~T_SYNCMODE; 1866 wd33c93_update_xfer_mode(sc, sc->target); 1867 if ((ti->flags & T_NOSYNC) == 0) 1868 /* We can re-start sync negotiation */ 1869 ti->flags |= T_NEGOTIATE; 1870 break; 1871 case SEND_PARITY_ERROR: 1872 sc->sc_omsg[0] = MSG_PARITY_ERROR; 1873 break; 1874 case SEND_ABORT: 1875 sc->sc_flags |= SBICF_ABORTING; 1876 sc->sc_omsg[0] = MSG_ABORT; 1877 break; 1878 case SEND_INIT_DET_ERR: 1879 sc->sc_omsg[0] = MSG_INITIATOR_DET_ERR; 1880 break; 1881 case SEND_REJECT: 1882 sc->sc_omsg[0] = MSG_MESSAGE_REJECT; 1883 break; 1884 default: 1885 /* Wasn't expecting MSGOUT Phase */ 1886 sc->sc_omsg[0] = MSG_NOOP; 1887 break; 1888 } 1889 } 1890 1891 wd33c93_xfout(sc, sc->sc_omsglen, sc->sc_omsg); 1892 } 1893 1894 1895 /* 1896 * wd33c93_nextstate() 1897 * return: 1898 * SBIC_STATE_DONE == done 1899 * SBIC_STATE_RUNNING == working 1900 * SBIC_STATE_DISCONNECT == disconnected 1901 * SBIC_STATE_ERROR == error 1902 */ 1903 int 1904 wd33c93_nextstate(struct wd33c93_softc *sc, struct wd33c93_acb *acb, u_char csr, u_char asr) 1905 { 1906 SBIC_DEBUG(PHASE, ("next[a=%02x,c=%02x]: ",asr,csr)); 1907 1908 switch (csr) { 1909 1910 case SBIC_CSR_XFERRED | CMD_PHASE: 1911 case SBIC_CSR_MIS | CMD_PHASE: 1912 case SBIC_CSR_MIS_1 | CMD_PHASE: 1913 case SBIC_CSR_MIS_2 | CMD_PHASE: 1914 1915 if (wd33c93_xfout(sc, acb->clen, &acb->cmd)) 1916 goto abort; 1917 break; 1918 1919 case SBIC_CSR_XFERRED | STATUS_PHASE: 1920 case SBIC_CSR_MIS | STATUS_PHASE: 1921 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1922 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1923 1924 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 1925 1926 /* 1927 * this should be the normal i/o completion case. 1928 * get the status & cmd complete msg then let the 1929 * device driver look at what happened. 1930 */ 1931 wd33c93_xferdone(sc); 1932 1933 wd33c93_dma_stop(sc); 1934 1935 /* Fixup byte count to be passed to higher layer */ 1936 acb->dleft = (acb->flags & ACB_COMPLETE) ? 0 : 1937 sc->sc_dleft; 1938 1939 /* 1940 * Indicate to the upper layers that the command is done 1941 */ 1942 wd33c93_scsidone(sc, acb, sc->sc_status); 1943 1944 return SBIC_STATE_DONE; 1945 1946 1947 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 1948 case SBIC_CSR_MIS | DATA_IN_PHASE: 1949 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 1950 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 1951 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 1952 case SBIC_CSR_MIS | DATA_OUT_PHASE: 1953 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 1954 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 1955 /* 1956 * Verify that we expected to transfer data... 1957 */ 1958 if (acb->dleft <= 0) { 1959 printf("next: DATA phase with xfer count == %zd, asr:0x%02x csr:0x%02x\n", 1960 acb->dleft, asr, csr); 1961 goto abort; 1962 } 1963 1964 /* 1965 * Should we transfer using PIO or DMA ? 1966 */ 1967 if (acb->xs->xs_control & XS_CTL_POLL || 1968 sc->sc_flags & SBICF_NODMA) { 1969 /* Perform transfer using PIO */ 1970 int resid; 1971 1972 SBIC_DEBUG(DMA, ("PIO xfer: %d(%p:%zx)\n", sc->target, 1973 sc->sc_daddr, sc->sc_dleft)); 1974 1975 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 1976 /* data in */ 1977 resid = wd33c93_xfin(sc, sc->sc_dleft, 1978 sc->sc_daddr); 1979 else /* data out */ 1980 resid = wd33c93_xfout(sc, sc->sc_dleft, 1981 sc->sc_daddr); 1982 1983 sc->sc_daddr = (char *)sc->sc_daddr + 1984 (acb->dleft - resid); 1985 sc->sc_dleft = resid; 1986 } else { 1987 int datain = SBIC_PHASE(csr) == DATA_IN_PHASE; 1988 1989 /* Perform transfer using DMA */ 1990 wd33c93_dma_setup(sc, datain); 1991 1992 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI | 1993 sc->sc_dmamode); 1994 1995 SBIC_DEBUG(DMA, ("DMA xfer: %d(%p:%zx)\n", sc->target, 1996 sc->sc_daddr, sc->sc_dleft)); 1997 1998 /* Setup byte count for transfer */ 1999 SBIC_TC_PUT(sc, (unsigned)sc->sc_dleft); 2000 2001 /* Start the transfer */ 2002 SET_SBIC_cmd(sc, SBIC_CMD_XFER_INFO); 2003 2004 /* Start the DMA chip going */ 2005 sc->sc_tcnt = sc->sc_dmago(sc); 2006 2007 /* Indicate that we're in DMA mode */ 2008 sc->sc_flags |= SBICF_INDMA; 2009 } 2010 break; 2011 2012 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2013 case SBIC_CSR_MIS | MESG_IN_PHASE: 2014 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2015 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2016 2017 wd33c93_dma_stop(sc); 2018 2019 /* Handle a single message in... */ 2020 return wd33c93_msgin_phase(sc, 0); 2021 2022 case SBIC_CSR_MSGIN_W_ACK: 2023 2024 /* 2025 * We should never see this since it's handled in 2026 * 'wd33c93_msgin_phase()' but just for the sake of paranoia... 2027 */ 2028 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK); 2029 2030 printf("Acking unknown msgin CSR:%02x",csr); 2031 break; 2032 2033 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2034 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2035 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2036 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2037 2038 /* 2039 * Message out phase. ATN signal has been asserted 2040 */ 2041 wd33c93_dma_stop(sc); 2042 wd33c93_msgout(sc); 2043 return SBIC_STATE_RUNNING; 2044 2045 case SBIC_CSR_DISC: 2046 case SBIC_CSR_DISC_1: 2047 SBIC_DEBUG(RSEL, ("wd33c93next target %d disconnected\n", 2048 sc->target)); 2049 wd33c93_dma_stop(sc); 2050 2051 sc->sc_nexus = NULL; 2052 sc->sc_state = SBIC_IDLE; 2053 sc->sc_flags = 0; 2054 2055 ++sc->sc_tinfo[sc->target].dconns; 2056 ++sc->sc_disc; 2057 2058 if (acb->xs->xs_control & XS_CTL_POLL || wd33c93_nodisc) 2059 return SBIC_STATE_DISCONNECT; 2060 2061 /* Try to schedule another target */ 2062 wd33c93_sched(sc); 2063 2064 return SBIC_STATE_DISCONNECT; 2065 2066 case SBIC_CSR_RSLT_NI: 2067 case SBIC_CSR_RSLT_IFY: 2068 { 2069 /* 2070 * A reselection. 2071 * Note that since we don't enable Advanced Features (assuming 2072 * the WD chip is at least the 'A' revision), we're only ever 2073 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2074 * hell of it, we'll handle it anyway, for all the extra code 2075 * it needs... 2076 */ 2077 u_char newtarget, newlun; 2078 2079 if (sc->sc_flags & SBICF_INDMA) { 2080 printf("**** RESELECT WHILE DMA ACTIVE!!! ***\n"); 2081 wd33c93_dma_stop(sc); 2082 } 2083 2084 sc->sc_state = SBIC_RESELECTED; 2085 GET_SBIC_rselid(sc, newtarget); 2086 2087 /* check SBIC_RID_SIV? */ 2088 newtarget &= SBIC_RID_MASK; 2089 2090 if (csr == SBIC_CSR_RSLT_IFY) { 2091 /* Read Identify msg to avoid lockup */ 2092 GET_SBIC_data(sc, newlun); 2093 WAIT_CIP(sc); 2094 newlun &= SBIC_TLUN_MASK; 2095 sc->sc_msgify = MSG_IDENTIFY(newlun, 0); 2096 } else { 2097 /* 2098 * Need to read Identify message the hard way, assuming 2099 * the target even sends us one... 2100 */ 2101 for (newlun = 255; newlun; --newlun) { 2102 GET_SBIC_asr(sc, asr); 2103 if (asr & SBIC_ASR_INT) 2104 break; 2105 DELAY(10); 2106 } 2107 2108 /* If we didn't get an interrupt, something's up */ 2109 if ((asr & SBIC_ASR_INT) == 0) { 2110 printf("%s: Reselect without identify? asr %x\n", 2111 device_xname(sc->sc_dev), asr); 2112 newlun = 0; /* XXXX */ 2113 } else { 2114 /* 2115 * We got an interrupt, verify that it's a 2116 * change to message in phase, and if so 2117 * read the message. 2118 */ 2119 GET_SBIC_csr(sc,csr); 2120 2121 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2122 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2123 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2124 /* 2125 * Yup, gone to message in. 2126 * Fetch the target LUN 2127 */ 2128 sc->sc_msgify = 0; 2129 wd33c93_msgin_phase(sc, 1); 2130 newlun = sc->sc_msgify & SBIC_TLUN_MASK; 2131 } else { 2132 /* 2133 * Whoops! Target didn't go to msg_in 2134 * phase!! 2135 */ 2136 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2137 newlun = 0; /* XXXSCW */ 2138 } 2139 } 2140 } 2141 2142 /* Ok, we have the identity of the reselecting target. */ 2143 SBIC_DEBUG(RSEL, ("wd33c93next: reselect from targ %d lun %d", 2144 newtarget, newlun)); 2145 wd33c93_reselect(sc, newtarget, newlun, 0, 0); 2146 sc->sc_disc--; 2147 2148 if (csr == SBIC_CSR_RSLT_IFY) 2149 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK); 2150 break; 2151 } 2152 2153 default: 2154 abort: 2155 /* Something unexpected happened -- deal with it. */ 2156 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2157 2158 #ifdef DDB 2159 Debugger(); 2160 #endif 2161 2162 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI); 2163 if (acb->xs) 2164 wd33c93_error(sc, acb, "unexpected/abort"); 2165 wd33c93_abort(sc, acb, "next"); 2166 2167 if (sc->sc_flags & SBICF_INDMA) { 2168 wd33c93_dma_stop(sc); 2169 wd33c93_scsidone(sc, acb, STATUS_UNKNOWN); 2170 } 2171 return SBIC_STATE_ERROR; 2172 } 2173 return SBIC_STATE_RUNNING; 2174 } 2175 2176 2177 void 2178 wd33c93_reselect(struct wd33c93_softc *sc, int target, int lun, int tag_type, int tag_id) 2179 { 2180 2181 struct wd33c93_tinfo *ti; 2182 struct wd33c93_linfo *li; 2183 struct wd33c93_acb *acb; 2184 2185 if (sc->sc_nexus) { 2186 /* 2187 * Whoops! We've been reselected with a 2188 * command in progress! 2189 * The best we can do is to put the current 2190 * command back on the ready list and hope 2191 * for the best. 2192 */ 2193 SBIC_DEBUG(RSEL, ("%s: reselect with active command\n", 2194 device_xname(sc->sc_dev))); 2195 ti = &sc->sc_tinfo[sc->target]; 2196 li = TINFO_LUN(ti, sc->lun); 2197 li->state = L_STATE_IDLE; 2198 2199 wd33c93_dequeue(sc, sc->sc_nexus); 2200 TAILQ_INSERT_HEAD(&sc->ready_list, sc->sc_nexus, chain); 2201 sc->sc_nexus->flags |= ACB_READY; 2202 2203 sc->sc_nexus = NULL; 2204 } 2205 2206 /* Setup state for new nexus */ 2207 acb = NULL; 2208 sc->sc_flags = SBICF_SELECTED; 2209 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 2210 2211 ti = &sc->sc_tinfo[target]; 2212 li = TINFO_LUN(ti, lun); 2213 2214 if (li != NULL) { 2215 if (li->untagged != NULL && li->state) 2216 acb = li->untagged; 2217 else if (tag_type != MSG_SIMPLE_Q_TAG) { 2218 /* Wait for tag to come by during MESG_IN Phase */ 2219 sc->target = target; /* setup I_T_L nexus */ 2220 sc->lun = lun; 2221 sc->sc_state = SBIC_IDENTIFIED; 2222 return; 2223 } else if (tag_type) 2224 acb = li->queued[tag_id]; 2225 } 2226 2227 if (acb == NULL) { 2228 printf("%s: reselect from target %d lun %d tag %x:%x " 2229 "with no nexus; sending ABORT\n", 2230 device_xname(sc->sc_dev), target, lun, tag_type, tag_id); 2231 goto abort; 2232 } 2233 2234 sc->target = target; 2235 sc->lun = lun; 2236 sc->sc_nexus = acb; 2237 sc->sc_state = SBIC_CONNECTED; 2238 2239 if (!wd33c93_dmaok(sc, acb->xs)) 2240 sc->sc_flags |= SBICF_NODMA; 2241 2242 /* Do an implicit RESTORE POINTERS. */ 2243 sc->sc_daddr = acb->daddr; 2244 sc->sc_dleft = acb->dleft; 2245 2246 /* Set sync modes for new target */ 2247 wd33c93_setsync(sc, ti); 2248 2249 if (acb->flags & ACB_RESET) 2250 wd33c93_sched_msgout(sc, SEND_DEV_RESET); 2251 else if (acb->flags & ACB_ABORT) 2252 wd33c93_sched_msgout(sc, SEND_ABORT); 2253 return; 2254 2255 abort: 2256 wd33c93_sched_msgout(sc, SEND_ABORT); 2257 return; 2258 2259 } 2260 2261 void 2262 wd33c93_update_xfer_mode(struct wd33c93_softc *sc, int target) 2263 { 2264 struct wd33c93_tinfo *ti = &sc->sc_tinfo[target]; 2265 struct scsipi_xfer_mode xm; 2266 2267 xm.xm_target = target; 2268 xm.xm_mode = 0; 2269 xm.xm_period = 0; 2270 xm.xm_offset = 0; 2271 2272 if (ti->flags & T_SYNCMODE) { 2273 xm.xm_mode |= PERIPH_CAP_SYNC; 2274 xm.xm_period = ti->period; 2275 xm.xm_offset = ti->offset; 2276 } 2277 2278 if ((ti->flags & (T_NODISC|T_TAG)) == T_TAG) 2279 xm.xm_mode |= PERIPH_CAP_TQING; 2280 2281 SBIC_DEBUG(SYNC, ("wd33c93_update_xfer_mode: reporting target %d %s\n", 2282 xm.xm_target, 2283 (xm.xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 2284 2285 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 2286 } 2287 2288 void 2289 wd33c93_timeout_callout(void *arg) 2290 { 2291 struct wd33c93_acb *acb = arg; 2292 int x; 2293 2294 x = splbio(); 2295 wd33c93_timeout(acb); 2296 splx(x); 2297 } 2298 2299 /** 2300 * @brief Handle timeout events. 2301 * 2302 * Note: this can be run from outside splbio(), it will acquire it as needed. 2303 * 2304 * Returns 1 if the transfer was aborted and the caller should 2305 * reschedule or complete the acb, 0 otherwise. 2306 */ 2307 int 2308 wd33c93_timeout(struct wd33c93_acb *acb) 2309 { 2310 struct scsipi_xfer *xs = acb->xs; 2311 struct scsipi_periph *periph = xs->xs_periph; 2312 struct wd33c93_softc *sc = 2313 device_private(periph->periph_channel->chan_adapter->adapt_dev); 2314 int s, asr; 2315 int ret; 2316 2317 s = splbio(); 2318 2319 GET_SBIC_asr(sc, asr); 2320 2321 scsipi_printaddr(periph); 2322 printf("%s: timed out; asr=0x%02x [acb %p (flags 0x%x, dleft %zx)], " 2323 "<state %d, nexus %p, resid %lx, msg(q %x,o %x)>", 2324 device_xname(sc->sc_dev), asr, acb, acb->flags, acb->dleft, 2325 sc->sc_state, sc->sc_nexus, (long)sc->sc_dleft, 2326 sc->sc_msgpriq, sc->sc_msgout); 2327 2328 if (asr & SBIC_ASR_INT) { 2329 /* We need to service a missed IRQ */ 2330 wd33c93_intr(sc); 2331 ret = 0; 2332 } else { 2333 (void) wd33c93_abort(sc, acb, "timeout"); 2334 ret = 1; 2335 } 2336 splx(s); 2337 2338 return (ret); 2339 } 2340 2341 2342 void 2343 wd33c93_watchdog(void *arg) 2344 { 2345 struct wd33c93_softc *sc = arg; 2346 struct wd33c93_tinfo *ti; 2347 struct wd33c93_linfo *li; 2348 int t, s, l; 2349 /* scrub LUN's that have not been used in the last 10min. */ 2350 time_t old = time_second - (10 * 60); 2351 2352 for (t = 0; t < SBIC_NTARG; t++) { 2353 ti = &sc->sc_tinfo[t]; 2354 for (l = 0; l < SBIC_NLUN; l++) { 2355 s = splbio(); 2356 li = TINFO_LUN(ti, l); 2357 if (li && li->last_used < old && 2358 li->untagged == NULL && li->used == 0) { 2359 ti->lun[li->lun] = NULL; 2360 free(li, M_DEVBUF); 2361 } 2362 splx(s); 2363 } 2364 } 2365 callout_reset(&sc->sc_watchdog, 60 * hz, wd33c93_watchdog, sc); 2366 } 2367 2368 2369 #ifdef DEBUG 2370 void 2371 wd33c93_hexdump(u_char *buf, int len) 2372 { 2373 printf("{%d}:", len); 2374 while (len--) 2375 printf(" %02x", *buf++); 2376 printf("\n"); 2377 } 2378 2379 2380 void 2381 wd33c93_print_csr(u_char csr) 2382 { 2383 switch (SCSI_PHASE(csr)) { 2384 case CMD_PHASE: 2385 printf("CMD_PHASE\n"); 2386 break; 2387 2388 case STATUS_PHASE: 2389 printf("STATUS_PHASE\n"); 2390 break; 2391 2392 case DATA_IN_PHASE: 2393 printf("DATAIN_PHASE\n"); 2394 break; 2395 2396 case DATA_OUT_PHASE: 2397 printf("DATAOUT_PHASE\n"); 2398 break; 2399 2400 case MESG_IN_PHASE: 2401 printf("MESG_IN_PHASE\n"); 2402 break; 2403 2404 case MESG_OUT_PHASE: 2405 printf("MESG_OUT_PHASE\n"); 2406 break; 2407 2408 default: 2409 switch (csr) { 2410 case SBIC_CSR_DISC_1: 2411 printf("DISC_1\n"); 2412 break; 2413 2414 case SBIC_CSR_RSLT_NI: 2415 printf("RESELECT_NO_IFY\n"); 2416 break; 2417 2418 case SBIC_CSR_RSLT_IFY: 2419 printf("RESELECT_IFY\n"); 2420 break; 2421 2422 case SBIC_CSR_SLT: 2423 printf("SELECT\n"); 2424 break; 2425 2426 case SBIC_CSR_SLT_ATN: 2427 printf("SELECT, ATN\n"); 2428 break; 2429 2430 case SBIC_CSR_UNK_GROUP: 2431 printf("UNK_GROUP\n"); 2432 break; 2433 2434 default: 2435 printf("UNKNOWN csr=%02x\n", csr); 2436 } 2437 } 2438 } 2439 #endif 2440
Indexes created Sun Oct 25 00:26:45 UTC 2026