1 /* $NetBSD: if_gm.c,v 1.60 2025/10/04 04:44:20 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_gm.c,v 1.60 2025/10/04 04:44:20 thorpej Exp $"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/device.h> 36 #include <sys/ioctl.h> 37 #include <sys/kernel.h> 38 #include <sys/mbuf.h> 39 #include <sys/socket.h> 40 #include <sys/systm.h> 41 #include <sys/callout.h> 42 43 #include <sys/rndsource.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 49 #include <net/bpf.h> 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/if_inarp.h> 54 #endif 55 56 #include <dev/mii/mii.h> 57 #include <dev/mii/miivar.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/ofw/openfirm.h> 64 #include <macppc/dev/if_gmreg.h> 65 #include <machine/pio.h> 66 #include <powerpc/oea/spr.h> 67 68 #define NTXBUF 4 69 #define NRXBUF 32 70 71 struct gmac_softc { 72 device_t sc_dev; 73 struct ethercom sc_ethercom; 74 vaddr_t sc_reg; 75 struct gmac_dma *sc_txlist; 76 struct gmac_dma *sc_rxlist; 77 int sc_txnext; 78 bool sc_txbusy; 79 int sc_rxlast; 80 void *sc_txbuf[NTXBUF]; 81 void *sc_rxbuf[NRXBUF]; 82 struct mii_data sc_mii; 83 struct callout sc_tick_ch; 84 char sc_laddr[6]; 85 86 krndsource_t sc_rnd_source; /* random source */ 87 }; 88 89 #define sc_if sc_ethercom.ec_if 90 91 int gmac_match(device_t, cfdata_t, void *); 92 void gmac_attach(device_t, device_t, void *); 93 94 static inline u_int gmac_read_reg(struct gmac_softc *, int); 95 static inline void gmac_write_reg(struct gmac_softc *, int, u_int); 96 97 static inline void gmac_start_txdma(struct gmac_softc *); 98 static inline void gmac_start_rxdma(struct gmac_softc *); 99 static inline void gmac_stop_txdma(struct gmac_softc *); 100 static inline void gmac_stop_rxdma(struct gmac_softc *); 101 102 int gmac_intr(void *); 103 void gmac_tint(struct gmac_softc *); 104 void gmac_rint(struct gmac_softc *); 105 struct mbuf * gmac_get(struct gmac_softc *, void *, int); 106 void gmac_start(struct ifnet *); 107 int gmac_put(struct gmac_softc *, void *, struct mbuf *); 108 109 void gmac_stop(struct gmac_softc *); 110 void gmac_reset(struct gmac_softc *); 111 void gmac_init(struct gmac_softc *); 112 void gmac_init_mac(struct gmac_softc *); 113 void gmac_setladrf(struct gmac_softc *); 114 115 int gmac_ioctl(struct ifnet *, u_long, void *); 116 void gmac_watchdog(struct ifnet *); 117 118 int gmac_mii_readreg(device_t, int, int, uint16_t *); 119 int gmac_mii_writereg(device_t, int, int, uint16_t); 120 void gmac_mii_statchg(struct ifnet *); 121 void gmac_mii_tick(void *); 122 123 CFATTACH_DECL_NEW(gm, sizeof(struct gmac_softc), 124 gmac_match, gmac_attach, NULL, NULL); 125 126 int 127 gmac_match(device_t parent, cfdata_t match, void *aux) 128 { 129 struct pci_attach_args *pa = aux; 130 131 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 132 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 133 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2 || 134 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC3)) 135 return 1; 136 137 return 0; 138 } 139 140 void 141 gmac_attach(device_t parent, device_t self, void *aux) 142 { 143 struct gmac_softc * const sc = device_private(self); 144 struct pci_attach_args * const pa = aux; 145 struct ifnet * const ifp = &sc->sc_if; 146 struct mii_data * const mii = &sc->sc_mii; 147 pci_intr_handle_t ih; 148 const char *intrstr = NULL; 149 const char * const xname = device_xname(self); 150 int node, i; 151 char *p; 152 struct gmac_dma *dp; 153 uint32_t reg[10]; 154 u_char laddr[6]; 155 char buf[PCI_INTRSTR_LEN]; 156 157 sc->sc_dev = self; 158 159 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 160 if (node == 0) { 161 printf(": cannot find gmac node\n"); 162 return; 163 } 164 165 if (! ether_getaddr(self, laddr)) { 166 printf(": failed to get MAC address\n"); 167 return; 168 } 169 170 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 171 172 memcpy(sc->sc_laddr, laddr, sizeof laddr); 173 sc->sc_reg = reg[2]; 174 175 if (pci_intr_map(pa, &ih)) { 176 printf(": unable to map interrupt\n"); 177 return; 178 } 179 intrstr = pci_intr_string(pa->pa_pc, ih, buf, sizeof(buf)); 180 181 if (pci_intr_establish_xname(pa->pa_pc, ih, IPL_NET, gmac_intr, sc, 182 device_xname(self)) == NULL) { 183 printf(": unable to establish interrupt"); 184 if (intrstr) 185 printf(" at %s", intrstr); 186 printf("\n"); 187 return; 188 } 189 190 /* Setup packet buffers and DMA descriptors. */ 191 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_WAITOK); 192 p = (void *)roundup((vaddr_t)p, 0x800); 193 memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 194 195 sc->sc_rxlist = (void *)p; 196 p += 0x800; 197 sc->sc_txlist = (void *)p; 198 p += 0x800; 199 200 dp = sc->sc_rxlist; 201 for (i = 0; i < NRXBUF; i++) { 202 sc->sc_rxbuf[i] = p; 203 dp->address = htole32(vtophys((vaddr_t)p)); 204 dp->cmd = htole32(GMAC_OWN); 205 dp++; 206 p += 2048; 207 } 208 209 dp = sc->sc_txlist; 210 for (i = 0; i < NTXBUF; i++) { 211 sc->sc_txbuf[i] = p; 212 dp->address = htole32(vtophys((vaddr_t)p)); 213 dp++; 214 p += 2048; 215 } 216 217 aprint_normal(": Ethernet address %s\n", ether_sprintf(laddr)); 218 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 219 220 callout_init(&sc->sc_tick_ch, 0); 221 222 gmac_reset(sc); 223 gmac_init_mac(sc); 224 225 memcpy(ifp->if_xname, xname, IFNAMSIZ); 226 ifp->if_softc = sc; 227 ifp->if_ioctl = gmac_ioctl; 228 ifp->if_start = gmac_start; 229 ifp->if_watchdog = gmac_watchdog; 230 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 231 IFQ_SET_READY(&ifp->if_snd); 232 233 mii->mii_ifp = ifp; 234 mii->mii_readreg = gmac_mii_readreg; 235 mii->mii_writereg = gmac_mii_writereg; 236 mii->mii_statchg = gmac_mii_statchg; 237 238 sc->sc_ethercom.ec_mii = mii; 239 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 240 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 241 242 /* Choose a default media. */ 243 if (LIST_FIRST(&mii->mii_phys) == NULL) { 244 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 245 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 246 } else 247 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 248 249 if_attach(ifp); 250 if_deferred_start_init(ifp, NULL); 251 ether_ifattach(ifp, laddr); 252 rnd_attach_source(&sc->sc_rnd_source, xname, RND_TYPE_NET, 253 RND_FLAG_DEFAULT); 254 } 255 256 u_int 257 gmac_read_reg(struct gmac_softc *sc, int reg) 258 { 259 return in32rb(sc->sc_reg + reg); 260 } 261 262 void 263 gmac_write_reg(struct gmac_softc *sc, int reg, u_int val) 264 { 265 out32rb(sc->sc_reg + reg, val); 266 } 267 268 void 269 gmac_start_txdma(struct gmac_softc *sc) 270 { 271 u_int x; 272 273 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 274 x |= 1; 275 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 276 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 277 x |= 1; 278 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 279 } 280 281 void 282 gmac_start_rxdma(struct gmac_softc *sc) 283 { 284 u_int x; 285 286 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 287 x |= 1; 288 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 289 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 290 x |= 1; 291 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 292 } 293 294 void 295 gmac_stop_txdma(struct gmac_softc *sc) 296 { 297 u_int x; 298 299 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 300 x &= ~1; 301 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 302 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 303 x &= ~1; 304 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 305 } 306 307 void 308 gmac_stop_rxdma(struct gmac_softc *sc) 309 { 310 u_int x; 311 312 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 313 x &= ~1; 314 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 315 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 316 x &= ~1; 317 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 318 } 319 320 int 321 gmac_intr(void *v) 322 { 323 struct gmac_softc *sc = v; 324 u_int status; 325 326 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 327 if (status == 0) 328 return 0; 329 330 if (status & GMAC_INT_RXDONE) 331 gmac_rint(sc); 332 333 if (status & GMAC_INT_TXEMPTY) 334 gmac_tint(sc); 335 336 rnd_add_uint32(&sc->sc_rnd_source, status); 337 return 1; 338 } 339 340 void 341 gmac_tint(struct gmac_softc *sc) 342 { 343 struct ifnet *ifp = &sc->sc_if; 344 345 sc->sc_txbusy = false; 346 ifp->if_timer = 0; 347 if_schedule_deferred_start(ifp); 348 } 349 350 void 351 gmac_rint(struct gmac_softc *sc) 352 { 353 struct ifnet *ifp = &sc->sc_if; 354 volatile struct gmac_dma *dp; 355 struct mbuf *m; 356 int i, j, len; 357 u_int cmd; 358 359 for (i = sc->sc_rxlast;; i++) { 360 if (i == NRXBUF) 361 i = 0; 362 363 dp = &sc->sc_rxlist[i]; 364 cmd = le32toh(dp->cmd); 365 if (cmd & GMAC_OWN) 366 break; 367 len = (cmd >> 16) & GMAC_LEN_MASK; 368 len -= 4; /* CRC */ 369 370 if (le32toh(dp->cmd_hi) & 0x40000000) { 371 if_statinc(ifp, if_ierrors); 372 goto next; 373 } 374 375 m = gmac_get(sc, sc->sc_rxbuf[i], len); 376 if (m == NULL) { 377 if_statinc(ifp, if_ierrors); 378 goto next; 379 } 380 381 if_percpuq_enqueue(ifp->if_percpuq, m); 382 383 next: 384 dp->cmd_hi = 0; 385 __asm volatile ("sync"); 386 dp->cmd = htole32(GMAC_OWN); 387 } 388 sc->sc_rxlast = i; 389 390 /* XXX Make sure free buffers have GMAC_OWN. */ 391 i++; 392 for (j = 1; j < NRXBUF; j++) { 393 if (i == NRXBUF) 394 i = 0; 395 dp = &sc->sc_rxlist[i++]; 396 dp->cmd = htole32(GMAC_OWN); 397 } 398 } 399 400 struct mbuf * 401 gmac_get(struct gmac_softc *sc, void *pkt, int totlen) 402 { 403 struct mbuf *m; 404 struct mbuf *top, **mp; 405 int len; 406 407 MGETHDR(m, M_DONTWAIT, MT_DATA); 408 if (m == 0) 409 return 0; 410 m_set_rcvif(m, &sc->sc_if); 411 m->m_pkthdr.len = totlen; 412 len = MHLEN; 413 top = 0; 414 mp = ⊤ 415 416 while (totlen > 0) { 417 if (top) { 418 MGET(m, M_DONTWAIT, MT_DATA); 419 if (m == 0) { 420 m_freem(top); 421 return 0; 422 } 423 len = MLEN; 424 } 425 if (totlen >= MINCLSIZE) { 426 MCLGET(m, M_DONTWAIT); 427 if ((m->m_flags & M_EXT) == 0) { 428 m_free(m); 429 m_freem(top); 430 return 0; 431 } 432 len = MCLBYTES; 433 } 434 m->m_len = len = imin(totlen, len); 435 memcpy(mtod(m, void *), pkt, len); 436 pkt = (char *)pkt + len; 437 totlen -= len; 438 *mp = m; 439 mp = &m->m_next; 440 } 441 442 return top; 443 } 444 445 void 446 gmac_start(struct ifnet *ifp) 447 { 448 struct gmac_softc *sc = ifp->if_softc; 449 struct mbuf *m; 450 void *buff; 451 int i, tlen; 452 volatile struct gmac_dma *dp; 453 454 if ((ifp->if_flags & IFF_RUNNING) == 0) 455 return; 456 457 while (!sc->sc_txbusy) { 458 IFQ_DEQUEUE(&ifp->if_snd, m); 459 if (m == 0) 460 break; 461 462 /* 5 seconds to watch for failing to transmit */ 463 ifp->if_timer = 5; 464 if_statinc(ifp, if_opackets); /* # of pkts */ 465 466 i = sc->sc_txnext; 467 buff = sc->sc_txbuf[i]; 468 tlen = gmac_put(sc, buff, m); 469 470 dp = &sc->sc_txlist[i]; 471 dp->cmd_hi = 0; 472 dp->address_hi = 0; 473 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 474 475 i++; 476 if (i == NTXBUF) 477 i = 0; 478 __asm volatile ("sync"); 479 480 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 481 sc->sc_txnext = i; 482 483 /* 484 * If BPF is listening on this interface, let it see the 485 * packet before we commit it to the wire. 486 */ 487 bpf_mtap(ifp, m, BPF_D_OUT); 488 m_freem(m); 489 490 i++; 491 if (i == NTXBUF) 492 i = 0; 493 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 494 sc->sc_txbusy = true; 495 break; 496 } 497 } 498 } 499 500 int 501 gmac_put(struct gmac_softc *sc, void *buff, struct mbuf *m) 502 { 503 int len, tlen = 0; 504 505 for (; m; m = m->m_next) { 506 len = m->m_len; 507 if (len == 0) 508 continue; 509 memcpy(buff, mtod(m, void *), len); 510 buff = (char *)buff + len; 511 tlen += len; 512 } 513 if (tlen > 2048) 514 panic("%s: gmac_put packet overflow", device_xname(sc->sc_dev)); 515 516 return tlen; 517 } 518 519 void 520 gmac_reset(struct gmac_softc *sc) 521 { 522 int i, s; 523 524 s = splnet(); 525 526 gmac_stop_txdma(sc); 527 gmac_stop_rxdma(sc); 528 529 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 530 for (i = 10; i > 0; i--) { 531 delay(300000); /* XXX long delay */ 532 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 533 break; 534 } 535 if (i == 0) 536 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 537 538 sc->sc_txnext = 0; 539 sc->sc_rxlast = 0; 540 for (i = 0; i < NRXBUF; i++) 541 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 542 __asm volatile ("sync"); 543 544 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 545 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 546 vtophys((vaddr_t)sc->sc_txlist)); 547 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 548 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 549 vtophys((vaddr_t)sc->sc_rxlist)); 550 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 551 552 splx(s); 553 } 554 555 void 556 gmac_stop(struct gmac_softc *sc) 557 { 558 struct ifnet *ifp = &sc->sc_if; 559 int s; 560 561 s = splnet(); 562 563 callout_stop(&sc->sc_tick_ch); 564 mii_down(&sc->sc_mii); 565 566 gmac_stop_txdma(sc); 567 gmac_stop_rxdma(sc); 568 569 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 570 571 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 572 ifp->if_timer = 0; 573 574 splx(s); 575 } 576 577 void 578 gmac_init_mac(struct gmac_softc *sc) 579 { 580 int i, tb; 581 char *laddr = sc->sc_laddr; 582 583 if ((mfpvr() >> 16) == MPC601) 584 tb = mfrtcl(); 585 else 586 tb = mftbl(); 587 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 588 589 /* init-mii */ 590 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 591 gmac_mii_writereg(sc->sc_dev, 0, 0, 0x1000); 592 593 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 594 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 595 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 596 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 597 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 598 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 599 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 600 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 601 gmac_write_reg(sc, GMAC_PASIZE, 7); 602 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 603 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT, 0x10); 604 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 605 606 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 607 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 608 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 609 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 610 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 611 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 612 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 613 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 614 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 615 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 616 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 617 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 618 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 619 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 620 621 for (i = 0; i < 0x6c; i += 4) 622 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 623 624 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 625 626 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 627 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 628 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 629 } else { 630 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 631 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 632 } 633 634 if (0) /* g-bit? */ 635 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 636 else 637 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 638 } 639 640 void 641 gmac_setladrf(struct gmac_softc *sc) 642 { 643 struct ifnet *ifp = &sc->sc_if; 644 struct ether_multi *enm; 645 struct ether_multistep step; 646 struct ethercom *ec = &sc->sc_ethercom; 647 uint32_t crc; 648 uint32_t hash[16]; 649 u_int v; 650 int i; 651 652 /* Clear hash table */ 653 for (i = 0; i < 16; i++) 654 hash[i] = 0; 655 656 /* Get current RX configuration */ 657 v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 658 659 if ((ifp->if_flags & IFF_PROMISC) != 0) { 660 /* Turn on promiscuous mode; turn off the hash filter */ 661 v |= GMAC_RXMAC_PR; 662 v &= ~GMAC_RXMAC_HEN; 663 ifp->if_flags |= IFF_ALLMULTI; 664 goto chipit; 665 } 666 667 /* Turn off promiscuous mode; turn on the hash filter */ 668 v &= ~GMAC_RXMAC_PR; 669 v |= GMAC_RXMAC_HEN; 670 671 /* 672 * Set up multicast address filter by passing all multicast addresses 673 * through a crc generator, and then using the high order 8 bits as an 674 * index into the 256 bit logical address filter. The high order bit 675 * selects the word, while the rest of the bits select the bit within 676 * the word. 677 */ 678 679 ETHER_LOCK(ec); 680 ETHER_FIRST_MULTI(step, ec, enm); 681 while (enm != NULL) { 682 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 683 /* 684 * We must listen to a range of multicast addresses. 685 * For now, just accept all multicasts, rather than 686 * trying to set only those filter bits needed to match 687 * the range. (At this time, the only use of address 688 * ranges is for IP multicast routing, for which the 689 * range is big enough to require all bits set.) 690 */ 691 for (i = 0; i < 16; i++) 692 hash[i] = 0xffff; 693 ifp->if_flags |= IFF_ALLMULTI; 694 ETHER_UNLOCK(ec); 695 goto chipit; 696 } 697 698 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 699 700 /* Just want the 8 most significant bits. */ 701 crc >>= 24; 702 703 /* Set the corresponding bit in the filter. */ 704 hash[crc >> 4] |= 1 << (crc & 0xf); 705 706 ETHER_NEXT_MULTI(step, enm); 707 } 708 ETHER_UNLOCK(ec); 709 710 ifp->if_flags &= ~IFF_ALLMULTI; 711 712 chipit: 713 /* Now load the hash table into the chip */ 714 for (i = 0; i < 16; i++) 715 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 716 717 gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 718 } 719 720 void 721 gmac_init(struct gmac_softc *sc) 722 { 723 struct ifnet *ifp = &sc->sc_if; 724 725 gmac_stop_txdma(sc); 726 gmac_stop_rxdma(sc); 727 728 gmac_init_mac(sc); 729 gmac_setladrf(sc); 730 731 gmac_start_txdma(sc); 732 gmac_start_rxdma(sc); 733 734 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 735 736 ifp->if_flags |= IFF_RUNNING; 737 sc->sc_txbusy = false; 738 ifp->if_timer = 0; 739 740 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 741 742 gmac_start(ifp); 743 } 744 745 int 746 gmac_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 747 { 748 struct gmac_softc *sc = ifp->if_softc; 749 struct ifaddr *ifa = (struct ifaddr *)data; 750 int s, error = 0; 751 752 s = splnet(); 753 754 switch (cmd) { 755 756 case SIOCINITIFADDR: 757 ifp->if_flags |= IFF_UP; 758 759 gmac_init(sc); 760 switch (ifa->ifa_addr->sa_family) { 761 #ifdef INET 762 case AF_INET: 763 arp_ifinit(ifp, ifa); 764 break; 765 #endif 766 default: 767 break; 768 } 769 break; 770 771 case SIOCSIFFLAGS: 772 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 773 break; 774 /* XXX see the comment in ed_ioctl() about code re-use */ 775 if ((ifp->if_flags & IFF_UP) == 0 && 776 (ifp->if_flags & IFF_RUNNING) != 0) { 777 /* 778 * If interface is marked down and it is running, then 779 * stop it. 780 */ 781 gmac_stop(sc); 782 ifp->if_flags &= ~IFF_RUNNING; 783 } else if ((ifp->if_flags & IFF_UP) != 0 && 784 (ifp->if_flags & IFF_RUNNING) == 0) { 785 /* 786 * If interface is marked up and it is stopped, then 787 * start it. 788 */ 789 gmac_init(sc); 790 } else { 791 /* 792 * Reset the interface to pick up changes in any other 793 * flags that affect hardware registers. 794 */ 795 gmac_reset(sc); 796 gmac_init(sc); 797 } 798 #ifdef GMAC_DEBUG 799 if (ifp->if_flags & IFF_DEBUG) 800 sc->sc_flags |= GMAC_DEBUGFLAG; 801 #endif 802 break; 803 804 default: 805 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 806 /* 807 * Multicast list has changed; set the hardware filter 808 * accordingly. 809 */ 810 if (ifp->if_flags & IFF_RUNNING) { 811 gmac_init(sc); 812 /* gmac_setladrf(sc); */ 813 } 814 error = 0; 815 } 816 break; 817 } 818 819 splx(s); 820 return error; 821 } 822 823 void 824 gmac_watchdog(struct ifnet *ifp) 825 { 826 struct gmac_softc *sc = ifp->if_softc; 827 828 printf("%s: device timeout\n", ifp->if_xname); 829 if_statinc(ifp, if_oerrors); 830 831 gmac_reset(sc); 832 gmac_init(sc); 833 } 834 835 int 836 gmac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 837 { 838 struct gmac_softc *sc = device_private(self); 839 int i; 840 841 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 842 0x60020000 | (phy << 23) | (reg << 18)); 843 844 for (i = 1000; i >= 0; i -= 10) { 845 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 846 break; 847 delay(10); 848 } 849 if (i < 0) { 850 aprint_error_dev(sc->sc_dev, "gmac_mii_readreg: timeout\n"); 851 return ETIMEDOUT; 852 } 853 854 *val = gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 855 return 0; 856 } 857 858 int 859 gmac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 860 { 861 struct gmac_softc *sc = device_private(self); 862 int i; 863 864 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 865 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 866 867 for (i = 1000; i >= 0; i -= 10) { 868 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 869 break; 870 delay(10); 871 } 872 if (i < 0) { 873 aprint_error_dev(sc->sc_dev, "gmac_mii_writereg: timeout\n"); 874 return ETIMEDOUT; 875 } 876 877 return 0; 878 } 879 880 void 881 gmac_mii_statchg(struct ifnet *ifp) 882 { 883 struct gmac_softc *sc = ifp->if_softc; 884 885 gmac_stop_txdma(sc); 886 gmac_stop_rxdma(sc); 887 888 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 889 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 890 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 891 } else { 892 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 893 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 894 } 895 896 if (0) /* g-bit? */ 897 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 898 else 899 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 900 901 gmac_start_txdma(sc); 902 gmac_start_rxdma(sc); 903 } 904 905 void 906 gmac_mii_tick(void *v) 907 { 908 struct gmac_softc *sc = v; 909 int s; 910 911 s = splnet(); 912 mii_tick(&sc->sc_mii); 913 splx(s); 914 915 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 916 } 917
Indexes created Mon Oct 26 00:26:21 UTC 2026