1 /* $NetBSD: ohci_pci.c,v 1.61 2025/03/31 14:48:50 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ohci_pci.c,v 1.61 2025/03/31 14:48:50 riastradh Exp $"); 35 36 #include "ehci.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/proc.h> 43 #include <sys/queue.h> 44 45 #include <sys/bus.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/usb_pci.h> 50 51 #include <dev/usb/usb.h> 52 #include <dev/usb/usbdi.h> 53 #include <dev/usb/usbdivar.h> 54 #include <dev/usb/usb_mem.h> 55 56 #include <dev/usb/ohcireg.h> 57 #include <dev/usb/ohcivar.h> 58 59 struct ohci_pci_softc { 60 ohci_softc_t sc; 61 #if NEHCI > 0 62 struct usb_pci sc_pci; 63 #endif 64 pci_chipset_tag_t sc_pc; 65 pcitag_t sc_tag; 66 void *sc_ih; /* interrupt vectoring */ 67 }; 68 69 static int 70 ohci_pci_match(device_t parent, cfdata_t match, void *aux) 71 { 72 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 73 74 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 75 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 76 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI) 77 return 1; 78 79 return 0; 80 } 81 82 static void 83 ohci_pci_attach(device_t parent, device_t self, void *aux) 84 { 85 struct ohci_pci_softc *sc = device_private(self); 86 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 87 pci_chipset_tag_t pc = pa->pa_pc; 88 pcitag_t tag = pa->pa_tag; 89 char const *intrstr; 90 pci_intr_handle_t ih; 91 pcireg_t csr; 92 char intrbuf[PCI_INTRSTR_LEN]; 93 94 sc->sc.sc_dev = self; 95 sc->sc.sc_bus.ub_hcpriv = sc; 96 97 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 98 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_USB) { 99 sc->sc.sc_flags = OHCIF_SUPERIO; 100 } 101 102 pci_aprint_devinfo(pa, "USB Controller"); 103 104 /* check if memory space access is enabled */ 105 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 106 #ifdef DEBUG 107 printf("csr: %08x\n", csr); 108 #endif 109 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { 110 aprint_error_dev(self, "memory access is disabled\n"); 111 return; 112 } 113 114 /* Map I/O registers */ 115 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 116 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 117 sc->sc.sc_size = 0; 118 aprint_error_dev(self, "can't map mem space\n"); 119 return; 120 } 121 122 /* Disable interrupts, so we don't get any spurious ones. */ 123 bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE, 124 OHCI_ALL_INTRS); 125 126 sc->sc_pc = pc; 127 sc->sc_tag = tag; 128 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; 129 130 /* Enable the device. */ 131 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 132 csr | PCI_COMMAND_MASTER_ENABLE); 133 134 /* Map and establish the interrupt. */ 135 if (pci_intr_map(pa, &ih)) { 136 aprint_error_dev(self, "couldn't map interrupt\n"); 137 goto fail; 138 } 139 140 /* 141 * Allocate IRQ 142 */ 143 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 144 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_USB, ohci_intr, sc, 145 device_xname(self)); 146 if (sc->sc_ih == NULL) { 147 aprint_error_dev(self, "couldn't establish interrupt"); 148 if (intrstr != NULL) 149 aprint_error(" at %s", intrstr); 150 aprint_error("\n"); 151 goto fail; 152 } 153 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 154 155 int err = ohci_init(&sc->sc); 156 if (err) { 157 aprint_error_dev(self, "init failed, error=%d\n", err); 158 goto fail; 159 } 160 161 #if NEHCI > 0 162 usb_pci_add(&sc->sc_pci, pa, self); 163 #endif 164 165 if (!pmf_device_register1(self, ohci_suspend, ohci_resume, 166 ohci_shutdown)) 167 aprint_error_dev(self, "couldn't establish power handler\n"); 168 169 /* Attach usb device. */ 170 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint, 171 CFARGS_NONE); 172 return; 173 174 fail: 175 if (sc->sc_ih) { 176 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 177 sc->sc_ih = NULL; 178 } 179 if (sc->sc.sc_size) { 180 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 181 sc->sc.sc_size = 0; 182 } 183 return; 184 } 185 186 static int 187 ohci_pci_detach(device_t self, int flags) 188 { 189 struct ohci_pci_softc *sc = device_private(self); 190 int error; 191 192 /* 193 * Detach the USB child first. Disconnects all USB devices and 194 * prevents connecting new ones. 195 */ 196 error = config_detach_children(self, flags); 197 if (error) 198 return error; 199 200 /* 201 * Stop listing this as a possible companion controller for 202 * ehci(4). 203 */ 204 #if NEHCI > 0 205 usb_pci_rem(&sc->sc_pci); 206 #endif 207 208 /* 209 * Shut down the controller and block interrupts at the device 210 * level. Once we have shut down the controller, the shutdown 211 * handler no longer needed -- deregister it from PMF. 212 * (Harmless to call ohci_shutdown more than once, so no 213 * synchronization needed.) 214 */ 215 ohci_shutdown(self, 0); 216 pmf_device_deregister(self); 217 218 /* 219 * Interrupts are blocked at the device level by ohci_shutdown. 220 * Disestablish the interrupt handler. This waits for it to 221 * complete on all CPUs. 222 */ 223 if (sc->sc_ih != NULL) { 224 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 225 sc->sc_ih = NULL; 226 } 227 228 /* 229 * Free the bus-independent ohci(4) state now that the 230 * interrupt handler has ceased to run on all CPUs. 231 */ 232 ohci_detach(&sc->sc); 233 234 /* 235 * Unmap the registers now that we're all done with them. 236 */ 237 if (sc->sc.sc_size) { 238 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 239 sc->sc.sc_size = 0; 240 } 241 242 return 0; 243 } 244 245 CFATTACH_DECL3_NEW(ohci_pci, sizeof(struct ohci_pci_softc), 246 ohci_pci_match, ohci_pci_attach, ohci_pci_detach, ohci_activate, NULL, 247 ohci_childdet, 0); 248
Indexes created Sun Oct 25 00:26:45 UTC 2026