1 /* $NetBSD: cuda.c,v 1.35 2026/02/18 13:35:40 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.35 2026/02/18 13:35:40 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/proc.h> 37 #include <sys/mutex.h> 38 39 #include <sys/bus.h> 40 #include <machine/autoconf.h> 41 #include <machine/pio.h> 42 #include <dev/clock_subr.h> 43 44 #include <dev/i2c/i2cvar.h> 45 #include <dev/i2c/i2c_calls.h> 46 #include <dev/i2c/i2c_enum.h> 47 48 #include <macppc/dev/viareg.h> 49 #include <macppc/dev/cudavar.h> 50 51 #include <dev/ofw/openfirm.h> 52 #include <dev/adb/adbvar.h> 53 #include "opt_cuda.h" 54 55 #ifdef CUDA_DEBUG 56 #define DPRINTF printf 57 #else 58 #define DPRINTF while (0) printf 59 #endif 60 61 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 62 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 63 #define CUDA_OUT 0x3 /* sending out a command */ 64 #define CUDA_IN 0x4 /* receiving data */ 65 #define CUDA_POLLING 0x5 /* polling - II only */ 66 67 static void cuda_attach(device_t, device_t, void *); 68 static int cuda_match(device_t, struct cfdata *, void *); 69 static void cuda_autopoll(void *, int); 70 71 static int cuda_intr(void *); 72 73 typedef struct _cuda_handler { 74 int (*handler)(void *, int, uint8_t *); 75 void *cookie; 76 } CudaHandler; 77 78 struct cuda_softc { 79 device_t sc_dev; 80 void *sc_ih; 81 CudaHandler sc_handlers[16]; 82 struct todr_chip_handle sc_todr; 83 struct adb_bus_accessops sc_adbops; 84 struct i2c_controller sc_i2c; 85 bus_space_tag_t sc_memt; 86 bus_space_handle_t sc_memh; 87 88 /* 89 * We provide our own i2c device enumeration method, so we 90 * need to subclass our device handle. 91 */ 92 struct devhandle_impl sc_devhandle_impl; 93 94 int sc_node; 95 int sc_state; 96 int sc_waiting; 97 int sc_polling; 98 int sc_sent; 99 int sc_out_length; 100 int sc_received; 101 int sc_iic_done; 102 int sc_error; 103 /* time */ 104 uint32_t sc_tod; 105 uint32_t sc_autopoll; 106 kcondvar_t sc_todev; 107 kmutex_t sc_todevmtx; 108 /* ADB */ 109 void (*sc_adb_handler)(void *, int, uint8_t *); 110 void *sc_adb_cookie; 111 uint32_t sc_i2c_read_len; 112 /* internal buffers */ 113 uint8_t sc_in[256]; 114 uint8_t sc_out[256]; 115 }; 116 117 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc), 118 cuda_match, cuda_attach, NULL, NULL); 119 120 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 121 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 122 static void cuda_idle(struct cuda_softc *); 123 static void cuda_tip(struct cuda_softc *); 124 static void cuda_clear_tip(struct cuda_softc *); 125 static void cuda_in(struct cuda_softc *); 126 static void cuda_out(struct cuda_softc *); 127 static void cuda_toggle_ack(struct cuda_softc *); 128 static void cuda_ack_off(struct cuda_softc *); 129 static int cuda_intr_state(struct cuda_softc *); 130 131 static void cuda_init(struct cuda_softc *); 132 133 /* 134 * send a message to Cuda. 135 */ 136 /* cookie, flags, length, data */ 137 static int cuda_send(void *, int, int, uint8_t *); 138 static void cuda_poll(void *); 139 static void cuda_adb_poll(void *); 140 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 141 142 static int cuda_error_handler(void *, int, uint8_t *); 143 144 static int cuda_todr_handler(void *, int, uint8_t *); 145 static int cuda_todr_set(todr_chip_handle_t, struct timeval *); 146 static int cuda_todr_get(todr_chip_handle_t, struct timeval *); 147 148 static int cuda_adb_handler(void *, int, uint8_t *); 149 static void cuda_final(device_t); 150 151 static struct cuda_attach_args *cuda0 = NULL; 152 153 /* ADB bus attachment stuff */ 154 static int cuda_adb_send(void *, int, int, int, uint8_t *); 155 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 156 157 /* i2c stuff */ 158 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 159 void *, size_t, int); 160 161 static const struct i2c_deventry cuda_i2c_devices[] = { 162 { .name = "videopll", 163 .compat = "aapl,valkyrie-videopll", 164 .addr = 0x50, 165 .data = "/valkyrie" }, 166 167 { .name = "sgsmix", 168 .compat = "st,tda7433", 169 .addr = 0x8a, 170 .data = "/perch" }, 171 172 I2C_DEVENTRY_EOL 173 }; 174 175 static bool 176 cuda_i2cdev_callback(device_t dev, devhandle_t call_handle, 177 const struct i2c_deventry *entry, devhandle_t *child_devhandlep) 178 { 179 return (OF_finddevice((const char *)entry->data) != -1); 180 } 181 182 static int 183 cuda_i2c_enumerate_devices(device_t dev, devhandle_t call_handle, void *v) 184 { 185 struct i2c_enumerate_devices_args *args = v; 186 187 return i2c_enumerate_deventries(dev, call_handle, args, 188 cuda_i2c_devices, cuda_i2cdev_callback); 189 } 190 191 static device_call_t 192 cuda_devhandle_lookup_device_call(devhandle_t handle, const char *name, 193 devhandle_t *call_handlep) 194 { 195 if (strcmp(name, I2C_ENUMERATE_DEVICES_STR) == 0) { 196 return cuda_i2c_enumerate_devices; 197 } 198 199 /* Defer everything else to the "super". */ 200 return NULL; 201 } 202 203 static int 204 cuda_match(device_t parent, struct cfdata *cf, void *aux) 205 { 206 struct confargs *ca = aux; 207 208 if (ca->ca_nreg < 8) 209 return 0; 210 211 if (ca->ca_nintr < 4) 212 return 0; 213 214 if (strcmp(ca->ca_name, "via-cuda") == 0) { 215 return 10; /* beat adb* at obio? */ 216 } 217 218 return 0; 219 } 220 221 static void 222 cuda_attach(device_t parent, device_t self, void *aux) 223 { 224 struct confargs *ca = aux; 225 struct cuda_softc *sc = device_private(self); 226 static struct cuda_attach_args caa; 227 int irq = ca->ca_intr[0]; 228 int node, i, child; 229 char name[32]; 230 231 sc->sc_dev = self; 232 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1"); 233 if (node) 234 OF_getprop(node, "interrupts", &irq, 4); 235 236 aprint_normal(" irq %d", irq); 237 238 sc->sc_node = ca->ca_node; 239 sc->sc_memt = ca->ca_tag; 240 241 sc->sc_sent = 0; 242 sc->sc_received = 0; 243 sc->sc_waiting = 0; 244 sc->sc_polling = 0; 245 sc->sc_state = CUDA_NOTREADY; 246 sc->sc_error = 0; 247 sc->sc_i2c_read_len = 0; 248 249 cv_init(&sc->sc_todev, "cuda_event"); 250 mutex_init(&sc->sc_todevmtx, MUTEX_DEFAULT, IPL_NONE); 251 252 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 253 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 254 255 aprint_normal(": unable to map registers\n"); 256 return; 257 } 258 sc->sc_ih = intr_establish_xname(irq, IST_EDGE, IPL_TTY, cuda_intr, sc, 259 device_xname(self)); 260 printf("\n"); 261 262 for (i = 0; i < 16; i++) { 263 sc->sc_handlers[i].handler = NULL; 264 sc->sc_handlers[i].cookie = NULL; 265 } 266 267 cuda_init(sc); 268 269 /* now attach children */ 270 config_interrupts(self, cuda_final); 271 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 272 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 273 274 child = OF_child(ca->ca_node); 275 while (child != 0) { 276 277 if (OF_getprop(child, "name", name, 32) == 0) 278 continue; 279 if (strncmp(name, "adb", 4) == 0) { 280 281 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 282 sc->sc_adbops.cookie = sc; 283 sc->sc_adbops.send = cuda_adb_send; 284 sc->sc_adbops.poll = cuda_adb_poll; 285 sc->sc_adbops.autopoll = cuda_autopoll; 286 sc->sc_adbops.set_handler = cuda_adb_set_handler; 287 config_found(self, &sc->sc_adbops, nadb_print, 288 CFARGS(.iattr = "adb_bus")); 289 } else if (strncmp(name, "rtc", 4) == 0) { 290 291 sc->sc_todr.todr_gettime = cuda_todr_get; 292 sc->sc_todr.todr_settime = cuda_todr_set; 293 sc->sc_todr.todr_dev = self; 294 todr_attach(&sc->sc_todr); 295 } 296 child = OF_peer(child); 297 } 298 299 caa.cookie = sc; 300 caa.set_handler = cuda_set_handler; 301 caa.send = cuda_send; 302 caa.poll = cuda_poll; 303 #if notyet 304 config_found(self, &caa, cuda_print, CFARGS_NONE); 305 #endif 306 307 /* 308 * There are no OF nodes for our I2C devices, so we provide 309 * our own enumeration method. 310 */ 311 iic_tag_init(&sc->sc_i2c); 312 sc->sc_i2c.ic_cookie = sc; 313 sc->sc_i2c.ic_exec = cuda_i2c_exec; 314 315 iicbus_attach_with_devhandle(self, &sc->sc_i2c, 316 devhandle_subclass(device_handle(self), 317 &sc->sc_devhandle_impl, 318 cuda_devhandle_lookup_device_call)); 319 320 if (cuda0 == NULL) 321 cuda0 = &caa; 322 } 323 324 static void 325 cuda_init(struct cuda_softc *sc) 326 { 327 uint8_t reg; 328 329 reg = cuda_read_reg(sc, vDirB); 330 reg |= 0x30; /* register B bits 4 and 5: outputs */ 331 cuda_write_reg(sc, vDirB, reg); 332 333 reg = cuda_read_reg(sc, vDirB); 334 reg &= 0xf7; /* register B bit 3: input */ 335 cuda_write_reg(sc, vDirB, reg); 336 337 reg = cuda_read_reg(sc, vACR); 338 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 339 cuda_write_reg(sc, vACR, reg); 340 341 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 342 343 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 344 345 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 346 cuda_idle(sc); /* set ADB bus state to idle */ 347 348 /* sort of a device reset */ 349 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 350 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 351 cuda_idle(sc); /* reset state to idle */ 352 delay(150); 353 cuda_tip(sc); /* signal start of frame */ 354 delay(150); 355 cuda_toggle_ack(sc); 356 delay(150); 357 cuda_clear_tip(sc); 358 delay(150); 359 cuda_idle(sc); /* back to idle state */ 360 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 361 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 362 } 363 364 static void 365 cuda_final(device_t dev) 366 { 367 struct cuda_softc *sc = device_private(dev); 368 369 sc->sc_polling = 0; 370 } 371 372 static inline void 373 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 374 { 375 376 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 377 } 378 379 static inline uint8_t 380 cuda_read_reg(struct cuda_softc *sc, int offset) 381 { 382 383 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 384 } 385 386 static int 387 cuda_set_handler(void *cookie, int type, 388 int (*handler)(void *, int, uint8_t *), void *hcookie) 389 { 390 struct cuda_softc *sc = cookie; 391 CudaHandler *me; 392 393 if ((type >= 0) && (type < 16)) { 394 me = &sc->sc_handlers[type]; 395 me->handler = handler; 396 me->cookie = hcookie; 397 return 0; 398 } 399 return -1; 400 } 401 402 static int 403 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 404 { 405 struct cuda_softc *sc = cookie; 406 int s; 407 408 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 409 if (sc->sc_state == CUDA_NOTREADY) 410 return -1; 411 412 s = splhigh(); 413 414 if (sc->sc_state == CUDA_IDLE /*&& 415 (cuda_read_reg(sc, vBufB) & vPB3) == vPB3*/) { 416 /* fine */ 417 DPRINTF("chip is idle\n"); 418 } else { 419 DPRINTF("cuda state is %d\n", sc->sc_state); 420 if (sc->sc_waiting == 0) { 421 sc->sc_waiting = 1; 422 } else { 423 splx(s); 424 return -1; 425 } 426 } 427 428 sc->sc_error = 0; 429 memcpy(sc->sc_out, msg, length); 430 sc->sc_out_length = length; 431 sc->sc_sent = 0; 432 433 if (sc->sc_waiting != 1) { 434 435 delay(150); 436 sc->sc_state = CUDA_OUT; 437 cuda_out(sc); 438 cuda_write_reg(sc, vSR, sc->sc_out[0]); 439 cuda_ack_off(sc); 440 cuda_tip(sc); 441 } 442 sc->sc_waiting = 1; 443 444 if (sc->sc_polling || poll || cold) { 445 cuda_poll(sc); 446 } 447 448 splx(s); 449 450 return 0; 451 } 452 453 static void 454 cuda_poll(void *cookie) 455 { 456 struct cuda_softc *sc = cookie; 457 int s; 458 459 DPRINTF("polling\n"); 460 while ((sc->sc_state != CUDA_IDLE) || 461 (cuda_intr_state(sc)) || 462 (sc->sc_waiting == 1)) { 463 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 464 s = splhigh(); 465 cuda_intr(sc); 466 splx(s); 467 } 468 } 469 } 470 471 static void 472 cuda_adb_poll(void *cookie) 473 { 474 struct cuda_softc *sc = cookie; 475 int s; 476 477 s = splhigh(); 478 cuda_intr(sc); 479 splx(s); 480 } 481 482 static void 483 cuda_idle(struct cuda_softc *sc) 484 { 485 uint8_t reg; 486 487 reg = cuda_read_reg(sc, vBufB); 488 reg |= (vPB4 | vPB5); 489 cuda_write_reg(sc, vBufB, reg); 490 } 491 492 static void 493 cuda_tip(struct cuda_softc *sc) 494 { 495 uint8_t reg; 496 497 reg = cuda_read_reg(sc, vBufB); 498 reg &= ~vPB5; 499 cuda_write_reg(sc, vBufB, reg); 500 } 501 502 static void 503 cuda_clear_tip(struct cuda_softc *sc) 504 { 505 uint8_t reg; 506 507 reg = cuda_read_reg(sc, vBufB); 508 reg |= vPB5; 509 cuda_write_reg(sc, vBufB, reg); 510 } 511 512 static void 513 cuda_in(struct cuda_softc *sc) 514 { 515 uint8_t reg; 516 517 reg = cuda_read_reg(sc, vACR); 518 reg &= ~vSR_OUT; 519 cuda_write_reg(sc, vACR, reg); 520 } 521 522 static void 523 cuda_out(struct cuda_softc *sc) 524 { 525 uint8_t reg; 526 527 reg = cuda_read_reg(sc, vACR); 528 reg |= vSR_OUT; 529 cuda_write_reg(sc, vACR, reg); 530 } 531 532 static void 533 cuda_toggle_ack(struct cuda_softc *sc) 534 { 535 uint8_t reg; 536 537 reg = cuda_read_reg(sc, vBufB); 538 reg ^= vPB4; 539 cuda_write_reg(sc, vBufB, reg); 540 } 541 542 static void 543 cuda_ack_off(struct cuda_softc *sc) 544 { 545 uint8_t reg; 546 547 reg = cuda_read_reg(sc, vBufB); 548 reg |= vPB4; 549 cuda_write_reg(sc, vBufB, reg); 550 } 551 552 static int 553 cuda_intr_state(struct cuda_softc *sc) 554 { 555 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 556 } 557 558 static int 559 cuda_intr(void *arg) 560 { 561 struct cuda_softc *sc = arg; 562 int ending, type; 563 uint8_t reg; 564 565 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 566 DPRINTF("["); 567 if ((reg & 0x80) == 0) { 568 DPRINTF("irq %02x]", reg); 569 return 0; /* No interrupts to process */ 570 } 571 DPRINTF(":"); 572 573 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 574 575 switch_start: 576 switch (sc->sc_state) { 577 case CUDA_IDLE: 578 /* 579 * This is an unexpected packet, so grab the first (dummy) 580 * byte, set up the proper vars, and tell the chip we are 581 * starting to receive the packet by setting the TIP bit. 582 */ 583 sc->sc_in[1] = cuda_read_reg(sc, vSR); 584 DPRINTF("start: %02x", sc->sc_in[1]); 585 if (cuda_intr_state(sc) == 0) { 586 /* must have been a fake start */ 587 DPRINTF(" ... fake start\n"); 588 if (sc->sc_waiting) { 589 /* start over */ 590 delay(150); 591 sc->sc_state = CUDA_OUT; 592 sc->sc_sent = 0; 593 cuda_out(sc); 594 cuda_write_reg(sc, vSR, sc->sc_out[1]); 595 cuda_ack_off(sc); 596 cuda_tip(sc); 597 } 598 break; 599 } 600 601 cuda_in(sc); 602 cuda_tip(sc); 603 604 sc->sc_received = 1; 605 sc->sc_state = CUDA_IN; 606 DPRINTF(" CUDA_IN"); 607 break; 608 609 case CUDA_IN: 610 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 611 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 612 ending = 0; 613 if (sc->sc_received > 255) { 614 /* bitch only once */ 615 if (sc->sc_received == 256) { 616 aprint_error_dev(sc->sc_dev, 617 "input overflow\n"); 618 ending = 1; 619 } 620 } else 621 sc->sc_received++; 622 if (sc->sc_received > 3) { 623 if ((sc->sc_in[3] == CMD_IIC) && 624 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 625 ending = 1; 626 } 627 } 628 629 /* intr off means this is the last byte (end of frame) */ 630 if (cuda_intr_state(sc) == 0) { 631 ending = 1; 632 DPRINTF(".\n"); 633 } else { 634 cuda_toggle_ack(sc); 635 } 636 637 if (ending == 1) { /* end of message? */ 638 639 sc->sc_in[0] = sc->sc_received - 1; 640 641 /* reset vars and signal the end of this frame */ 642 cuda_idle(sc); 643 644 /* check if we have a handler for this message */ 645 type = sc->sc_in[1]; 646 if ((type >= 0) && (type < 16)) { 647 CudaHandler *me = &sc->sc_handlers[type]; 648 649 if (me->handler != NULL) { 650 me->handler(me->cookie, 651 sc->sc_received - 1, &sc->sc_in[1]); 652 } else { 653 aprint_error_dev(sc->sc_dev, 654 "no handler for type %02x\n", type); 655 panic("barf"); 656 } 657 } 658 659 DPRINTF("CUDA_IDLE"); 660 sc->sc_state = CUDA_IDLE; 661 662 sc->sc_received = 0; 663 664 /* 665 * If there is something waiting to be sent out, 666 * set everything up and send the first byte. 667 */ 668 if (sc->sc_waiting == 1) { 669 670 DPRINTF("pending write\n"); 671 delay(1500); /* required */ 672 sc->sc_sent = 0; 673 sc->sc_state = CUDA_OUT; 674 675 /* 676 * If the interrupt is on, we were too slow 677 * and the chip has already started to send 678 * something to us, so back out of the write 679 * and start a read cycle. 680 */ 681 if (cuda_intr_state(sc)) { 682 cuda_in(sc); 683 cuda_idle(sc); 684 sc->sc_sent = 0; 685 sc->sc_state = CUDA_IDLE; 686 sc->sc_received = 0; 687 delay(150); 688 DPRINTF("too slow - incoming message\n"); 689 goto switch_start; 690 } 691 /* 692 * If we got here, it's ok to start sending 693 * so load the first byte and tell the chip 694 * we want to send. 695 */ 696 DPRINTF("sending "); 697 698 cuda_out(sc); 699 cuda_write_reg(sc, vSR, 700 sc->sc_out[sc->sc_sent]); 701 cuda_ack_off(sc); 702 cuda_tip(sc); 703 } 704 } 705 break; 706 707 case CUDA_OUT: 708 (void)cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 709 710 sc->sc_sent++; 711 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 712 713 DPRINTF("incoming msg during send\n"); 714 cuda_in(sc); /* make sure SR is set to IN */ 715 cuda_idle(sc); 716 sc->sc_sent = 0; /* must start all over */ 717 sc->sc_state = CUDA_IDLE; /* new state */ 718 sc->sc_received = 0; 719 sc->sc_waiting = 1; /* must retry when done with 720 * read */ 721 delay(150); 722 goto switch_start; /* process next state right 723 * now */ 724 break; 725 } 726 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 727 728 sc->sc_waiting = 0; /* done writing */ 729 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 730 cuda_in(sc); 731 cuda_idle(sc); 732 DPRINTF("done sending\n"); 733 } else { 734 /* send next byte */ 735 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 736 DPRINTF("%02x", sc->sc_out[sc->sc_sent]); 737 cuda_toggle_ack(sc); /* signal byte ready to 738 * shift */ 739 } 740 break; 741 742 case CUDA_NOTREADY: 743 DPRINTF("adb: not yet initialized\n"); 744 break; 745 746 default: 747 DPRINTF("intr: unknown ADB state\n"); 748 break; 749 } 750 751 DPRINTF("]"); 752 return 1; 753 } 754 755 static int 756 cuda_error_handler(void *cookie, int len, uint8_t *data) 757 { 758 struct cuda_softc *sc = cookie; 759 760 /* 761 * something went wrong 762 * byte 3 seems to be the failed command 763 */ 764 sc->sc_error = 1; 765 DPRINTF("cuda error %02x %02x %02x %02x\n", data[0], data[1], data[2], data[3]); 766 cv_signal(&sc->sc_todev); 767 return 0; 768 } 769 770 771 /* real time clock */ 772 773 static int 774 cuda_todr_handler(void *cookie, int len, uint8_t *data) 775 { 776 struct cuda_softc *sc = cookie; 777 778 #ifdef CUDA_DEBUG 779 int i; 780 printf("msg: %02x", data[0]); 781 for (i = 1; i < len; i++) { 782 printf(" %02x", data[i]); 783 } 784 printf("\n"); 785 #endif 786 787 switch(data[2]) { 788 case CMD_READ_RTC: 789 memcpy(&sc->sc_tod, &data[3], 4); 790 break; 791 case CMD_WRITE_RTC: 792 sc->sc_tod = 0xffffffff; 793 break; 794 case CMD_AUTOPOLL: 795 sc->sc_autopoll = 1; 796 break; 797 case CMD_IIC: 798 sc->sc_iic_done = len; 799 break; 800 } 801 cv_signal(&sc->sc_todev); 802 return 0; 803 } 804 805 #define DIFF19041970 2082844800 806 807 static int 808 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp) 809 { 810 struct cuda_softc *sc = device_private(tch->todr_dev); 811 int cnt = 0; 812 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 813 814 sc->sc_tod = 0; 815 while (sc->sc_tod == 0) { 816 cuda_send(sc, 0, 2, cmd); 817 818 while ((sc->sc_tod == 0) && (cnt < 10)) { 819 mutex_enter(&sc->sc_todevmtx); 820 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz); 821 mutex_exit(&sc->sc_todevmtx); 822 823 cnt++; 824 } 825 826 if (sc->sc_tod == 0) { 827 aprint_error_dev(sc->sc_dev, 828 "unable to read a sane RTC value\n"); 829 return EIO; 830 } 831 if ((sc->sc_tod > 0xf0000000UL) || 832 (sc->sc_tod < DIFF19041970)) { 833 /* huh? try again */ 834 sc->sc_tod = 0; 835 aprint_verbose_dev(sc->sc_dev, 836 "got garbage reading RTC, trying again\n"); 837 } 838 } 839 840 tvp->tv_sec = sc->sc_tod - DIFF19041970; 841 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec); 842 tvp->tv_usec = 0; 843 return 0; 844 } 845 846 static int 847 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp) 848 { 849 struct cuda_softc *sc = device_private(tch->todr_dev); 850 uint32_t sec; 851 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 852 853 sec = tvp->tv_sec + DIFF19041970; 854 memcpy(&cmd[2], &sec, 4); 855 sc->sc_tod = 0; 856 if (cuda_send(sc, 0, 6, cmd) == 0) { 857 while (sc->sc_tod == 0) { 858 mutex_enter(&sc->sc_todevmtx); 859 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz); 860 mutex_exit(&sc->sc_todevmtx); 861 } 862 return 0; 863 } 864 aprint_error_dev(sc->sc_dev, "%s failed\n", __func__); 865 return -1; 866 867 } 868 869 /* poweroff and reboot */ 870 871 void 872 cuda_poweroff(void) 873 { 874 struct cuda_softc *sc; 875 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 876 877 if (cuda0 == NULL) 878 return; 879 sc = cuda0->cookie; 880 sc->sc_polling = 1; 881 cuda0->poll(sc); 882 if (cuda0->send(sc, 1, 2, cmd) == 0) 883 while (1); 884 } 885 886 void 887 cuda_restart(void) 888 { 889 struct cuda_softc *sc; 890 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 891 892 if (cuda0 == NULL) 893 return; 894 sc = cuda0->cookie; 895 sc->sc_polling = 1; 896 cuda0->poll(sc); 897 if (cuda0->send(sc, 1, 2, cmd) == 0) 898 while (1); 899 } 900 901 /* ADB message handling */ 902 903 static void 904 cuda_autopoll(void *cookie, int flag) 905 { 906 struct cuda_softc *sc = cookie; 907 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 908 909 if (cmd[2] == sc->sc_autopoll) 910 return; 911 912 sc->sc_autopoll = -1; 913 cuda_send(sc, 0, 3, cmd); 914 while(sc->sc_autopoll == -1) { 915 if (sc->sc_polling || cold) { 916 cuda_poll(sc); 917 } else { 918 mutex_enter(&sc->sc_todevmtx); 919 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz); 920 mutex_exit(&sc->sc_todevmtx); 921 } 922 } 923 } 924 925 static int 926 cuda_adb_handler(void *cookie, int len, uint8_t *data) 927 { 928 struct cuda_softc *sc = cookie; 929 930 if (sc->sc_adb_handler != NULL) { 931 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 932 &data[1]); 933 return 0; 934 } 935 return -1; 936 } 937 938 static int 939 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 940 { 941 struct cuda_softc *sc = cookie; 942 int i, s = 0; 943 uint8_t packet[16]; 944 945 /* construct an ADB command packet and send it */ 946 packet[0] = CUDA_ADB; 947 packet[1] = command; 948 for (i = 0; i < len; i++) 949 packet[i + 2] = data[i]; 950 if (poll || cold) { 951 s = splhigh(); 952 cuda_poll(sc); 953 } 954 cuda_send(sc, poll, len + 2, packet); 955 if (poll || cold) { 956 cuda_poll(sc); 957 splx(s); 958 } 959 return 0; 960 } 961 962 static int 963 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 964 void *hcookie) 965 { 966 struct cuda_softc *sc = cookie; 967 968 /* register a callback for incoming ADB messages */ 969 sc->sc_adb_handler = handler; 970 sc->sc_adb_cookie = hcookie; 971 return 0; 972 } 973 974 /* i2c message handling */ 975 976 static int 977 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 978 size_t send_len, void *_recv, size_t recv_len, int flags) 979 { 980 struct cuda_softc *sc = cookie; 981 const uint8_t *send = _send; 982 uint8_t *recv = _recv; 983 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 984 985 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 986 command[2] = addr; 987 988 /* Copy command and output data bytes, if any, to buffer */ 989 if (send_len > 0) 990 memcpy(&command[3], send, uimin((int)send_len, 12)); 991 else if (I2C_OP_READ_P(op) && (recv_len == 0)) { 992 /* 993 * If no data bytes in either direction, it's a "quick" 994 * i2c operation. We don't know how to do a quick_read 995 * since that requires us to set the low bit of the 996 * address byte after it has been left-shifted. 997 */ 998 sc->sc_error = 0; 999 return -1; 1000 } 1001 1002 sc->sc_iic_done = 0; 1003 cuda_send(sc, sc->sc_polling, send_len + 3, command); 1004 1005 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 1006 if (sc->sc_polling || cold) { 1007 cuda_poll(sc); 1008 } else { 1009 mutex_enter(&sc->sc_todevmtx); 1010 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz); 1011 mutex_exit(&sc->sc_todevmtx); 1012 } 1013 } 1014 1015 if (sc->sc_error) { 1016 sc->sc_error = 0; 1017 aprint_error_dev(sc->sc_dev, "error doing I2C\n"); 1018 return -1; 1019 } 1020 1021 /* see if we're supposed to do a read */ 1022 if (recv_len > 0) { 1023 sc->sc_iic_done = 0; 1024 command[2] |= 1; 1025 command[3] = 0; 1026 1027 /* 1028 * XXX we need to do something to limit the size of the answer 1029 * - apparently the chip keeps sending until we tell it to stop 1030 */ 1031 sc->sc_i2c_read_len = recv_len; 1032 DPRINTF("rcv_len: %d\n", recv_len); 1033 cuda_send(sc, sc->sc_polling, 3, command); 1034 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 1035 if (sc->sc_polling || cold) { 1036 cuda_poll(sc); 1037 } else { 1038 mutex_enter(&sc->sc_todevmtx); 1039 cv_timedwait(&sc->sc_todev, &sc->sc_todevmtx, hz); 1040 mutex_exit(&sc->sc_todevmtx); 1041 } 1042 } 1043 1044 if (sc->sc_error) { 1045 aprint_error_dev(sc->sc_dev, 1046 "error trying to read from I2C\n"); 1047 sc->sc_error = 0; 1048 return -1; 1049 } 1050 } 1051 1052 DPRINTF("received: %d\n", sc->sc_iic_done); 1053 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 1054 int rlen; 1055 1056 /* we got an answer */ 1057 rlen = uimin(sc->sc_iic_done - 3, recv_len); 1058 memcpy(recv, &sc->sc_in[4], rlen); 1059 #ifdef CUDA_DEBUG 1060 { 1061 int i; 1062 printf("ret:"); 1063 for (i = 0; i < rlen; i++) 1064 printf(" %02x", recv[i]); 1065 printf("\n"); 1066 } 1067 #endif 1068 return rlen; 1069 } 1070 return 0; 1071 } 1072
Indexes created Sun Oct 25 00:26:45 UTC 2026