1 /* $NetBSD: if_urtwn.c,v 1.121 2026/01/10 09:50:06 mlelstv Exp $ */ 2 /* $OpenBSD: if_urtwn.c,v 1.42 2015/02/10 23:25:46 mpi Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2014 Kevin Lo <kevlo (at) FreeBSD.org> 7 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss (at) yahoo.com.au> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /*- 23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU 24 * RTL8192EU. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: if_urtwn.c,v 1.121 2026/01/10 09:50:06 mlelstv Exp $"); 29 30 #ifdef _KERNEL_OPT 31 #include "opt_inet.h" 32 #include "opt_usb.h" 33 #endif 34 35 #include <sys/param.h> 36 #include <sys/sockio.h> 37 #include <sys/sysctl.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/module.h> 43 #include <sys/conf.h> 44 #include <sys/device.h> 45 #include <sys/rndsource.h> 46 47 #include <sys/bus.h> 48 #include <machine/endian.h> 49 #include <sys/intr.h> 50 51 #include <net/bpf.h> 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/if_dl.h> 55 #include <net/if_ether.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_inarp.h> 64 65 #include <net80211/ieee80211_netbsd.h> 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 69 #include <dev/firmload.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 #include <dev/usb/usbdivar.h> 74 #include <dev/usb/usbdi_util.h> 75 #include <dev/usb/usbdevs.h> 76 #include <dev/usb/usbhist.h> 77 78 #include <dev/ic/rtwnreg.h> 79 #include <dev/ic/rtwn_data.h> 80 #include <dev/usb/if_urtwnreg.h> 81 #include <dev/usb/if_urtwnvar.h> 82 83 /* 84 * The sc_write_mtx locking is to prevent sequences of writes from 85 * being intermingled with each other. I don't know if this is really 86 * needed. I have added it just to be on the safe side. 87 */ 88 89 #ifdef URTWN_DEBUG 90 #define DBG_INIT __BIT(0) 91 #define DBG_FN __BIT(1) 92 #define DBG_TX __BIT(2) 93 #define DBG_RX __BIT(3) 94 #define DBG_STM __BIT(4) 95 #define DBG_RF __BIT(5) 96 #define DBG_REG __BIT(6) 97 #define DBG_ALL 0xffffffffU 98 99 #ifndef URTWN_DEBUG_DEFAULT 100 #define URTWN_DEBUG_DEFAULT 0 101 #endif 102 103 u_int urtwn_debug = URTWN_DEBUG_DEFAULT; 104 105 #define DPRINTFN(n, fmt, a, b, c, d) do { \ 106 if (urtwn_debug & (n)) { \ 107 KERNHIST_LOG(usbhist, fmt, a, b, c, d); \ 108 } \ 109 } while (/*CONSTCOND*/0) 110 #define URTWNHIST_FUNC() USBHIST_FUNC() 111 #define URTWNHIST_CALLED() do { \ 112 if (urtwn_debug & DBG_FN) { \ 113 KERNHIST_CALLED(usbhist); \ 114 } \ 115 } while(/*CONSTCOND*/0) 116 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) do { \ 117 if (urtwn_debug & DBG_FN) { \ 118 KERNHIST_CALLARGS(usbhist, fmt, a, b, c, d); \ 119 } \ 120 } while(/*CONSTCOND*/0) 121 #else 122 #define DPRINTFN(n, fmt, a, b, c, d) 123 #define URTWNHIST_FUNC() 124 #define URTWNHIST_CALLED() 125 #define URTWNHIST_CALLARGS(fmt, a, b, c, d) 126 #endif 127 128 #define URTWN_DEV(v,p) { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, 0 } 129 #define URTWN_RTL8188E_DEV(v,p) \ 130 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8188E } 131 #define URTWN_RTL8192EU_DEV(v,p) \ 132 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, FLAG_RTL8192E } 133 static const struct urtwn_dev { 134 struct usb_devno dev; 135 uint32_t flags; 136 #define FLAG_RTL8188E __BIT(0) 137 #define FLAG_RTL8192E __BIT(1) 138 } urtwn_devs[] = { 139 URTWN_DEV(ABOCOM, RTL8188CU_1), 140 URTWN_DEV(ABOCOM, RTL8188CU_2), 141 URTWN_DEV(ABOCOM, RTL8192CU), 142 URTWN_DEV(ASUSTEK, RTL8192CU), 143 URTWN_DEV(ASUSTEK, RTL8192CU_3), 144 URTWN_DEV(ASUSTEK, USBN10NANO), 145 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 146 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 147 URTWN_DEV(AZUREWAVE, RTL8188CU), 148 URTWN_DEV(BELKIN, F7D2102), 149 URTWN_DEV(BELKIN, RTL8188CU), 150 URTWN_DEV(BELKIN, RTL8188CUS), 151 URTWN_DEV(BELKIN, RTL8192CU), 152 URTWN_DEV(BELKIN, RTL8192CU_1), 153 URTWN_DEV(BELKIN, RTL8192CU_2), 154 URTWN_DEV(CHICONY, RTL8188CUS_1), 155 URTWN_DEV(CHICONY, RTL8188CUS_2), 156 URTWN_DEV(CHICONY, RTL8188CUS_3), 157 URTWN_DEV(CHICONY, RTL8188CUS_4), 158 URTWN_DEV(CHICONY, RTL8188CUS_5), 159 URTWN_DEV(CHICONY, RTL8188CUS_6), 160 URTWN_DEV(COMPARE, RTL8192CU), 161 URTWN_DEV(COREGA, RTL8192CU), 162 URTWN_DEV(DLINK, DWA131B), 163 URTWN_DEV(DLINK, RTL8188CU), 164 URTWN_DEV(DLINK, RTL8192CU_1), 165 URTWN_DEV(DLINK, RTL8192CU_2), 166 URTWN_DEV(DLINK, RTL8192CU_3), 167 URTWN_DEV(DLINK, RTL8192CU_4), 168 URTWN_DEV(EDIMAX, RTL8188CU), 169 URTWN_DEV(EDIMAX, RTL8192CU), 170 URTWN_DEV(FEIXUN, RTL8188CU), 171 URTWN_DEV(FEIXUN, RTL8192CU), 172 URTWN_DEV(GUILLEMOT, HWNUP150), 173 URTWN_DEV(GUILLEMOT, RTL8192CU), 174 URTWN_DEV(HAWKING, RTL8192CU), 175 URTWN_DEV(HAWKING, RTL8192CU_2), 176 URTWN_DEV(HP3, RTL8188CU), 177 URTWN_DEV(IODATA, WNG150UM), 178 URTWN_DEV(IODATA, RTL8192CU), 179 URTWN_DEV(NETGEAR, WNA1000M), 180 URTWN_DEV(NETGEAR, RTL8192CU), 181 URTWN_DEV(NETGEAR4, RTL8188CU), 182 URTWN_DEV(NOVATECH, RTL8188CU), 183 URTWN_DEV(PLANEX2, RTL8188CU_1), 184 URTWN_DEV(PLANEX2, RTL8188CU_2), 185 URTWN_DEV(PLANEX2, RTL8192CU), 186 URTWN_DEV(PLANEX2, RTL8188CU_3), 187 URTWN_DEV(PLANEX2, RTL8188CU_4), 188 URTWN_DEV(PLANEX2, RTL8188CUS), 189 URTWN_DEV(REALTEK, RTL8188CE_0), 190 URTWN_DEV(REALTEK, RTL8188CE_1), 191 URTWN_DEV(REALTEK, RTL8188CTV), 192 URTWN_DEV(REALTEK, RTL8188CU_0), 193 URTWN_DEV(REALTEK, RTL8188CU_1), 194 URTWN_DEV(REALTEK, RTL8188CU_2), 195 URTWN_DEV(REALTEK, RTL8188CU_3), 196 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 197 URTWN_DEV(REALTEK, RTL8188CUS), 198 URTWN_DEV(REALTEK, RTL8188RU), 199 URTWN_DEV(REALTEK, RTL8188RU_2), 200 URTWN_DEV(REALTEK, RTL8188RU_3), 201 URTWN_DEV(REALTEK, RTL8191CU), 202 URTWN_DEV(REALTEK, RTL8192CE), 203 URTWN_DEV(REALTEK, RTL8192CU), 204 URTWN_DEV(SITECOMEU, RTL8188CU), 205 URTWN_DEV(SITECOMEU, RTL8188CU_2), 206 URTWN_DEV(SITECOMEU, RTL8192CU), 207 URTWN_DEV(SITECOMEU, RTL8192CUR2), 208 URTWN_DEV(TPLINK, RTL8192CU), 209 URTWN_DEV(TRENDNET, RTL8188CU), 210 URTWN_DEV(TRENDNET, RTL8192CU), 211 URTWN_DEV(TRENDNET, TEW648UBM), 212 URTWN_DEV(ZYXEL, RTL8192CU), 213 214 /* URTWN_RTL8188E */ 215 URTWN_RTL8188E_DEV(ASUSTEK, USBN10NANO_B1), 216 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 217 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 218 URTWN_RTL8188E_DEV(MERCUSYS, MW150USV2), 219 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 220 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 221 URTWN_RTL8188E_DEV(ABOCOM, RTL8188EU), 222 URTWN_RTL8188E_DEV(TPLINK, RTL8188EU), 223 URTWN_RTL8188E_DEV(DLINK, DWA121B1), 224 URTWN_RTL8188E_DEV(EDIMAX, EW7811UNV2), 225 226 /* URTWN_RTL8192EU */ 227 URTWN_RTL8192EU_DEV(DLINK, DWA131E), 228 URTWN_RTL8192EU_DEV(REALTEK, RTL8192EU), 229 URTWN_RTL8192EU_DEV(TPLINK, WN821NV5), 230 URTWN_RTL8192EU_DEV(TPLINK, WN822NV4), 231 URTWN_RTL8192EU_DEV(TPLINK, WN823NV2), 232 }; 233 #undef URTWN_DEV 234 #undef URTWN_RTL8188E_DEV 235 #undef URTWN_RTL8192EU_DEV 236 237 static int urtwn_match(device_t, cfdata_t, void *); 238 static void urtwn_attach(device_t, device_t, void *); 239 static int urtwn_detach(device_t, int); 240 static int urtwn_activate(device_t, enum devact); 241 242 CFATTACH_DECL_NEW(urtwn, sizeof(struct urtwn_softc), urtwn_match, 243 urtwn_attach, urtwn_detach, urtwn_activate); 244 245 static int urtwn_open_pipes(struct urtwn_softc *); 246 static void urtwn_close_pipes(struct urtwn_softc *); 247 static int urtwn_alloc_rx_list(struct urtwn_softc *); 248 static void urtwn_free_rx_list(struct urtwn_softc *); 249 static int urtwn_alloc_tx_list(struct urtwn_softc *); 250 static void urtwn_free_tx_list(struct urtwn_softc *); 251 static void urtwn_task(void *); 252 static void urtwn_do_async(struct urtwn_softc *, 253 void (*)(struct urtwn_softc *, void *), void *, int); 254 static void urtwn_wait_async(struct urtwn_softc *); 255 static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 256 int); 257 static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 258 static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 259 static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 260 static int urtwn_write_region(struct urtwn_softc *, uint16_t, uint8_t *, 261 int); 262 static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 263 int); 264 static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 265 static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 266 static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 267 static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, const void *, int); 268 static void urtwn_r92c_rf_write(struct urtwn_softc *, int, uint8_t, 269 uint32_t); 270 static void urtwn_r88e_rf_write(struct urtwn_softc *, int, uint8_t, 271 uint32_t); 272 static void urtwn_r92e_rf_write(struct urtwn_softc *, int, uint8_t, 273 uint32_t); 274 static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 275 static int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 276 static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 277 static void urtwn_efuse_read(struct urtwn_softc *); 278 static void urtwn_efuse_switch_power(struct urtwn_softc *); 279 static int urtwn_read_chipid(struct urtwn_softc *); 280 #ifdef URTWN_DEBUG 281 static void urtwn_dump_rom(struct urtwn_softc *, struct r92c_rom *); 282 #endif 283 static void urtwn_read_rom(struct urtwn_softc *); 284 static void urtwn_r88e_read_rom(struct urtwn_softc *); 285 static int urtwn_media_change(struct ifnet *); 286 static int urtwn_ra_init(struct urtwn_softc *); 287 static int urtwn_get_nettype(struct urtwn_softc *); 288 static void urtwn_set_nettype0_msr(struct urtwn_softc *, uint8_t); 289 static void urtwn_tsf_sync_enable(struct urtwn_softc *); 290 static void urtwn_set_led(struct urtwn_softc *, int, int); 291 static void urtwn_calib_to(void *); 292 static void urtwn_calib_to_cb(struct urtwn_softc *, void *); 293 static void urtwn_next_scan(void *); 294 static int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 295 int); 296 static void urtwn_newstate_cb(struct urtwn_softc *, void *); 297 static int urtwn_wme_update(struct ieee80211com *); 298 static void urtwn_wme_update_cb(struct urtwn_softc *, void *); 299 static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 300 static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 301 static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 302 static void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 303 static void urtwn_rxeof(struct usbd_xfer *, void *, usbd_status); 304 static void urtwn_txeof(struct usbd_xfer *, void *, usbd_status); 305 static int urtwn_tx(struct urtwn_softc *, struct mbuf *, 306 struct ieee80211_node *, struct urtwn_tx_data *); 307 static struct urtwn_tx_data * 308 urtwn_get_tx_data(struct urtwn_softc *, size_t); 309 static void urtwn_start(struct ifnet *); 310 static void urtwn_watchdog(struct ifnet *); 311 static int urtwn_ioctl(struct ifnet *, u_long, void *); 312 static int urtwn_r92c_power_on(struct urtwn_softc *); 313 static int urtwn_r92e_power_on(struct urtwn_softc *); 314 static int urtwn_r88e_power_on(struct urtwn_softc *); 315 static int urtwn_llt_init(struct urtwn_softc *); 316 static void urtwn_fw_reset(struct urtwn_softc *); 317 static void urtwn_r88e_fw_reset(struct urtwn_softc *); 318 static int urtwn_fw_loadpage(struct urtwn_softc *, int, uint8_t *, int); 319 static int urtwn_load_firmware(struct urtwn_softc *); 320 static int urtwn_r92c_dma_init(struct urtwn_softc *); 321 static int urtwn_r88e_dma_init(struct urtwn_softc *); 322 static void urtwn_mac_init(struct urtwn_softc *); 323 static void urtwn_bb_init(struct urtwn_softc *); 324 static void urtwn_rf_init(struct urtwn_softc *); 325 static void urtwn_cam_init(struct urtwn_softc *); 326 static void urtwn_pa_bias_init(struct urtwn_softc *); 327 static void urtwn_rxfilter_init(struct urtwn_softc *); 328 static void urtwn_edca_init(struct urtwn_softc *); 329 static void urtwn_write_txpower(struct urtwn_softc *, int, 330 uint16_t[URTWN_RIDX_COUNT]); 331 static void urtwn_get_txpower(struct urtwn_softc *, size_t, u_int, u_int, 332 uint16_t[URTWN_RIDX_COUNT]); 333 static void urtwn_r88e_get_txpower(struct urtwn_softc *, size_t, u_int, 334 u_int, uint16_t[URTWN_RIDX_COUNT]); 335 static void urtwn_set_txpower(struct urtwn_softc *, u_int, u_int); 336 static void urtwn_set_chan(struct urtwn_softc *, struct ieee80211_channel *, 337 u_int); 338 static void urtwn_iq_calib(struct urtwn_softc *, bool); 339 static void urtwn_lc_calib(struct urtwn_softc *); 340 static void urtwn_temp_calib(struct urtwn_softc *); 341 static int urtwn_init(struct ifnet *); 342 static void urtwn_stop(struct ifnet *, int); 343 static int urtwn_reset(struct ifnet *); 344 static void urtwn_chip_stop(struct urtwn_softc *); 345 static void urtwn_newassoc(struct ieee80211_node *, int); 346 static void urtwn_delay_ms(struct urtwn_softc *, int ms); 347 348 /* Aliases. */ 349 #define urtwn_bb_write urtwn_write_4 350 #define urtwn_bb_read urtwn_read_4 351 352 #define urtwn_lookup(d,v,p) ((const struct urtwn_dev *)usb_lookup(d,v,p)) 353 354 static const uint16_t addaReg[] = { 355 R92C_FPGA0_XCD_SWITCHCTL, R92C_BLUETOOTH, R92C_RX_WAIT_CCA, 356 R92C_TX_CCK_RFON, R92C_TX_CCK_BBON, R92C_TX_OFDM_RFON, 357 R92C_TX_OFDM_BBON, R92C_TX_TO_RX, R92C_TX_TO_TX, R92C_RX_CCK, 358 R92C_RX_OFDM, R92C_RX_WAIT_RIFS, R92C_RX_TO_RX, 359 R92C_STANDBY, R92C_SLEEP, R92C_PMPD_ANAEN 360 }; 361 362 static int 363 urtwn_match(device_t parent, cfdata_t match, void *aux) 364 { 365 struct usb_attach_arg *uaa = aux; 366 367 return urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product) != 368 NULL ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 369 } 370 371 static void 372 urtwn_attach(device_t parent, device_t self, void *aux) 373 { 374 struct urtwn_softc *sc = device_private(self); 375 struct ieee80211com *ic = &sc->sc_ic; 376 struct ifnet *ifp = &sc->sc_if; 377 struct usb_attach_arg *uaa = aux; 378 char *devinfop; 379 const struct urtwn_dev *dev; 380 usb_device_request_t req; 381 size_t i; 382 int error; 383 384 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 385 386 sc->sc_dev = self; 387 sc->sc_udev = uaa->uaa_device; 388 389 sc->chip = 0; 390 dev = urtwn_lookup(urtwn_devs, uaa->uaa_vendor, uaa->uaa_product); 391 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8188E)) 392 SET(sc->chip, URTWN_CHIP_88E); 393 if (dev != NULL && ISSET(dev->flags, FLAG_RTL8192E)) 394 SET(sc->chip, URTWN_CHIP_92EU); 395 396 aprint_naive("\n"); 397 aprint_normal("\n"); 398 399 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 400 aprint_normal_dev(self, "%s\n", devinfop); 401 usbd_devinfo_free(devinfop); 402 403 req.bmRequestType = UT_WRITE_DEVICE; 404 req.bRequest = UR_SET_FEATURE; 405 USETW(req.wValue, UF_DEVICE_REMOTE_WAKEUP); 406 USETW(req.wIndex, UHF_PORT_SUSPEND); 407 USETW(req.wLength, 0); 408 409 (void) usbd_do_request(sc->sc_udev, &req, 0); 410 411 cv_init(&sc->sc_task_cv, "urtwntsk"); 412 mutex_init(&sc->sc_task_mtx, MUTEX_DEFAULT, IPL_NET); 413 mutex_init(&sc->sc_tx_mtx, MUTEX_DEFAULT, IPL_NONE); 414 mutex_init(&sc->sc_rx_mtx, MUTEX_DEFAULT, IPL_NONE); 415 mutex_init(&sc->sc_fwcmd_mtx, MUTEX_DEFAULT, IPL_NONE); 416 mutex_init(&sc->sc_write_mtx, MUTEX_DEFAULT, IPL_NONE); 417 418 usb_init_task(&sc->sc_task, urtwn_task, sc, 0); 419 420 callout_init(&sc->sc_scan_to, 0); 421 callout_setfunc(&sc->sc_scan_to, urtwn_next_scan, sc); 422 callout_init(&sc->sc_calib_to, 0); 423 callout_setfunc(&sc->sc_calib_to, urtwn_calib_to, sc); 424 425 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 426 RND_TYPE_NET, RND_FLAG_DEFAULT); 427 428 error = usbd_set_config_no(sc->sc_udev, 1, 0); 429 if (error != 0) { 430 aprint_error_dev(self, "failed to set configuration" 431 ", err=%s\n", usbd_errstr(error)); 432 goto fail; 433 } 434 435 /* Get the first interface handle. */ 436 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 437 if (error != 0) { 438 aprint_error_dev(self, "could not get interface handle\n"); 439 goto fail; 440 } 441 442 error = urtwn_read_chipid(sc); 443 if (error != 0) { 444 aprint_error_dev(self, "unsupported test chip\n"); 445 goto fail; 446 } 447 448 /* Determine number of Tx/Rx chains. */ 449 if (sc->chip & URTWN_CHIP_92C) { 450 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 451 sc->nrxchains = 2; 452 } else if (sc->chip & URTWN_CHIP_92EU) { 453 sc->ntxchains = 2; 454 sc->nrxchains = 2; 455 } else { 456 sc->ntxchains = 1; 457 sc->nrxchains = 1; 458 } 459 460 if (ISSET(sc->chip, URTWN_CHIP_88E) || 461 ISSET(sc->chip, URTWN_CHIP_92EU)) 462 urtwn_r88e_read_rom(sc); 463 else 464 urtwn_read_rom(sc); 465 466 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %zdT%zdR, address %s\n", 467 (sc->chip & URTWN_CHIP_92EU) ? "8192EU" : 468 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 469 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 470 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 471 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 472 "8188CUS", sc->ntxchains, sc->nrxchains, 473 ether_sprintf(ic->ic_myaddr)); 474 475 error = urtwn_open_pipes(sc); 476 if (error != 0) { 477 aprint_error_dev(sc->sc_dev, "could not open pipes\n"); 478 goto fail; 479 } 480 aprint_normal_dev(self, "%d rx pipe%s, %d tx pipe%s\n", 481 sc->rx_npipe, sc->rx_npipe > 1 ? "s" : "", 482 sc->tx_npipe, sc->tx_npipe > 1 ? "s" : ""); 483 484 /* 485 * Setup the 802.11 device. 486 */ 487 ic->ic_ifp = ifp; 488 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 489 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 490 ic->ic_state = IEEE80211_S_INIT; 491 492 /* Set device capabilities. */ 493 ic->ic_caps = 494 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 495 IEEE80211_C_IBSS | /* IBSS mode supported */ 496 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 497 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 498 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 499 IEEE80211_C_WME | /* 802.11e */ 500 IEEE80211_C_WPA; /* 802.11i */ 501 502 /* Set supported .11b and .11g rates. */ 503 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 504 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 505 506 /* Set supported .11b and .11g channels (1 through 14). */ 507 for (i = 1; i <= 14; i++) { 508 ic->ic_channels[i].ic_freq = 509 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 510 ic->ic_channels[i].ic_flags = 511 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 512 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 513 } 514 515 ifp->if_softc = sc; 516 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 517 ifp->if_init = urtwn_init; 518 ifp->if_ioctl = urtwn_ioctl; 519 ifp->if_start = urtwn_start; 520 ifp->if_watchdog = urtwn_watchdog; 521 IFQ_SET_READY(&ifp->if_snd); 522 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 523 524 if_initialize(ifp); 525 ieee80211_ifattach(ic); 526 527 /* override default methods */ 528 ic->ic_newassoc = urtwn_newassoc; 529 ic->ic_reset = urtwn_reset; 530 ic->ic_wme.wme_update = urtwn_wme_update; 531 532 /* Override state transition machine. */ 533 sc->sc_newstate = ic->ic_newstate; 534 ic->ic_newstate = urtwn_newstate; 535 536 /* XXX media locking needs revisiting */ 537 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 538 ieee80211_media_init_with_lock(ic, 539 urtwn_media_change, ieee80211_media_status, &sc->sc_media_mtx); 540 541 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 542 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 543 &sc->sc_drvbpf); 544 545 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 546 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 547 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 548 549 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 550 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 551 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 552 553 ifp->if_percpuq = if_percpuq_create(ifp); 554 if_register(ifp); 555 556 ieee80211_announce(ic); 557 558 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 559 560 if (!pmf_device_register(self, NULL, NULL)) 561 aprint_error_dev(self, "couldn't establish power handler\n"); 562 563 SET(sc->sc_flags, URTWN_FLAG_ATTACHED); 564 return; 565 566 fail: 567 sc->sc_dying = 1; 568 aprint_error_dev(self, "attach failed\n"); 569 } 570 571 static int 572 urtwn_detach(device_t self, int flags) 573 { 574 struct urtwn_softc *sc = device_private(self); 575 struct ifnet *ifp = &sc->sc_if; 576 int s; 577 578 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 579 580 pmf_device_deregister(self); 581 582 s = splusb(); 583 584 sc->sc_dying = 1; 585 586 callout_halt(&sc->sc_scan_to, NULL); 587 callout_halt(&sc->sc_calib_to, NULL); 588 589 if (ISSET(sc->sc_flags, URTWN_FLAG_ATTACHED)) { 590 urtwn_stop(ifp, 0); 591 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 592 NULL); 593 594 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 595 bpf_detach(ifp); 596 ieee80211_ifdetach(&sc->sc_ic); 597 if_detach(ifp); 598 599 mutex_destroy(&sc->sc_media_mtx); 600 601 /* Close Tx/Rx pipes. Abort done by urtwn_stop. */ 602 urtwn_close_pipes(sc); 603 } 604 605 splx(s); 606 607 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 608 609 rnd_detach_source(&sc->rnd_source); 610 611 callout_destroy(&sc->sc_scan_to); 612 callout_destroy(&sc->sc_calib_to); 613 614 cv_destroy(&sc->sc_task_cv); 615 mutex_destroy(&sc->sc_write_mtx); 616 mutex_destroy(&sc->sc_fwcmd_mtx); 617 mutex_destroy(&sc->sc_tx_mtx); 618 mutex_destroy(&sc->sc_rx_mtx); 619 mutex_destroy(&sc->sc_task_mtx); 620 621 return 0; 622 } 623 624 static int 625 urtwn_activate(device_t self, enum devact act) 626 { 627 struct urtwn_softc *sc = device_private(self); 628 629 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 630 631 switch (act) { 632 case DVACT_DEACTIVATE: 633 if_deactivate(sc->sc_ic.ic_ifp); 634 return 0; 635 default: 636 return EOPNOTSUPP; 637 } 638 } 639 640 static int 641 urtwn_open_pipes(struct urtwn_softc *sc) 642 { 643 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 644 static uint8_t epaddr[R92C_MAX_EPOUT]; 645 static uint8_t rxepaddr[R92C_MAX_EPIN]; 646 usb_interface_descriptor_t *id; 647 usb_endpoint_descriptor_t *ed; 648 size_t i, ntx = 0, nrx = 0; 649 int error; 650 651 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 652 653 /* Determine the number of bulk-out pipes. */ 654 id = usbd_get_interface_descriptor(sc->sc_iface); 655 for (i = 0; i < id->bNumEndpoints; i++) { 656 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 657 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) { 658 continue; 659 } 660 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) { 661 if (ntx < sizeof(epaddr)) 662 epaddr[ntx] = ed->bEndpointAddress; 663 ntx++; 664 } 665 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 666 if (nrx < sizeof(rxepaddr)) 667 rxepaddr[nrx] = ed->bEndpointAddress; 668 nrx++; 669 } 670 } 671 if (nrx == 0 || nrx > R92C_MAX_EPIN) { 672 aprint_error_dev(sc->sc_dev, 673 "%zd: invalid number of Rx bulk pipes\n", nrx); 674 return EIO; 675 } 676 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 677 aprint_error_dev(sc->sc_dev, 678 "%zd: invalid number of Tx bulk pipes\n", ntx); 679 return EIO; 680 } 681 DPRINTFN(DBG_INIT, "found %jd/%jd bulk-in/out pipes", 682 nrx, ntx, 0, 0); 683 sc->rx_npipe = nrx; 684 sc->tx_npipe = ntx; 685 686 /* Open bulk-in pipe at address 0x81. */ 687 for (i = 0; i < nrx; i++) { 688 error = usbd_open_pipe(sc->sc_iface, rxepaddr[i], 689 USBD_EXCLUSIVE_USE, &sc->rx_pipe[i]); 690 if (error != 0) { 691 aprint_error_dev(sc->sc_dev, 692 "could not open Rx bulk pipe 0x%02x: %d\n", 693 rxepaddr[i], error); 694 goto fail; 695 } 696 } 697 698 /* Open bulk-out pipes (up to 3). */ 699 for (i = 0; i < ntx; i++) { 700 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 701 USBD_EXCLUSIVE_USE, &sc->tx_pipe[i]); 702 if (error != 0) { 703 aprint_error_dev(sc->sc_dev, 704 "could not open Tx bulk pipe 0x%02x: %d\n", 705 epaddr[i], error); 706 goto fail; 707 } 708 } 709 710 /* Map 802.11 access categories to USB pipes. */ 711 sc->ac2idx[WME_AC_BK] = 712 sc->ac2idx[WME_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 713 sc->ac2idx[WME_AC_VI] = (ntx == 3) ? 1 : 0; 714 sc->ac2idx[WME_AC_VO] = 0; /* Always use highest prio. */ 715 716 fail: 717 if (error != 0) 718 urtwn_close_pipes(sc); 719 return error; 720 } 721 722 static void 723 urtwn_close_pipes(struct urtwn_softc *sc) 724 { 725 struct usbd_pipe *pipe; 726 size_t i; 727 728 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 729 730 /* Close Rx pipes. */ 731 CTASSERT(sizeof(pipe) == sizeof(void *)); 732 for (i = 0; i < sc->rx_npipe; i++) { 733 pipe = atomic_swap_ptr(&sc->rx_pipe[i], NULL); 734 if (pipe != NULL) { 735 usbd_close_pipe(pipe); 736 } 737 } 738 739 /* Close Tx pipes. */ 740 for (i = 0; i < sc->tx_npipe; i++) { 741 pipe = atomic_swap_ptr(&sc->tx_pipe[i], NULL); 742 if (pipe != NULL) { 743 usbd_close_pipe(pipe); 744 } 745 } 746 } 747 748 static int __noinline 749 urtwn_alloc_rx_list(struct urtwn_softc *sc) 750 { 751 struct urtwn_rx_data *data; 752 size_t i; 753 int error = 0; 754 755 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 756 757 for (size_t j = 0; j < sc->rx_npipe; j++) { 758 TAILQ_INIT(&sc->rx_free_list[j]); 759 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 760 data = &sc->rx_data[j][i]; 761 762 data->sc = sc; /* Backpointer for callbacks. */ 763 data->pidx = j; 764 765 error = usbd_create_xfer(sc->rx_pipe[j], URTWN_RXBUFSZ, 766 0, 0, &data->xfer); 767 if (error) { 768 aprint_error_dev(sc->sc_dev, 769 "could not allocate xfer\n"); 770 break; 771 } 772 773 data->buf = usbd_get_buffer(data->xfer); 774 TAILQ_INSERT_TAIL(&sc->rx_free_list[j], data, next); 775 } 776 } 777 if (error != 0) 778 urtwn_free_rx_list(sc); 779 return error; 780 } 781 782 static void 783 urtwn_free_rx_list(struct urtwn_softc *sc) 784 { 785 struct usbd_xfer *xfer; 786 size_t i; 787 788 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 789 790 /* NB: Caller must abort pipe first. */ 791 for (size_t j = 0; j < sc->rx_npipe; j++) { 792 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 793 CTASSERT(sizeof(xfer) == sizeof(void *)); 794 xfer = atomic_swap_ptr(&sc->rx_data[j][i].xfer, NULL); 795 if (xfer != NULL) 796 usbd_destroy_xfer(xfer); 797 } 798 } 799 } 800 801 static int __noinline 802 urtwn_alloc_tx_list(struct urtwn_softc *sc) 803 { 804 struct urtwn_tx_data *data; 805 size_t i; 806 int error = 0; 807 808 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 809 810 mutex_enter(&sc->sc_tx_mtx); 811 for (size_t j = 0; j < sc->tx_npipe; j++) { 812 TAILQ_INIT(&sc->tx_free_list[j]); 813 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 814 data = &sc->tx_data[j][i]; 815 816 data->sc = sc; /* Backpointer for callbacks. */ 817 data->pidx = j; 818 819 error = usbd_create_xfer(sc->tx_pipe[j], 820 URTWN_TXBUFSZ, USBD_FORCE_SHORT_XFER, 0, 821 &data->xfer); 822 if (error) { 823 aprint_error_dev(sc->sc_dev, 824 "could not allocate xfer\n"); 825 goto fail; 826 } 827 828 data->buf = usbd_get_buffer(data->xfer); 829 830 /* Append this Tx buffer to our free list. */ 831 TAILQ_INSERT_TAIL(&sc->tx_free_list[j], data, next); 832 } 833 } 834 mutex_exit(&sc->sc_tx_mtx); 835 return 0; 836 837 fail: 838 urtwn_free_tx_list(sc); 839 mutex_exit(&sc->sc_tx_mtx); 840 return error; 841 } 842 843 static void 844 urtwn_free_tx_list(struct urtwn_softc *sc) 845 { 846 struct usbd_xfer *xfer; 847 size_t i; 848 849 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 850 851 /* NB: Caller must abort pipe first. */ 852 for (size_t j = 0; j < sc->tx_npipe; j++) { 853 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 854 CTASSERT(sizeof(xfer) == sizeof(void *)); 855 xfer = atomic_swap_ptr(&sc->tx_data[j][i].xfer, NULL); 856 if (xfer != NULL) 857 usbd_destroy_xfer(xfer); 858 } 859 } 860 } 861 862 static int 863 urtwn_tx_beacon(struct urtwn_softc *sc, struct mbuf *m, 864 struct ieee80211_node *ni) 865 { 866 struct urtwn_tx_data *data = 867 urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 868 869 if (data == NULL) 870 return ENOBUFS; 871 872 return urtwn_tx(sc, m, ni, data); 873 } 874 875 static void 876 urtwn_cmdq_invariants(struct urtwn_softc *sc) 877 { 878 struct urtwn_host_cmd_ring *const ring = &sc->cmdq; 879 880 KASSERT(mutex_owned(&sc->sc_task_mtx)); 881 KASSERTMSG((ring->cur >= 0 && ring->cur < URTWN_HOST_CMD_RING_COUNT), 882 "%s: cur=%d next=%d queued=%d", 883 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 884 KASSERTMSG((ring->next >= 0 && ring->next < URTWN_HOST_CMD_RING_COUNT), 885 "%s: cur=%d next=%d queued=%d", 886 device_xname(sc->sc_dev), ring->cur, ring->next, ring->queued); 887 KASSERTMSG((ring->queued >= 0 && 888 ring->queued <= URTWN_HOST_CMD_RING_COUNT), 889 "%s: %d commands queued", 890 device_xname(sc->sc_dev), ring->queued); 891 } 892 893 static void 894 urtwn_task(void *arg) 895 { 896 struct urtwn_softc *sc = arg; 897 struct ieee80211com *ic = &sc->sc_ic; 898 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 899 struct urtwn_host_cmd *cmd; 900 int s; 901 902 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 903 if (ic->ic_state == IEEE80211_S_RUN && 904 (ic->ic_opmode == IEEE80211_M_HOSTAP || 905 ic->ic_opmode == IEEE80211_M_IBSS)) { 906 907 struct mbuf *m = ieee80211_beacon_alloc(ic, ic->ic_bss, 908 &sc->sc_bo); 909 if (m == NULL) { 910 aprint_error_dev(sc->sc_dev, 911 "could not allocate beacon"); 912 } 913 914 if (urtwn_tx_beacon(sc, m, ic->ic_bss) != 0) { 915 aprint_error_dev(sc->sc_dev, "could not send beacon\n"); 916 } 917 918 /* beacon is no longer needed */ 919 m_freem(m); 920 } 921 922 /* Process host commands. */ 923 s = splusb(); 924 mutex_spin_enter(&sc->sc_task_mtx); 925 urtwn_cmdq_invariants(sc); 926 while (ring->next != ring->cur) { 927 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 928 device_xname(sc->sc_dev), 929 ring->cur, ring->next, ring->queued); 930 cmd = &ring->cmd[ring->next]; 931 mutex_spin_exit(&sc->sc_task_mtx); 932 splx(s); 933 /* Invoke callback with kernel lock held. */ 934 cmd->cb(sc, cmd->data); 935 s = splusb(); 936 mutex_spin_enter(&sc->sc_task_mtx); 937 urtwn_cmdq_invariants(sc); 938 KASSERTMSG(ring->queued > 0, "%s: cur=%d next=%d queued=%d", 939 device_xname(sc->sc_dev), 940 ring->cur, ring->next, ring->queued); 941 ring->queued--; 942 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 943 } 944 cv_broadcast(&sc->sc_task_cv); 945 mutex_spin_exit(&sc->sc_task_mtx); 946 splx(s); 947 } 948 949 static void 950 urtwn_do_async(struct urtwn_softc *sc, void (*cb)(struct urtwn_softc *, void *), 951 void *arg, int len) 952 { 953 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 954 struct urtwn_host_cmd *cmd; 955 bool schedtask = false; 956 int s; 957 958 URTWNHIST_FUNC(); 959 URTWNHIST_CALLARGS("cb=%#jx, arg=%#jx, len=%jd", 960 (uintptr_t)cb, (uintptr_t)arg, len, 0); 961 962 s = splusb(); 963 mutex_spin_enter(&sc->sc_task_mtx); 964 urtwn_cmdq_invariants(sc); 965 966 if (sc->sc_dying) { 967 mutex_spin_exit(&sc->sc_task_mtx); 968 splx(s); 969 return; 970 } 971 972 cmd = &ring->cmd[ring->cur]; 973 cmd->cb = cb; 974 KASSERT(len <= sizeof(cmd->data)); 975 memcpy(cmd->data, arg, len); 976 977 /* 978 * Schedule a task to process the command if need be. 979 */ 980 if (ring->queued == URTWN_HOST_CMD_RING_COUNT) 981 device_printf(sc->sc_dev, "command queue overflow\n"); 982 else { 983 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 984 if (ring->queued++ == 0) 985 schedtask = true; 986 } 987 988 mutex_spin_exit(&sc->sc_task_mtx); 989 splx(s); 990 991 if (schedtask) 992 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 993 } 994 995 static void 996 urtwn_wait_async(struct urtwn_softc *sc) 997 { 998 999 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1000 1001 /* Wait for all queued asynchronous commands to complete. */ 1002 mutex_spin_enter(&sc->sc_task_mtx); 1003 while (sc->cmdq.queued > 0) 1004 cv_wait(&sc->sc_task_cv, &sc->sc_task_mtx); 1005 mutex_spin_exit(&sc->sc_task_mtx); 1006 } 1007 1008 static int 1009 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1010 int len) 1011 { 1012 usb_device_request_t req; 1013 usbd_status error; 1014 1015 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1016 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1017 1018 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1019 req.bRequest = R92C_REQ_REGS; 1020 USETW(req.wValue, addr); 1021 USETW(req.wIndex, 0); 1022 USETW(req.wLength, len); 1023 error = usbd_do_request(sc->sc_udev, &req, buf); 1024 if (error != USBD_NORMAL_COMPLETION) { 1025 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1026 error, addr, len, 0); 1027 } 1028 return error; 1029 } 1030 1031 static void 1032 urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1033 { 1034 1035 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1036 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1037 1038 urtwn_write_region_1(sc, addr, &val, 1); 1039 } 1040 1041 static void 1042 urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1043 { 1044 uint8_t buf[2]; 1045 1046 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1047 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1048 1049 buf[0] = (uint8_t)val; 1050 buf[1] = (uint8_t)(val >> 8); 1051 urtwn_write_region_1(sc, addr, buf, 2); 1052 } 1053 1054 static void 1055 urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1056 { 1057 uint8_t buf[4]; 1058 1059 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1060 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1061 1062 buf[0] = (uint8_t)val; 1063 buf[1] = (uint8_t)(val >> 8); 1064 buf[2] = (uint8_t)(val >> 16); 1065 buf[3] = (uint8_t)(val >> 24); 1066 urtwn_write_region_1(sc, addr, buf, 4); 1067 } 1068 1069 static int 1070 urtwn_write_region(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, int len) 1071 { 1072 1073 URTWNHIST_FUNC(); 1074 URTWNHIST_CALLARGS("addr=%#jx, len=%#jx", addr, len, 0, 0); 1075 1076 return urtwn_write_region_1(sc, addr, buf, len); 1077 } 1078 1079 static int 1080 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1081 int len) 1082 { 1083 usb_device_request_t req; 1084 usbd_status error; 1085 1086 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1087 1088 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1089 req.bRequest = R92C_REQ_REGS; 1090 USETW(req.wValue, addr); 1091 USETW(req.wIndex, 0); 1092 USETW(req.wLength, len); 1093 error = usbd_do_request(sc->sc_udev, &req, buf); 1094 if (error != USBD_NORMAL_COMPLETION) { 1095 DPRINTFN(DBG_REG, "error=%jd: addr=%#jx, len=%jd", 1096 error, addr, len, 0); 1097 } 1098 return error; 1099 } 1100 1101 static uint8_t 1102 urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1103 { 1104 uint8_t val; 1105 1106 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1107 1108 if (urtwn_read_region_1(sc, addr, &val, 1) != USBD_NORMAL_COMPLETION) 1109 return 0xff; 1110 1111 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1112 return val; 1113 } 1114 1115 static uint16_t 1116 urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1117 { 1118 uint8_t buf[2]; 1119 uint16_t val; 1120 1121 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1122 1123 if (urtwn_read_region_1(sc, addr, buf, 2) != USBD_NORMAL_COMPLETION) 1124 return 0xffff; 1125 1126 val = LE_READ_2(&buf[0]); 1127 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1128 return val; 1129 } 1130 1131 static uint32_t 1132 urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1133 { 1134 uint8_t buf[4]; 1135 uint32_t val; 1136 1137 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1138 1139 if (urtwn_read_region_1(sc, addr, buf, 4) != USBD_NORMAL_COMPLETION) 1140 return 0xffffffff; 1141 1142 val = LE_READ_4(&buf[0]); 1143 DPRINTFN(DBG_REG, "addr=%#jx, val=%#jx", addr, val, 0, 0); 1144 return val; 1145 } 1146 1147 static int 1148 urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1149 { 1150 struct r92c_fw_cmd cmd; 1151 uint8_t *cp; 1152 int fwcur; 1153 int ntries; 1154 1155 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1156 DPRINTFN(DBG_REG, "id=%jd, buf=%#jx, len=%jd", id, (uintptr_t)buf, len, 0); 1157 1158 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1159 1160 mutex_enter(&sc->sc_fwcmd_mtx); 1161 fwcur = sc->fwcur; 1162 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1163 1164 /* Wait for current FW box to be empty. */ 1165 for (ntries = 0; ntries < 100; ntries++) { 1166 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << fwcur))) 1167 break; 1168 urtwn_delay_ms(sc, 2); 1169 } 1170 if (ntries == 100) { 1171 aprint_error_dev(sc->sc_dev, 1172 "could not send firmware command %d\n", id); 1173 mutex_exit(&sc->sc_fwcmd_mtx); 1174 return ETIMEDOUT; 1175 } 1176 1177 memset(&cmd, 0, sizeof(cmd)); 1178 KASSERT(len <= sizeof(cmd.msg)); 1179 memcpy(cmd.msg, buf, len); 1180 1181 /* Write the first word last since that will trigger the FW. */ 1182 cp = (uint8_t *)&cmd; 1183 cmd.id = id; 1184 if (len >= 4) { 1185 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1186 cmd.id |= R92C_CMD_FLAG_EXT; 1187 urtwn_write_region(sc, R92C_HMEBOX_EXT(fwcur), 1188 &cp[1], 2); 1189 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1190 cp[0] + (cp[3] << 8) + (cp[4] << 16) + 1191 ((uint32_t)cp[5] << 24)); 1192 } else { 1193 urtwn_write_region(sc, R92E_HMEBOX_EXT(fwcur), 1194 &cp[4], 2); 1195 urtwn_write_4(sc, R92C_HMEBOX(fwcur), 1196 cp[0] + (cp[1] << 8) + (cp[2] << 16) + 1197 ((uint32_t)cp[3] << 24)); 1198 } 1199 } else { 1200 urtwn_write_region(sc, R92C_HMEBOX(fwcur), cp, len); 1201 } 1202 mutex_exit(&sc->sc_fwcmd_mtx); 1203 1204 return 0; 1205 } 1206 1207 static __inline void 1208 urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1209 { 1210 1211 sc->sc_rf_write(sc, chain, addr, val); 1212 } 1213 1214 static void 1215 urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1216 uint32_t val) 1217 { 1218 1219 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1220 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1221 } 1222 1223 static void 1224 urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1225 uint32_t val) 1226 { 1227 1228 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1229 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1230 } 1231 1232 static void 1233 urtwn_r92e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1234 uint32_t val) 1235 { 1236 1237 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1238 SM(R88E_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 1239 } 1240 1241 static uint32_t 1242 urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1243 { 1244 uint32_t reg[R92C_MAX_CHAINS], val; 1245 1246 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1247 if (chain != 0) { 1248 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1249 } 1250 1251 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1252 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1253 urtwn_delay_ms(sc, 1); 1254 1255 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1256 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1257 R92C_HSSI_PARAM2_READ_EDGE); 1258 urtwn_delay_ms(sc, 1); 1259 1260 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1261 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1262 urtwn_delay_ms(sc, 1); 1263 1264 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) { 1265 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1266 } else { 1267 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1268 } 1269 return MS(val, R92C_LSSI_READBACK_DATA); 1270 } 1271 1272 static int 1273 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1274 { 1275 int ntries; 1276 1277 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1278 1279 urtwn_write_4(sc, R92C_LLT_INIT, 1280 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1281 SM(R92C_LLT_INIT_ADDR, addr) | 1282 SM(R92C_LLT_INIT_DATA, data)); 1283 /* Wait for write operation to complete. */ 1284 for (ntries = 0; ntries < 20; ntries++) { 1285 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1286 R92C_LLT_INIT_OP_NO_ACTIVE) { 1287 /* Done */ 1288 return 0; 1289 } 1290 DELAY(5); 1291 } 1292 return ETIMEDOUT; 1293 } 1294 1295 static uint8_t 1296 urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1297 { 1298 uint32_t reg; 1299 int ntries; 1300 1301 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1302 1303 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1304 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1305 reg &= ~R92C_EFUSE_CTRL_VALID; 1306 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1307 1308 /* Wait for read operation to complete. */ 1309 for (ntries = 0; ntries < 100; ntries++) { 1310 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1311 if (reg & R92C_EFUSE_CTRL_VALID) { 1312 /* Done */ 1313 return MS(reg, R92C_EFUSE_CTRL_DATA); 1314 } 1315 DELAY(5); 1316 } 1317 aprint_error_dev(sc->sc_dev, 1318 "could not read efuse byte at address 0x%04x\n", addr); 1319 return 0xff; 1320 } 1321 1322 static void 1323 urtwn_efuse_read(struct urtwn_softc *sc) 1324 { 1325 uint8_t *rom = (uint8_t *)&sc->rom; 1326 uint32_t reg; 1327 uint16_t addr = 0; 1328 uint8_t off, msk; 1329 size_t i; 1330 1331 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1332 1333 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1334 1335 urtwn_efuse_switch_power(sc); 1336 1337 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1338 while (addr < 512) { 1339 reg = urtwn_efuse_read_1(sc, addr); 1340 if (reg == 0xff) 1341 break; 1342 addr++; 1343 off = reg >> 4; 1344 msk = reg & 0xf; 1345 for (i = 0; i < 4; i++) { 1346 if (msk & (1U << i)) 1347 continue; 1348 1349 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1350 addr++; 1351 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1352 addr++; 1353 } 1354 } 1355 #ifdef URTWN_DEBUG 1356 /* Dump ROM content. */ 1357 for (i = 0; i < (int)sizeof(sc->rom); i++) 1358 DPRINTFN(DBG_INIT, "%04jx: %02jx", i, rom[i], 0, 0); 1359 #endif 1360 } 1361 1362 static void 1363 urtwn_efuse_switch_power(struct urtwn_softc *sc) 1364 { 1365 uint32_t reg; 1366 1367 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1368 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1369 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1370 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1371 } 1372 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1373 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1374 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1375 reg | R92C_SYS_FUNC_EN_ELDR); 1376 } 1377 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1378 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1379 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1380 urtwn_write_2(sc, R92C_SYS_CLKR, 1381 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1382 } 1383 } 1384 1385 static int 1386 urtwn_read_chipid(struct urtwn_softc *sc) 1387 { 1388 uint32_t reg; 1389 1390 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1391 1392 if (ISSET(sc->chip, URTWN_CHIP_88E) || 1393 ISSET(sc->chip, URTWN_CHIP_92EU)) 1394 return 0; 1395 1396 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1397 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) { 1398 /* test chip, not supported */ 1399 return EIO; 1400 } 1401 if (reg & R92C_SYS_CFG_TYPE_92C) { 1402 sc->chip |= URTWN_CHIP_92C; 1403 /* Check if it is a castrated 8192C. */ 1404 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1405 R92C_HPON_FSM_CHIP_BONDING_ID) == 1406 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) { 1407 sc->chip |= URTWN_CHIP_92C_1T2R; 1408 } 1409 } 1410 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1411 sc->chip |= URTWN_CHIP_UMC; 1412 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) { 1413 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1414 } 1415 } 1416 return 0; 1417 } 1418 1419 #ifdef URTWN_DEBUG 1420 static void 1421 urtwn_dump_rom(struct urtwn_softc *sc, struct r92c_rom *rp) 1422 { 1423 1424 aprint_normal_dev(sc->sc_dev, 1425 "id 0x%04x, dbg_sel %#x, vid %#x, pid %#x\n", 1426 rp->id, rp->dbg_sel, rp->vid, rp->pid); 1427 1428 aprint_normal_dev(sc->sc_dev, 1429 "usb_opt %#x, ep_setting %#x, usb_phy %#x\n", 1430 rp->usb_opt, rp->ep_setting, rp->usb_phy); 1431 1432 aprint_normal_dev(sc->sc_dev, 1433 "macaddr %s\n", 1434 ether_sprintf(rp->macaddr)); 1435 1436 aprint_normal_dev(sc->sc_dev, 1437 "string %s, subcustomer_id %#x\n", 1438 rp->string, rp->subcustomer_id); 1439 1440 aprint_normal_dev(sc->sc_dev, 1441 "cck_tx_pwr c0: %d %d %d, c1: %d %d %d\n", 1442 rp->cck_tx_pwr[0][0], rp->cck_tx_pwr[0][1], rp->cck_tx_pwr[0][2], 1443 rp->cck_tx_pwr[1][0], rp->cck_tx_pwr[1][1], rp->cck_tx_pwr[1][2]); 1444 1445 aprint_normal_dev(sc->sc_dev, 1446 "ht40_1s_tx_pwr c0 %d %d %d, c1 %d %d %d\n", 1447 rp->ht40_1s_tx_pwr[0][0], rp->ht40_1s_tx_pwr[0][1], 1448 rp->ht40_1s_tx_pwr[0][2], 1449 rp->ht40_1s_tx_pwr[1][0], rp->ht40_1s_tx_pwr[1][1], 1450 rp->ht40_1s_tx_pwr[1][2]); 1451 1452 aprint_normal_dev(sc->sc_dev, 1453 "ht40_2s_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1454 rp->ht40_2s_tx_pwr_diff[0] & 0xf, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1455 rp->ht40_2s_tx_pwr_diff[2] & 0xf, 1456 rp->ht40_2s_tx_pwr_diff[0] >> 4, rp->ht40_2s_tx_pwr_diff[1] & 0xf, 1457 rp->ht40_2s_tx_pwr_diff[2] >> 4); 1458 1459 aprint_normal_dev(sc->sc_dev, 1460 "ht20_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1461 rp->ht20_tx_pwr_diff[0] & 0xf, rp->ht20_tx_pwr_diff[1] & 0xf, 1462 rp->ht20_tx_pwr_diff[2] & 0xf, 1463 rp->ht20_tx_pwr_diff[0] >> 4, rp->ht20_tx_pwr_diff[1] >> 4, 1464 rp->ht20_tx_pwr_diff[2] >> 4); 1465 1466 aprint_normal_dev(sc->sc_dev, 1467 "ofdm_tx_pwr_diff c0: %d %d %d, c1: %d %d %d\n", 1468 rp->ofdm_tx_pwr_diff[0] & 0xf, rp->ofdm_tx_pwr_diff[1] & 0xf, 1469 rp->ofdm_tx_pwr_diff[2] & 0xf, 1470 rp->ofdm_tx_pwr_diff[0] >> 4, rp->ofdm_tx_pwr_diff[1] >> 4, 1471 rp->ofdm_tx_pwr_diff[2] >> 4); 1472 1473 aprint_normal_dev(sc->sc_dev, 1474 "ht40_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1475 rp->ht40_max_pwr[0] & 0xf, rp->ht40_max_pwr[1] & 0xf, 1476 rp->ht40_max_pwr[2] & 0xf, 1477 rp->ht40_max_pwr[0] >> 4, rp->ht40_max_pwr[1] >> 4, 1478 rp->ht40_max_pwr[2] >> 4); 1479 1480 aprint_normal_dev(sc->sc_dev, 1481 "ht20_max_pwr_offset c0: %d %d %d, c1: %d %d %d\n", 1482 rp->ht20_max_pwr[0] & 0xf, rp->ht20_max_pwr[1] & 0xf, 1483 rp->ht20_max_pwr[2] & 0xf, 1484 rp->ht20_max_pwr[0] >> 4, rp->ht20_max_pwr[1] >> 4, 1485 rp->ht20_max_pwr[2] >> 4); 1486 1487 aprint_normal_dev(sc->sc_dev, 1488 "xtal_calib %d, tssi %d %d, thermal %d\n", 1489 rp->xtal_calib, rp->tssi[0], rp->tssi[1], rp->thermal_meter); 1490 1491 aprint_normal_dev(sc->sc_dev, 1492 "rf_opt1 %#x, rf_opt2 %#x, rf_opt3 %#x, rf_opt4 %#x\n", 1493 rp->rf_opt1, rp->rf_opt2, rp->rf_opt3, rp->rf_opt4); 1494 1495 aprint_normal_dev(sc->sc_dev, 1496 "channnel_plan %d, version %d customer_id %#x\n", 1497 rp->channel_plan, rp->version, rp->curstomer_id); 1498 } 1499 #endif 1500 1501 static void 1502 urtwn_read_rom(struct urtwn_softc *sc) 1503 { 1504 struct ieee80211com *ic = &sc->sc_ic; 1505 struct r92c_rom *rom = &sc->rom; 1506 1507 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1508 1509 mutex_enter(&sc->sc_write_mtx); 1510 1511 /* Read full ROM image. */ 1512 urtwn_efuse_read(sc); 1513 #ifdef URTWN_DEBUG 1514 if (urtwn_debug & DBG_REG) 1515 urtwn_dump_rom(sc, rom); 1516 #endif 1517 1518 /* XXX Weird but this is what the vendor driver does. */ 1519 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1520 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1521 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1522 1523 DPRINTFN(DBG_INIT, 1524 "PA setting=%#jx, board=%#jx, regulatory=%jd", 1525 sc->pa_setting, sc->board_type, sc->regulatory, 0); 1526 1527 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1528 1529 sc->sc_rf_write = urtwn_r92c_rf_write; 1530 sc->sc_power_on = urtwn_r92c_power_on; 1531 sc->sc_dma_init = urtwn_r92c_dma_init; 1532 1533 mutex_exit(&sc->sc_write_mtx); 1534 } 1535 1536 static void 1537 urtwn_r88e_read_rom(struct urtwn_softc *sc) 1538 { 1539 struct ieee80211com *ic = &sc->sc_ic; 1540 uint8_t *rom = sc->r88e_rom; 1541 uint32_t reg; 1542 uint16_t addr = 0; 1543 uint8_t off, msk, tmp; 1544 int i; 1545 1546 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1547 1548 mutex_enter(&sc->sc_write_mtx); 1549 1550 off = 0; 1551 urtwn_efuse_switch_power(sc); 1552 1553 /* Read full ROM image. */ 1554 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1555 while (addr < 4096) { 1556 reg = urtwn_efuse_read_1(sc, addr); 1557 if (reg == 0xff) 1558 break; 1559 addr++; 1560 if ((reg & 0x1f) == 0x0f) { 1561 tmp = (reg & 0xe0) >> 5; 1562 reg = urtwn_efuse_read_1(sc, addr); 1563 if ((reg & 0x0f) != 0x0f) 1564 off = ((reg & 0xf0) >> 1) | tmp; 1565 addr++; 1566 } else 1567 off = reg >> 4; 1568 msk = reg & 0xf; 1569 for (i = 0; i < 4; i++) { 1570 if (msk & (1 << i)) 1571 continue; 1572 rom[off * 8 + i * 2 + 0] = urtwn_efuse_read_1(sc, addr); 1573 addr++; 1574 rom[off * 8 + i * 2 + 1] = urtwn_efuse_read_1(sc, addr); 1575 addr++; 1576 } 1577 } 1578 #ifdef URTWN_DEBUG 1579 if (urtwn_debug & DBG_REG) { 1580 } 1581 #endif 1582 1583 addr = 0x10; 1584 for (i = 0; i < 6; i++) 1585 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1586 for (i = 0; i < 5; i++) 1587 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1588 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1589 if (sc->bw20_tx_pwr_diff & 0x08) 1590 sc->bw20_tx_pwr_diff |= 0xf0; 1591 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1592 if (sc->ofdm_tx_pwr_diff & 0x08) 1593 sc->ofdm_tx_pwr_diff |= 0xf0; 1594 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1595 1596 IEEE80211_ADDR_COPY(ic->ic_myaddr, &sc->r88e_rom[0xd7]); 1597 1598 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1599 sc->sc_power_on = urtwn_r92e_power_on; 1600 sc->sc_rf_write = urtwn_r92e_rf_write; 1601 } else { 1602 sc->sc_power_on = urtwn_r88e_power_on; 1603 sc->sc_rf_write = urtwn_r88e_rf_write; 1604 } 1605 sc->sc_dma_init = urtwn_r88e_dma_init; 1606 1607 mutex_exit(&sc->sc_write_mtx); 1608 } 1609 1610 static int 1611 urtwn_media_change(struct ifnet *ifp) 1612 { 1613 int error; 1614 1615 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1616 1617 if ((error = ieee80211_media_change(ifp)) != ENETRESET) 1618 return error; 1619 1620 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1621 (IFF_UP | IFF_RUNNING)) { 1622 urtwn_init(ifp); 1623 } 1624 return 0; 1625 } 1626 1627 /* 1628 * Initialize rate adaptation in firmware. 1629 */ 1630 static int __noinline 1631 urtwn_ra_init(struct urtwn_softc *sc) 1632 { 1633 static const uint8_t map[] = { 1634 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1635 }; 1636 struct ieee80211com *ic = &sc->sc_ic; 1637 struct ieee80211_node *ni = ic->ic_bss; 1638 struct ieee80211_rateset *rs = &ni->ni_rates; 1639 struct r92c_fw_cmd_macid_cfg cmd; 1640 uint32_t rates, basicrates; 1641 uint32_t rrsr_mask, rrsr_rate; 1642 uint8_t mode; 1643 size_t maxrate, maxbasicrate, i, j; 1644 int error; 1645 1646 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1647 1648 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1649 1650 /* Get normal and basic rates mask. */ 1651 rates = basicrates = 1; 1652 maxrate = maxbasicrate = 0; 1653 for (i = 0; i < rs->rs_nrates; i++) { 1654 /* Convert 802.11 rate to HW rate index. */ 1655 for (j = 0; j < __arraycount(map); j++) { 1656 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) { 1657 break; 1658 } 1659 } 1660 if (j == __arraycount(map)) { 1661 /* Unknown rate, skip. */ 1662 continue; 1663 } 1664 1665 rates |= 1U << j; 1666 if (j > maxrate) { 1667 maxrate = j; 1668 } 1669 1670 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1671 basicrates |= 1U << j; 1672 if (j > maxbasicrate) { 1673 maxbasicrate = j; 1674 } 1675 } 1676 } 1677 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1678 mode = R92C_RAID_11B; 1679 } else { 1680 mode = R92C_RAID_11BG; 1681 } 1682 DPRINTFN(DBG_INIT, "mode=%#jx", mode, 0, 0, 0); 1683 DPRINTFN(DBG_INIT, "rates=%#jx, basicrates=%#jx, " 1684 "maxrate=%jx, maxbasicrate=%jx", 1685 rates, basicrates, maxrate, maxbasicrate); 1686 1687 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) { 1688 maxbasicrate |= R92C_RATE_SHORTGI; 1689 maxrate |= R92C_RATE_SHORTGI; 1690 } 1691 1692 /* Set rates mask for group addressed frames. */ 1693 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1694 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1695 cmd.macid |= RTWN_MACID_SHORTGI; 1696 cmd.mask = htole32((mode << 28) | basicrates); 1697 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1698 if (error != 0) { 1699 aprint_error_dev(sc->sc_dev, 1700 "could not add broadcast station\n"); 1701 return error; 1702 } 1703 /* Set initial MRR rate. */ 1704 DPRINTFN(DBG_INIT, "maxbasicrate=%jd", maxbasicrate, 0, 0, 0); 1705 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1706 1707 /* Set rates mask for unicast frames. */ 1708 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1709 if (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) 1710 cmd.macid |= RTWN_MACID_SHORTGI; 1711 cmd.mask = htole32((mode << 28) | rates); 1712 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1713 if (error != 0) { 1714 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1715 return error; 1716 } 1717 /* Set initial MRR rate. */ 1718 DPRINTFN(DBG_INIT, "maxrate=%jd", maxrate, 0, 0, 0); 1719 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1720 1721 rrsr_rate = ic->ic_fixed_rate; 1722 if (rrsr_rate == -1) 1723 rrsr_rate = 11; 1724 1725 rrsr_mask = 0xffff >> (15 - rrsr_rate); 1726 urtwn_write_2(sc, R92C_RRSR, rrsr_mask); 1727 1728 /* Indicate highest supported rate. */ 1729 ni->ni_txrate = rs->rs_nrates - 1; 1730 1731 return 0; 1732 } 1733 1734 static int 1735 urtwn_get_nettype(struct urtwn_softc *sc) 1736 { 1737 struct ieee80211com *ic = &sc->sc_ic; 1738 int type; 1739 1740 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1741 1742 switch (ic->ic_opmode) { 1743 case IEEE80211_M_STA: 1744 type = R92C_CR_NETTYPE_INFRA; 1745 break; 1746 1747 case IEEE80211_M_IBSS: 1748 type = R92C_CR_NETTYPE_ADHOC; 1749 break; 1750 1751 default: 1752 type = R92C_CR_NETTYPE_NOLINK; 1753 break; 1754 } 1755 1756 return type; 1757 } 1758 1759 static void 1760 urtwn_set_nettype0_msr(struct urtwn_softc *sc, uint8_t type) 1761 { 1762 uint8_t reg; 1763 1764 URTWNHIST_FUNC(); 1765 URTWNHIST_CALLARGS("type=%jd", type, 0, 0, 0); 1766 1767 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1768 1769 reg = urtwn_read_1(sc, R92C_CR + 2) & 0x0c; 1770 urtwn_write_1(sc, R92C_CR + 2, reg | type); 1771 } 1772 1773 static void 1774 urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1775 { 1776 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1777 uint64_t tsf; 1778 1779 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1780 1781 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1782 1783 /* Enable TSF synchronization. */ 1784 urtwn_write_1(sc, R92C_BCN_CTRL, 1785 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1786 1787 /* Correct TSF */ 1788 urtwn_write_1(sc, R92C_BCN_CTRL, 1789 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1790 1791 /* Set initial TSF. */ 1792 tsf = ni->ni_tstamp.tsf; 1793 tsf = le64toh(tsf); 1794 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1795 tsf -= IEEE80211_DUR_TU; 1796 urtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1797 urtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1798 1799 urtwn_write_1(sc, R92C_BCN_CTRL, 1800 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1801 } 1802 1803 static void 1804 urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1805 { 1806 uint8_t reg; 1807 1808 URTWNHIST_FUNC(); 1809 URTWNHIST_CALLARGS("led=%jd, on=%jd", led, on, 0, 0); 1810 1811 KASSERT(mutex_owned(&sc->sc_write_mtx)); 1812 1813 if (led == URTWN_LED_LINK) { 1814 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 1815 urtwn_write_1(sc, 0x64, urtwn_read_1(sc, 0x64) & 0xfe); 1816 reg = urtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 1817 urtwn_write_1(sc, R92C_LEDCFG1, reg | 1818 (R92C_LEDCFG0_DIS << 1)); 1819 if (on) { 1820 reg = urtwn_read_1(sc, R92C_LEDCFG1) & 1821 R92E_LEDSON; 1822 urtwn_write_1(sc, R92C_LEDCFG1, reg); 1823 } 1824 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 1825 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1826 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1827 if (!on) { 1828 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1829 urtwn_write_1(sc, R92C_LEDCFG2, 1830 reg | R92C_LEDCFG0_DIS); 1831 reg = urtwn_read_1(sc, R92C_MAC_PINMUX_CFG); 1832 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1833 reg & 0xfe); 1834 } 1835 } else { 1836 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1837 if (!on) { 1838 reg |= R92C_LEDCFG0_DIS; 1839 } 1840 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1841 } 1842 sc->ledlink = on; /* Save LED state. */ 1843 } 1844 } 1845 1846 static void 1847 urtwn_calib_to(void *arg) 1848 { 1849 struct urtwn_softc *sc = arg; 1850 1851 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1852 1853 if (sc->sc_dying) 1854 return; 1855 1856 /* Do it in a process context. */ 1857 urtwn_do_async(sc, urtwn_calib_to_cb, NULL, 0); 1858 } 1859 1860 /* ARGSUSED */ 1861 static void 1862 urtwn_calib_to_cb(struct urtwn_softc *sc, void *arg) 1863 { 1864 struct r92c_fw_cmd_rssi cmd; 1865 struct r92e_fw_cmd_rssi cmde; 1866 1867 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1868 1869 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1870 goto restart_timer; 1871 1872 mutex_enter(&sc->sc_write_mtx); 1873 if (sc->avg_pwdb != -1) { 1874 /* Indicate Rx signal strength to FW for rate adaptation. */ 1875 memset(&cmd, 0, sizeof(cmd)); 1876 memset(&cmde, 0, sizeof(cmde)); 1877 cmd.macid = 0; /* BSS. */ 1878 cmde.macid = 0; /* BSS. */ 1879 cmd.pwdb = sc->avg_pwdb; 1880 cmde.pwdb = sc->avg_pwdb; 1881 DPRINTFN(DBG_RF, "sending RSSI command avg=%jd", 1882 sc->avg_pwdb, 0, 0, 0); 1883 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 1884 urtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1885 sizeof(cmd)); 1886 } else { 1887 urtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmde, 1888 sizeof(cmde)); 1889 } 1890 } 1891 1892 /* Do temperature compensation. */ 1893 urtwn_temp_calib(sc); 1894 mutex_exit(&sc->sc_write_mtx); 1895 1896 restart_timer: 1897 if (!sc->sc_dying) { 1898 /* Restart calibration timer. */ 1899 callout_schedule(&sc->sc_calib_to, hz); 1900 } 1901 } 1902 1903 static void 1904 urtwn_next_scan(void *arg) 1905 { 1906 struct urtwn_softc *sc = arg; 1907 int s; 1908 1909 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1910 1911 if (sc->sc_dying) 1912 return; 1913 1914 s = splnet(); 1915 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1916 ieee80211_next_scan(&sc->sc_ic); 1917 splx(s); 1918 } 1919 1920 static void 1921 urtwn_newassoc(struct ieee80211_node *ni, int isnew) 1922 { 1923 URTWNHIST_FUNC(); 1924 URTWNHIST_CALLARGS("new node %06jx%06jx", 1925 ni->ni_macaddr[0] << 2 | 1926 ni->ni_macaddr[1] << 1 | 1927 ni->ni_macaddr[2], 1928 ni->ni_macaddr[3] << 2 | 1929 ni->ni_macaddr[4] << 1 | 1930 ni->ni_macaddr[5], 1931 0, 0); 1932 /* start with lowest Tx rate */ 1933 ni->ni_txrate = 0; 1934 } 1935 1936 static int 1937 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1938 { 1939 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1940 struct urtwn_cmd_newstate cmd; 1941 1942 URTWNHIST_FUNC(); 1943 URTWNHIST_CALLARGS("nstate=%jd, arg=%jd", nstate, arg, 0, 0); 1944 1945 callout_stop(&sc->sc_scan_to); 1946 callout_stop(&sc->sc_calib_to); 1947 1948 /* Do it in a process context. */ 1949 cmd.state = nstate; 1950 cmd.arg = arg; 1951 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 1952 return 0; 1953 } 1954 1955 static void 1956 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 1957 { 1958 struct urtwn_cmd_newstate *cmd = arg; 1959 struct ieee80211com *ic = &sc->sc_ic; 1960 struct ieee80211_node *ni; 1961 enum ieee80211_state ostate = ic->ic_state; 1962 enum ieee80211_state nstate = cmd->state; 1963 uint32_t reg; 1964 uint8_t sifs_time, msr; 1965 int s; 1966 1967 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 1968 DPRINTFN(DBG_STM, "%jd->%jd", ostate, nstate, 0, 0); 1969 1970 s = splnet(); 1971 mutex_enter(&sc->sc_write_mtx); 1972 1973 callout_stop(&sc->sc_scan_to); 1974 callout_stop(&sc->sc_calib_to); 1975 1976 switch (ostate) { 1977 case IEEE80211_S_INIT: 1978 break; 1979 1980 case IEEE80211_S_SCAN: 1981 if (nstate != IEEE80211_S_SCAN) { 1982 /* 1983 * End of scanning 1984 */ 1985 /* flush 4-AC Queue after site_survey */ 1986 urtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1987 1988 /* Allow Rx from our BSSID only. */ 1989 urtwn_write_4(sc, R92C_RCR, 1990 urtwn_read_4(sc, R92C_RCR) | 1991 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1992 } 1993 break; 1994 1995 case IEEE80211_S_AUTH: 1996 case IEEE80211_S_ASSOC: 1997 break; 1998 1999 case IEEE80211_S_RUN: 2000 /* Turn link LED off. */ 2001 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2002 2003 /* Set media status to 'No Link'. */ 2004 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2005 2006 /* Stop Rx of data frames. */ 2007 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2008 2009 /* Reset TSF. */ 2010 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 2011 2012 /* Disable TSF synchronization. */ 2013 urtwn_write_1(sc, R92C_BCN_CTRL, 2014 urtwn_read_1(sc, R92C_BCN_CTRL) | 2015 R92C_BCN_CTRL_DIS_TSF_UDT0); 2016 2017 /* Back to 20MHz mode */ 2018 urtwn_set_chan(sc, ic->ic_curchan, 2019 IEEE80211_HTINFO_2NDCHAN_NONE); 2020 2021 if (ic->ic_opmode == IEEE80211_M_IBSS || 2022 ic->ic_opmode == IEEE80211_M_HOSTAP) { 2023 /* Stop BCN */ 2024 urtwn_write_1(sc, R92C_BCN_CTRL, 2025 urtwn_read_1(sc, R92C_BCN_CTRL) & 2026 ~(R92C_BCN_CTRL_EN_BCN | R92C_BCN_CTRL_TXBCN_RPT)); 2027 } 2028 2029 /* Reset EDCA parameters. */ 2030 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 2031 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 2032 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 2033 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 2034 2035 /* flush all cam entries */ 2036 urtwn_cam_init(sc); 2037 break; 2038 } 2039 2040 switch (nstate) { 2041 case IEEE80211_S_INIT: 2042 /* Turn link LED off. */ 2043 urtwn_set_led(sc, URTWN_LED_LINK, 0); 2044 break; 2045 2046 case IEEE80211_S_SCAN: 2047 if (ostate != IEEE80211_S_SCAN) { 2048 /* 2049 * Begin of scanning 2050 */ 2051 2052 /* Set gain for scanning. */ 2053 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2054 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2055 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2056 2057 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2058 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2059 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 2060 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2061 } 2062 2063 /* Set media status to 'No Link'. */ 2064 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2065 2066 /* Allow Rx from any BSSID. */ 2067 urtwn_write_4(sc, R92C_RCR, 2068 urtwn_read_4(sc, R92C_RCR) & 2069 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2070 2071 /* Stop Rx of data frames. */ 2072 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 2073 2074 /* Disable update TSF */ 2075 urtwn_write_1(sc, R92C_BCN_CTRL, 2076 urtwn_read_1(sc, R92C_BCN_CTRL) | 2077 R92C_BCN_CTRL_DIS_TSF_UDT0); 2078 } 2079 2080 /* Make link LED blink during scan. */ 2081 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 2082 2083 /* Pause AC Tx queues. */ 2084 urtwn_write_1(sc, R92C_TXPAUSE, 2085 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 2086 2087 urtwn_set_chan(sc, ic->ic_curchan, 2088 IEEE80211_HTINFO_2NDCHAN_NONE); 2089 2090 /* Start periodic scan. */ 2091 if (!sc->sc_dying) 2092 callout_schedule(&sc->sc_scan_to, hz / 5); 2093 break; 2094 2095 case IEEE80211_S_AUTH: 2096 /* Set initial gain under link. */ 2097 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2098 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2099 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 2100 2101 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2102 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2103 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2104 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 2105 } 2106 2107 /* Set media status to 'No Link'. */ 2108 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2109 2110 /* Allow Rx from any BSSID. */ 2111 urtwn_write_4(sc, R92C_RCR, 2112 urtwn_read_4(sc, R92C_RCR) & 2113 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2114 2115 urtwn_set_chan(sc, ic->ic_curchan, 2116 IEEE80211_HTINFO_2NDCHAN_NONE); 2117 break; 2118 2119 case IEEE80211_S_ASSOC: 2120 break; 2121 2122 case IEEE80211_S_RUN: 2123 ni = ic->ic_bss; 2124 2125 /* XXX: Set 20MHz mode */ 2126 urtwn_set_chan(sc, ic->ic_curchan, 2127 IEEE80211_HTINFO_2NDCHAN_NONE); 2128 2129 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2130 /* Back to 20MHz mode */ 2131 urtwn_set_chan(sc, ic->ic_curchan, 2132 IEEE80211_HTINFO_2NDCHAN_NONE); 2133 2134 /* Set media status to 'No Link'. */ 2135 urtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 2136 2137 /* Enable Rx of data frames. */ 2138 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2139 2140 /* Allow Rx from any BSSID. */ 2141 urtwn_write_4(sc, R92C_RCR, 2142 urtwn_read_4(sc, R92C_RCR) & 2143 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2144 2145 /* Accept Rx data/control/management frames */ 2146 urtwn_write_4(sc, R92C_RCR, 2147 urtwn_read_4(sc, R92C_RCR) | 2148 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 2149 2150 /* Turn link LED on. */ 2151 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2152 break; 2153 } 2154 2155 /* Set media status to 'Associated'. */ 2156 urtwn_set_nettype0_msr(sc, urtwn_get_nettype(sc)); 2157 2158 /* Set BSSID. */ 2159 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 2160 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 2161 2162 if (ic->ic_curmode == IEEE80211_MODE_11B) { 2163 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 2164 } else { 2165 /* 802.11b/g */ 2166 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 2167 } 2168 2169 /* Enable Rx of data frames. */ 2170 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2171 2172 /* Set beacon interval. */ 2173 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 2174 2175 msr = urtwn_read_1(sc, R92C_MSR); 2176 msr &= R92C_MSR_MASK; 2177 switch (ic->ic_opmode) { 2178 case IEEE80211_M_STA: 2179 /* Allow Rx from our BSSID only. */ 2180 urtwn_write_4(sc, R92C_RCR, 2181 urtwn_read_4(sc, R92C_RCR) | 2182 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 2183 2184 /* Enable TSF synchronization. */ 2185 urtwn_tsf_sync_enable(sc); 2186 2187 msr |= R92C_MSR_INFRA; 2188 break; 2189 case IEEE80211_M_HOSTAP: 2190 urtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 2191 2192 /* Allow Rx from any BSSID. */ 2193 urtwn_write_4(sc, R92C_RCR, 2194 urtwn_read_4(sc, R92C_RCR) & 2195 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 2196 2197 /* Reset TSF timer to zero. */ 2198 reg = urtwn_read_4(sc, R92C_TCR); 2199 reg &= ~0x01; 2200 urtwn_write_4(sc, R92C_TCR, reg); 2201 reg |= 0x01; 2202 urtwn_write_4(sc, R92C_TCR, reg); 2203 2204 msr |= R92C_MSR_AP; 2205 break; 2206 default: 2207 msr |= R92C_MSR_ADHOC; 2208 break; 2209 } 2210 urtwn_write_1(sc, R92C_MSR, msr); 2211 2212 sifs_time = 10; 2213 urtwn_write_1(sc, R92C_SIFS_CCK + 1, sifs_time); 2214 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, sifs_time); 2215 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, sifs_time); 2216 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, sifs_time); 2217 urtwn_write_1(sc, R92C_R2T_SIFS + 1, sifs_time); 2218 urtwn_write_1(sc, R92C_T2T_SIFS + 1, sifs_time); 2219 2220 /* Initialize rate adaptation. */ 2221 if (ISSET(sc->chip, URTWN_CHIP_88E) || 2222 ISSET(sc->chip, URTWN_CHIP_92EU)) 2223 ni->ni_txrate = ni->ni_rates.rs_nrates - 1; 2224 else 2225 urtwn_ra_init(sc); 2226 2227 /* Turn link LED on. */ 2228 urtwn_set_led(sc, URTWN_LED_LINK, 1); 2229 2230 /* Reset average RSSI. */ 2231 sc->avg_pwdb = -1; 2232 2233 /* Reset temperature calibration state machine. */ 2234 sc->thcal_state = 0; 2235 sc->thcal_lctemp = 0; 2236 2237 /* Start periodic calibration. */ 2238 if (!sc->sc_dying) 2239 callout_schedule(&sc->sc_calib_to, hz); 2240 break; 2241 } 2242 2243 (*sc->sc_newstate)(ic, nstate, cmd->arg); 2244 2245 mutex_exit(&sc->sc_write_mtx); 2246 splx(s); 2247 } 2248 2249 static int 2250 urtwn_wme_update(struct ieee80211com *ic) 2251 { 2252 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2253 2254 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2255 2256 /* don't override default WME values if WME is not actually enabled */ 2257 if (!(ic->ic_flags & IEEE80211_F_WME)) 2258 return 0; 2259 2260 /* Do it in a process context. */ 2261 urtwn_do_async(sc, urtwn_wme_update_cb, NULL, 0); 2262 return 0; 2263 } 2264 2265 static void 2266 urtwn_wme_update_cb(struct urtwn_softc *sc, void *arg) 2267 { 2268 static const uint16_t ac2reg[WME_NUM_AC] = { 2269 R92C_EDCA_BE_PARAM, 2270 R92C_EDCA_BK_PARAM, 2271 R92C_EDCA_VI_PARAM, 2272 R92C_EDCA_VO_PARAM 2273 }; 2274 struct ieee80211com *ic = &sc->sc_ic; 2275 const struct wmeParams *wmep; 2276 int ac, aifs, slottime; 2277 int s; 2278 2279 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2280 DPRINTFN(DBG_STM, "called", 0, 0, 0, 0); 2281 2282 s = splnet(); 2283 mutex_enter(&sc->sc_write_mtx); 2284 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2285 for (ac = 0; ac < WME_NUM_AC; ac++) { 2286 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2287 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 2288 aifs = wmep->wmep_aifsn * slottime + 10; 2289 urtwn_write_4(sc, ac2reg[ac], 2290 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 2291 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 2292 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 2293 SM(R92C_EDCA_PARAM_AIFS, aifs)); 2294 } 2295 mutex_exit(&sc->sc_write_mtx); 2296 splx(s); 2297 } 2298 2299 static void 2300 urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 2301 { 2302 int pwdb; 2303 2304 URTWNHIST_FUNC(); 2305 URTWNHIST_CALLARGS("rate=%jd, rsst=%jd", rate, rssi, 0, 0); 2306 2307 /* Convert antenna signal to percentage. */ 2308 if (rssi <= -100 || rssi >= 20) 2309 pwdb = 0; 2310 else if (rssi >= 0) 2311 pwdb = 100; 2312 else 2313 pwdb = 100 + rssi; 2314 if (!ISSET(sc->chip, URTWN_CHIP_88E)) { 2315 if (rate <= 3) { 2316 /* CCK gain is smaller than OFDM/MCS gain. */ 2317 pwdb += 6; 2318 if (pwdb > 100) 2319 pwdb = 100; 2320 if (pwdb <= 14) 2321 pwdb -= 4; 2322 else if (pwdb <= 26) 2323 pwdb -= 8; 2324 else if (pwdb <= 34) 2325 pwdb -= 6; 2326 else if (pwdb <= 42) 2327 pwdb -= 2; 2328 } 2329 } 2330 if (sc->avg_pwdb == -1) /* Init. */ 2331 sc->avg_pwdb = pwdb; 2332 else if (sc->avg_pwdb < pwdb) 2333 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 2334 else 2335 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 2336 2337 DPRINTFN(DBG_RF, "rate=%jd rssi=%jd PWDB=%jd EMA=%jd", 2338 rate, rssi, pwdb, sc->avg_pwdb); 2339 } 2340 2341 static int8_t 2342 urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2343 { 2344 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 2345 struct r92c_rx_phystat *phy; 2346 struct r92c_rx_cck *cck; 2347 uint8_t rpt; 2348 int8_t rssi; 2349 2350 URTWNHIST_FUNC(); 2351 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2352 2353 if (rate <= 3) { 2354 cck = (struct r92c_rx_cck *)physt; 2355 if (ISSET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR)) { 2356 rpt = (cck->agc_rpt >> 5) & 0x3; 2357 rssi = (cck->agc_rpt & 0x1f) << 1; 2358 } else { 2359 rpt = (cck->agc_rpt >> 6) & 0x3; 2360 rssi = cck->agc_rpt & 0x3e; 2361 } 2362 rssi = cckoff[rpt] - rssi; 2363 } else { /* OFDM/HT. */ 2364 phy = (struct r92c_rx_phystat *)physt; 2365 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2366 } 2367 return rssi; 2368 } 2369 2370 static int8_t 2371 urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 2372 { 2373 struct r92c_rx_phystat *phy; 2374 struct r88e_rx_cck *cck; 2375 uint8_t cck_agc_rpt, lna_idx, vga_idx; 2376 int8_t rssi; 2377 2378 URTWNHIST_FUNC(); 2379 URTWNHIST_CALLARGS("rate=%jd", rate, 0, 0, 0); 2380 2381 rssi = 0; 2382 if (rate <= 3) { 2383 cck = (struct r88e_rx_cck *)physt; 2384 cck_agc_rpt = cck->agc_rpt; 2385 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 2386 vga_idx = cck_agc_rpt & 0x1f; 2387 switch (lna_idx) { 2388 case 7: 2389 if (vga_idx <= 27) 2390 rssi = -100 + 2* (27 - vga_idx); 2391 else 2392 rssi = -100; 2393 break; 2394 case 6: 2395 rssi = -48 + 2 * (2 - vga_idx); 2396 break; 2397 case 5: 2398 rssi = -42 + 2 * (7 - vga_idx); 2399 break; 2400 case 4: 2401 rssi = -36 + 2 * (7 - vga_idx); 2402 break; 2403 case 3: 2404 rssi = -24 + 2 * (7 - vga_idx); 2405 break; 2406 case 2: 2407 rssi = -12 + 2 * (5 - vga_idx); 2408 break; 2409 case 1: 2410 rssi = 8 - (2 * vga_idx); 2411 break; 2412 case 0: 2413 rssi = 14 - (2 * vga_idx); 2414 break; 2415 } 2416 rssi += 6; 2417 } else { /* OFDM/HT. */ 2418 phy = (struct r92c_rx_phystat *)physt; 2419 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 2420 } 2421 return rssi; 2422 } 2423 2424 static void 2425 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 2426 { 2427 struct ieee80211com *ic = &sc->sc_ic; 2428 struct ifnet *ifp = ic->ic_ifp; 2429 struct ieee80211_frame *wh; 2430 struct ieee80211_node *ni; 2431 struct r92c_rx_desc_usb *stat; 2432 uint32_t rxdw0, rxdw3; 2433 struct mbuf *m; 2434 uint8_t rate; 2435 int8_t rssi = 0; 2436 int s, infosz; 2437 2438 URTWNHIST_FUNC(); 2439 URTWNHIST_CALLARGS("buf=%jp, pktlen=%#jd", (uintptr_t)buf, pktlen, 0, 0); 2440 2441 stat = (struct r92c_rx_desc_usb *)buf; 2442 rxdw0 = le32toh(stat->rxdw0); 2443 rxdw3 = le32toh(stat->rxdw3); 2444 2445 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 2446 /* 2447 * This should not happen since we setup our Rx filter 2448 * to not receive these frames. 2449 */ 2450 DPRINTFN(DBG_RX, "CRC error", 0, 0, 0, 0); 2451 if_statinc(ifp, if_ierrors); 2452 return; 2453 } 2454 /* 2455 * XXX: This will drop most control packets. Do we really 2456 * want this in IEEE80211_M_MONITOR mode? 2457 */ 2458 // if (__predict_false(pktlen < (int)sizeof(*wh))) { 2459 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 2460 DPRINTFN(DBG_RX, "packet too short %jd", pktlen, 0, 0, 0); 2461 ic->ic_stats.is_rx_tooshort++; 2462 if_statinc(ifp, if_ierrors); 2463 return; 2464 } 2465 if (__predict_false(pktlen > MCLBYTES)) { 2466 DPRINTFN(DBG_RX, "packet too big %jd", pktlen, 0, 0, 0); 2467 if_statinc(ifp, if_ierrors); 2468 return; 2469 } 2470 2471 rate = MS(rxdw3, R92C_RXDW3_RATE); 2472 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2473 2474 /* Get RSSI from PHY status descriptor if present. */ 2475 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 2476 if (!ISSET(sc->chip, URTWN_CHIP_92C)) 2477 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 2478 else 2479 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 2480 /* Update our average RSSI. */ 2481 urtwn_update_avgrssi(sc, rate, rssi); 2482 } 2483 2484 DPRINTFN(DBG_RX, "Rx frame len=%jd rate=%jd infosz=%jd rssi=%jd", 2485 pktlen, rate, infosz, rssi); 2486 2487 MGETHDR(m, M_DONTWAIT, MT_DATA); 2488 if (__predict_false(m == NULL)) { 2489 aprint_error_dev(sc->sc_dev, "couldn't allocate rx mbuf\n"); 2490 ic->ic_stats.is_rx_nobuf++; 2491 if_statinc(ifp, if_ierrors); 2492 return; 2493 } 2494 MCLAIM(m, &sc->sc_ec.ec_rx_mowner); 2495 if (pktlen > (int)MHLEN) { 2496 MCLGET(m, M_DONTWAIT); 2497 if (__predict_false(!(m->m_flags & M_EXT))) { 2498 aprint_error_dev(sc->sc_dev, 2499 "couldn't allocate rx mbuf cluster\n"); 2500 m_freem(m); 2501 ic->ic_stats.is_rx_nobuf++; 2502 if_statinc(ifp, if_ierrors); 2503 return; 2504 } 2505 } 2506 2507 /* Finalize mbuf. */ 2508 m_set_rcvif(m, ifp); 2509 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 2510 memcpy(mtod(m, uint8_t *), wh, pktlen); 2511 m->m_pkthdr.len = m->m_len = pktlen; 2512 2513 s = splnet(); 2514 if (__predict_false(sc->sc_drvbpf != NULL)) { 2515 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2516 2517 tap->wr_flags = 0; 2518 if (!(rxdw3 & R92C_RXDW3_HT)) { 2519 switch (rate) { 2520 /* CCK. */ 2521 case 0: tap->wr_rate = 2; break; 2522 case 1: tap->wr_rate = 4; break; 2523 case 2: tap->wr_rate = 11; break; 2524 case 3: tap->wr_rate = 22; break; 2525 /* OFDM. */ 2526 case 4: tap->wr_rate = 12; break; 2527 case 5: tap->wr_rate = 18; break; 2528 case 6: tap->wr_rate = 24; break; 2529 case 7: tap->wr_rate = 36; break; 2530 case 8: tap->wr_rate = 48; break; 2531 case 9: tap->wr_rate = 72; break; 2532 case 10: tap->wr_rate = 96; break; 2533 case 11: tap->wr_rate = 108; break; 2534 } 2535 } else if (rate >= 12) { /* MCS0~15. */ 2536 /* Bit 7 set means HT MCS instead of rate. */ 2537 tap->wr_rate = 0x80 | (rate - 12); 2538 } 2539 tap->wr_dbm_antsignal = rssi; 2540 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2541 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2542 2543 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2544 } 2545 2546 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2547 2548 /* push the frame up to the 802.11 stack */ 2549 ieee80211_input(ic, m, ni, rssi, 0); 2550 2551 /* Node is no longer needed. */ 2552 ieee80211_free_node(ni); 2553 2554 splx(s); 2555 } 2556 2557 static void 2558 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2559 { 2560 struct urtwn_rx_data *data = priv; 2561 struct urtwn_softc *sc = data->sc; 2562 struct r92c_rx_desc_usb *stat; 2563 size_t pidx = data->pidx; 2564 uint32_t rxdw0; 2565 uint8_t *buf; 2566 int len, totlen, pktlen, infosz, npkts, pktspacing; 2567 2568 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2569 DPRINTFN(DBG_RX, "status=%jd", status, 0, 0, 0); 2570 2571 mutex_enter(&sc->sc_rx_mtx); 2572 TAILQ_REMOVE(&sc->rx_free_list[pidx], data, next); 2573 TAILQ_INSERT_TAIL(&sc->rx_free_list[pidx], data, next); 2574 /* Put this Rx buffer back to our free list. */ 2575 mutex_exit(&sc->sc_rx_mtx); 2576 2577 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2578 if (status == USBD_STALLED) 2579 usbd_clear_endpoint_stall_async(sc->rx_pipe[pidx]); 2580 else if (status != USBD_CANCELLED) 2581 goto resubmit; 2582 return; 2583 } 2584 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 2585 2586 if (__predict_false(len < (int)sizeof(*stat))) { 2587 DPRINTFN(DBG_RX, "xfer too short %jd", len, 0, 0, 0); 2588 goto resubmit; 2589 } 2590 buf = data->buf; 2591 2592 /* Get the number of encapsulated frames. */ 2593 stat = (struct r92c_rx_desc_usb *)buf; 2594 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2595 npkts = MS(le32toh(stat->rxdw2), R92E_RXDW2_PKTCNT); 2596 else 2597 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 2598 DPRINTFN(DBG_RX, "Rx %jd frames in one chunk", npkts, 0, 0, 0); 2599 2600 if (npkts != 0) 2601 rnd_add_uint32(&sc->rnd_source, npkts); 2602 2603 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2604 pktspacing = 8; 2605 else 2606 pktspacing = 128; 2607 2608 /* Process all of them. */ 2609 while (npkts-- > 0 && len > 0) { 2610 if (__predict_false(len < (int)sizeof(*stat))) { 2611 DPRINTFN(DBG_RX, "len(%jd) is short than header", 2612 len, 0, 0, 0); 2613 break; 2614 } 2615 stat = (struct r92c_rx_desc_usb *)buf; 2616 rxdw0 = le32toh(stat->rxdw0); 2617 2618 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 2619 if (__predict_false(pktlen == 0)) { 2620 DPRINTFN(DBG_RX, "pktlen is 0 byte", 0, 0, 0, 0); 2621 break; 2622 } 2623 2624 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 2625 2626 /* Make sure everything fits in xfer. */ 2627 totlen = sizeof(*stat) + infosz + pktlen; 2628 if (__predict_false(totlen > len)) { 2629 DPRINTFN(DBG_RX, "pktlen (%jd+%jd+%jd) > %jd", 2630 (int)sizeof(*stat), infosz, pktlen, len); 2631 break; 2632 } 2633 2634 /* Process 802.11 frame. */ 2635 urtwn_rx_frame(sc, buf, pktlen); 2636 2637 totlen = roundup2(totlen, pktspacing); 2638 buf += totlen; 2639 len -= totlen; 2640 } 2641 2642 resubmit: 2643 /* Setup a new transfer. */ 2644 usbd_setup_xfer(xfer, data, data->buf, URTWN_RXBUFSZ, 2645 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtwn_rxeof); 2646 (void)usbd_transfer(xfer); 2647 } 2648 2649 static void 2650 urtwn_put_tx_data(struct urtwn_softc *sc, struct urtwn_tx_data *data) 2651 { 2652 size_t pidx = data->pidx; 2653 2654 mutex_enter(&sc->sc_tx_mtx); 2655 /* Put this Tx buffer back to our free list. */ 2656 TAILQ_INSERT_TAIL(&sc->tx_free_list[pidx], data, next); 2657 mutex_exit(&sc->sc_tx_mtx); 2658 } 2659 2660 static void 2661 urtwn_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2662 { 2663 struct urtwn_tx_data *data = priv; 2664 struct urtwn_softc *sc = data->sc; 2665 struct ifnet *ifp = &sc->sc_if; 2666 size_t pidx = data->pidx; 2667 int s; 2668 2669 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2670 DPRINTFN(DBG_TX, "status=%jd", status, 0, 0, 0); 2671 2672 urtwn_put_tx_data(sc, data); 2673 2674 s = splnet(); 2675 sc->tx_timer = 0; 2676 ifp->if_flags &= ~IFF_OACTIVE; 2677 2678 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2679 if (status != USBD_NOT_STARTED && status != USBD_CANCELLED) { 2680 if (status == USBD_STALLED) { 2681 struct usbd_pipe *pipe = sc->tx_pipe[pidx]; 2682 usbd_clear_endpoint_stall_async(pipe); 2683 } 2684 device_printf(sc->sc_dev, "transmit failed, %s\n", 2685 usbd_errstr(status)); 2686 if_statinc(ifp, if_oerrors); 2687 } 2688 splx(s); 2689 return; 2690 } 2691 2692 if_statinc(ifp, if_opackets); 2693 urtwn_start(ifp); 2694 splx(s); 2695 2696 } 2697 2698 static int 2699 urtwn_tx(struct urtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni, 2700 struct urtwn_tx_data *data) 2701 { 2702 struct ieee80211com *ic = &sc->sc_ic; 2703 struct ieee80211_frame *wh; 2704 struct ieee80211_key *k = NULL; 2705 struct r92c_tx_desc_usb *txd; 2706 size_t i, padsize, xferlen, txd_len; 2707 uint16_t seq, sum; 2708 uint8_t raid, type, tid; 2709 int s, hasqos, error; 2710 2711 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2712 2713 wh = mtod(m, struct ieee80211_frame *); 2714 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2715 txd_len = sizeof(*txd); 2716 2717 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 2718 txd_len = 32; 2719 2720 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2721 k = ieee80211_crypto_encap(ic, ni, m); 2722 if (k == NULL) { 2723 urtwn_put_tx_data(sc, data); 2724 m_free(m); 2725 return ENOBUFS; 2726 } 2727 2728 /* packet header may have moved, reset our local pointer */ 2729 wh = mtod(m, struct ieee80211_frame *); 2730 } 2731 2732 if (__predict_false(sc->sc_drvbpf != NULL)) { 2733 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2734 2735 tap->wt_flags = 0; 2736 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2737 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2738 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2739 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2740 2741 /* XXX: set tap->wt_rate? */ 2742 2743 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2744 } 2745 2746 /* non-qos data frames */ 2747 tid = R92C_TXDW1_QSEL_BE; 2748 if ((hasqos = ieee80211_has_qos(wh))) { 2749 /* data frames in 11n mode */ 2750 struct ieee80211_qosframe *qwh = (void *)wh; 2751 tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2752 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2753 tid = R92C_TXDW1_QSEL_MGNT; 2754 } 2755 2756 if (((txd_len + m->m_pkthdr.len) % 64) == 0) /* XXX: 64 */ 2757 padsize = 8; 2758 else 2759 padsize = 0; 2760 2761 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2762 padsize = 0; 2763 2764 /* Fill Tx descriptor. */ 2765 txd = (struct r92c_tx_desc_usb *)data->buf; 2766 memset(txd, 0, txd_len + padsize); 2767 2768 txd->txdw0 |= htole32( 2769 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 2770 SM(R92C_TXDW0_OFFSET, txd_len)); 2771 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2772 txd->txdw0 |= htole32( 2773 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 2774 } 2775 2776 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2777 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 2778 2779 /* fix pad field */ 2780 if (padsize > 0) { 2781 DPRINTFN(DBG_TX, "padding: size=%jd", padsize, 0, 0, 0); 2782 txd->txdw1 |= htole32(SM(R92C_TXDW1_PKTOFF, (padsize / 8))); 2783 } 2784 2785 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2786 type == IEEE80211_FC0_TYPE_DATA) { 2787 if (ic->ic_curmode == IEEE80211_MODE_11B) 2788 raid = R92C_RAID_11B; 2789 else 2790 raid = R92C_RAID_11BG; 2791 DPRINTFN(DBG_TX, "data packet: tid=%jd, raid=%jd", 2792 tid, raid, 0, 0); 2793 2794 if (!ISSET(sc->chip, URTWN_CHIP_92C)) { 2795 txd->txdw1 |= htole32( 2796 SM(R88E_TXDW1_MACID, RTWN_MACID_BSS) | 2797 SM(R92C_TXDW1_QSEL, tid) | 2798 SM(R92C_TXDW1_RAID, raid) | 2799 R92C_TXDW1_AGGBK); 2800 } else 2801 txd->txdw1 |= htole32( 2802 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2803 SM(R92C_TXDW1_QSEL, tid) | 2804 SM(R92C_TXDW1_RAID, raid) | 2805 R92C_TXDW1_AGGBK); 2806 2807 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2808 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 2809 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 2810 txd->txdw3 |= htole32(R92E_TXDW3_AGGBK); 2811 2812 if (hasqos) { 2813 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 2814 } 2815 2816 if (ic->ic_flags & IEEE80211_F_USEPROT) { 2817 /* for 11g */ 2818 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 2819 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 2820 R92C_TXDW4_HWRTSEN); 2821 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 2822 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 2823 R92C_TXDW4_HWRTSEN); 2824 } 2825 } 2826 /* Send RTS at OFDM24. */ 2827 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 2828 txd->txdw5 |= htole32(0x0001ff00); 2829 /* Send data at OFDM54. */ 2830 if (ISSET(sc->chip, URTWN_CHIP_88E)) 2831 txd->txdw5 |= htole32(0x13 & 0x3f); 2832 else 2833 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 2834 } else if (type == IEEE80211_FC0_TYPE_MGT) { 2835 DPRINTFN(DBG_TX, "mgmt packet", 0, 0, 0, 0); 2836 txd->txdw1 |= htole32( 2837 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 2838 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 2839 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2840 2841 /* Force CCK1. */ 2842 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2843 /* Use 1Mbps */ 2844 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2845 } else { 2846 /* broadcast or multicast packets */ 2847 DPRINTFN(DBG_TX, "bc or mc packet", 0, 0, 0, 0); 2848 txd->txdw1 |= htole32( 2849 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 2850 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 2851 2852 /* Force CCK1. */ 2853 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 2854 /* Use 1Mbps */ 2855 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 2856 } 2857 /* Set sequence number */ 2858 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 2859 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) { 2860 txd->txdseq |= htole16(seq); 2861 2862 if (!hasqos) { 2863 /* Use HW sequence numbering for non-QoS frames. */ 2864 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2865 txd->txdseq |= htole16(R92C_HWSEQ_EN); 2866 } 2867 } else { 2868 txd->txdseq2 |= htole16((seq & R92E_HWSEQ_MASK) << 2869 R92E_HWSEQ_SHIFT); 2870 if (!hasqos) { 2871 /* Use HW sequence numbering for non-QoS frames. */ 2872 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 2873 txd->txdw7 |= htole16(R92C_HWSEQ_EN); 2874 } 2875 } 2876 2877 /* Compute Tx descriptor checksum. */ 2878 sum = 0; 2879 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 2880 sum ^= ((uint16_t *)txd)[i]; 2881 txd->txdsum = sum; /* NB: already little endian. */ 2882 2883 xferlen = txd_len + m->m_pkthdr.len + padsize; 2884 m_copydata(m, 0, m->m_pkthdr.len, (char *)&txd[0] + txd_len + padsize); 2885 2886 s = splnet(); 2887 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2888 USBD_FORCE_SHORT_XFER, URTWN_TX_TIMEOUT, 2889 urtwn_txeof); 2890 error = usbd_transfer(data->xfer); 2891 if (__predict_false(error != USBD_NORMAL_COMPLETION && 2892 error != USBD_IN_PROGRESS)) { 2893 splx(s); 2894 DPRINTFN(DBG_TX, "transfer failed %jd", error, 0, 0, 0); 2895 return error; 2896 } 2897 splx(s); 2898 return 0; 2899 } 2900 2901 struct urtwn_tx_data * 2902 urtwn_get_tx_data(struct urtwn_softc *sc, size_t pidx) 2903 { 2904 struct urtwn_tx_data *data = NULL; 2905 2906 mutex_enter(&sc->sc_tx_mtx); 2907 if (!TAILQ_EMPTY(&sc->tx_free_list[pidx])) { 2908 data = TAILQ_FIRST(&sc->tx_free_list[pidx]); 2909 TAILQ_REMOVE(&sc->tx_free_list[pidx], data, next); 2910 } 2911 mutex_exit(&sc->sc_tx_mtx); 2912 2913 return data; 2914 } 2915 2916 static void 2917 urtwn_start(struct ifnet *ifp) 2918 { 2919 struct urtwn_softc *sc = ifp->if_softc; 2920 struct ieee80211com *ic = &sc->sc_ic; 2921 struct urtwn_tx_data *data; 2922 struct ether_header *eh; 2923 struct ieee80211_node *ni; 2924 struct mbuf *m; 2925 2926 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 2927 2928 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2929 return; 2930 2931 data = NULL; 2932 for (;;) { 2933 /* Send pending management frames first. */ 2934 IF_POLL(&ic->ic_mgtq, m); 2935 if (m != NULL) { 2936 /* Use AC_VO for management frames. */ 2937 2938 data = urtwn_get_tx_data(sc, sc->ac2idx[WME_AC_VO]); 2939 2940 if (data == NULL) { 2941 ifp->if_flags |= IFF_OACTIVE; 2942 DPRINTFN(DBG_TX, "empty tx_free_list", 2943 0, 0, 0, 0); 2944 return; 2945 } 2946 IF_DEQUEUE(&ic->ic_mgtq, m); 2947 ni = M_GETCTX(m, struct ieee80211_node *); 2948 M_CLEARCTX(m); 2949 goto sendit; 2950 } 2951 if (ic->ic_state != IEEE80211_S_RUN) 2952 break; 2953 2954 /* Encapsulate and send data frames. */ 2955 IFQ_POLL(&ifp->if_snd, m); 2956 if (m == NULL) 2957 break; 2958 2959 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2960 uint8_t type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2961 uint8_t qid = WME_AC_BE; 2962 if (ieee80211_has_qos(wh)) { 2963 /* data frames in 11n mode */ 2964 struct ieee80211_qosframe *qwh = (void *)wh; 2965 uint8_t tid = qwh->i_qos[0] & IEEE80211_QOS_TID; 2966 qid = TID_TO_WME_AC(tid); 2967 } else if (type != IEEE80211_FC0_TYPE_DATA) { 2968 qid = WME_AC_VO; 2969 } 2970 data = urtwn_get_tx_data(sc, sc->ac2idx[qid]); 2971 2972 if (data == NULL) { 2973 ifp->if_flags |= IFF_OACTIVE; 2974 DPRINTFN(DBG_TX, "empty tx_free_list", 0, 0, 0, 0); 2975 return; 2976 } 2977 IFQ_DEQUEUE(&ifp->if_snd, m); 2978 2979 if (m->m_len < (int)sizeof(*eh) && 2980 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2981 device_printf(sc->sc_dev, "m_pullup failed\n"); 2982 if_statinc(ifp, if_oerrors); 2983 urtwn_put_tx_data(sc, data); 2984 m_freem(m); 2985 continue; 2986 } 2987 eh = mtod(m, struct ether_header *); 2988 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2989 if (ni == NULL) { 2990 device_printf(sc->sc_dev, 2991 "unable to find transmit node\n"); 2992 if_statinc(ifp, if_oerrors); 2993 urtwn_put_tx_data(sc, data); 2994 m_freem(m); 2995 continue; 2996 } 2997 2998 bpf_mtap(ifp, m, BPF_D_OUT); 2999 3000 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 3001 ieee80211_free_node(ni); 3002 device_printf(sc->sc_dev, 3003 "unable to encapsulate packet\n"); 3004 if_statinc(ifp, if_oerrors); 3005 urtwn_put_tx_data(sc, data); 3006 m_freem(m); 3007 continue; 3008 } 3009 sendit: 3010 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 3011 3012 if (urtwn_tx(sc, m, ni, data) != 0) { 3013 m_freem(m); 3014 ieee80211_free_node(ni); 3015 device_printf(sc->sc_dev, 3016 "unable to transmit packet\n"); 3017 if_statinc(ifp, if_oerrors); 3018 urtwn_put_tx_data(sc, data); 3019 continue; 3020 } 3021 m_freem(m); 3022 ieee80211_free_node(ni); 3023 sc->tx_timer = 5; 3024 ifp->if_timer = 1; 3025 } 3026 } 3027 3028 static void 3029 urtwn_watchdog(struct ifnet *ifp) 3030 { 3031 struct urtwn_softc *sc = ifp->if_softc; 3032 3033 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3034 3035 ifp->if_timer = 0; 3036 3037 if (sc->tx_timer > 0) { 3038 if (--sc->tx_timer == 0) { 3039 device_printf(sc->sc_dev, "device timeout\n"); 3040 /* urtwn_init(ifp); XXX needs a process context! */ 3041 if_statinc(ifp, if_oerrors); 3042 return; 3043 } 3044 ifp->if_timer = 1; 3045 } 3046 ieee80211_watchdog(&sc->sc_ic); 3047 } 3048 3049 static int 3050 urtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 3051 { 3052 struct urtwn_softc *sc = ifp->if_softc; 3053 struct ieee80211com *ic = &sc->sc_ic; 3054 int s, error = 0; 3055 3056 URTWNHIST_FUNC(); 3057 URTWNHIST_CALLARGS("cmd=0x%08jx, data=%#jx", cmd, (uintptr_t)data, 3058 0, 0); 3059 3060 s = splnet(); 3061 3062 switch (cmd) { 3063 case SIOCSIFFLAGS: 3064 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 3065 break; 3066 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 3067 case IFF_UP | IFF_RUNNING: 3068 break; 3069 case IFF_UP: 3070 urtwn_init(ifp); 3071 break; 3072 case IFF_RUNNING: 3073 urtwn_stop(ifp, 1); 3074 break; 3075 case 0: 3076 break; 3077 } 3078 break; 3079 3080 case SIOCADDMULTI: 3081 case SIOCDELMULTI: 3082 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 3083 /* setup multicast filter, etc */ 3084 error = 0; 3085 } 3086 break; 3087 3088 case SIOCS80211CHANNEL: 3089 /* 3090 * This allows for fast channel switching in monitor mode 3091 * (used by kismet). In IBSS mode, we must explicitly reset 3092 * the interface to generate a new beacon frame. 3093 */ 3094 error = ieee80211_ioctl(ic, cmd, data); 3095 if (error == ENETRESET && 3096 ic->ic_opmode == IEEE80211_M_MONITOR) { 3097 urtwn_set_chan(sc, ic->ic_curchan, 3098 IEEE80211_HTINFO_2NDCHAN_NONE); 3099 error = 0; 3100 } 3101 break; 3102 3103 default: 3104 error = ieee80211_ioctl(ic, cmd, data); 3105 break; 3106 } 3107 if (error == ENETRESET) { 3108 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3109 (IFF_UP | IFF_RUNNING) && 3110 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) { 3111 urtwn_init(ifp); 3112 } 3113 error = 0; 3114 } 3115 3116 splx(s); 3117 3118 return error; 3119 } 3120 3121 static __inline int 3122 urtwn_power_on(struct urtwn_softc *sc) 3123 { 3124 3125 return sc->sc_power_on(sc); 3126 } 3127 3128 static int 3129 urtwn_r92c_power_on(struct urtwn_softc *sc) 3130 { 3131 uint32_t reg; 3132 int ntries; 3133 3134 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3135 3136 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3137 3138 /* Wait for autoload done bit. */ 3139 for (ntries = 0; ntries < 1000; ntries++) { 3140 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 3141 break; 3142 DELAY(5); 3143 } 3144 if (ntries == 1000) { 3145 aprint_error_dev(sc->sc_dev, 3146 "timeout waiting for chip autoload\n"); 3147 return ETIMEDOUT; 3148 } 3149 3150 /* Unlock ISO/CLK/Power control register. */ 3151 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 3152 DELAY(5); 3153 /* Move SPS into PWM mode. */ 3154 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 3155 DELAY(5); 3156 3157 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 3158 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 3159 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 3160 reg | R92C_LDOV12D_CTRL_LDV12_EN); 3161 DELAY(100); 3162 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 3163 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 3164 ~R92C_SYS_ISO_CTRL_MD2PP); 3165 } 3166 3167 /* Auto enable WLAN. */ 3168 urtwn_write_2(sc, R92C_APS_FSMCO, 3169 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3170 for (ntries = 0; ntries < 1000; ntries++) { 3171 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 3172 R92C_APS_FSMCO_APFM_ONMAC)) 3173 break; 3174 DELAY(100); 3175 } 3176 if (ntries == 1000) { 3177 aprint_error_dev(sc->sc_dev, 3178 "timeout waiting for MAC auto ON\n"); 3179 return ETIMEDOUT; 3180 } 3181 3182 /* Enable radio, GPIO and LED functions. */ 3183 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3184 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3185 urtwn_write_2(sc, R92C_APS_FSMCO, 3186 R92C_APS_FSMCO_AFSM_HSUS | 3187 R92C_APS_FSMCO_PDN_EN | 3188 R92C_APS_FSMCO_PFM_ALDN); 3189 3190 /* Release RF digital isolation. */ 3191 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 3192 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 3193 3194 /* Initialize MAC. */ 3195 urtwn_write_1(sc, R92C_APSD_CTRL, 3196 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 3197 for (ntries = 0; ntries < 200; ntries++) { 3198 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 3199 R92C_APSD_CTRL_OFF_STATUS)) 3200 break; 3201 DELAY(5); 3202 } 3203 if (ntries == 200) { 3204 aprint_error_dev(sc->sc_dev, 3205 "timeout waiting for MAC initialization\n"); 3206 return ETIMEDOUT; 3207 } 3208 3209 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3210 reg = urtwn_read_2(sc, R92C_CR); 3211 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3212 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3213 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3214 R92C_CR_ENSEC; 3215 urtwn_write_2(sc, R92C_CR, reg); 3216 3217 urtwn_write_1(sc, 0xfe10, 0x19); 3218 3219 urtwn_delay_ms(sc, 1); 3220 3221 return 0; 3222 } 3223 3224 static int 3225 urtwn_r92e_power_on(struct urtwn_softc *sc) 3226 { 3227 uint32_t reg; 3228 uint32_t val; 3229 int ntries; 3230 3231 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3232 3233 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3234 3235 /* Enable radio, GPIO and LED functions. */ 3236 KASSERT((R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_PDN_EN | 3237 R92C_APS_FSMCO_PFM_ALDN) == 0x0812); 3238 urtwn_write_2(sc, R92C_APS_FSMCO, 3239 R92C_APS_FSMCO_AFSM_HSUS | 3240 R92C_APS_FSMCO_PDN_EN | 3241 R92C_APS_FSMCO_PFM_ALDN); 3242 3243 if (urtwn_read_4(sc, R92E_SYS_CFG1_8192E) & R92E_SPSLDO_SEL){ 3244 /* LDO. */ 3245 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 3246 } 3247 else { 3248 urtwn_write_2(sc, R92C_SYS_SWR_CTRL2, urtwn_read_2(sc, 3249 R92C_SYS_SWR_CTRL2) & 0xffff); 3250 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 3251 } 3252 3253 for (ntries = 0; ntries < 2; ntries++) { 3254 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 3255 urtwn_read_1(sc, R92C_AFE_PLL_CTRL)); 3256 urtwn_write_2(sc, R92C_AFE_CTRL4, urtwn_read_2(sc, 3257 R92C_AFE_CTRL4)); 3258 } 3259 3260 /* Reset BB. */ 3261 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3262 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3263 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3264 3265 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, urtwn_read_1(sc, 3266 R92C_AFE_XTAL_CTRL + 2) | 0x80); 3267 3268 /* Disable HWPDN. */ 3269 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3270 R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 3271 3272 /* Disable WL suspend. */ 3273 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3274 R92C_APS_FSMCO) & ~(R92C_APS_FSMCO_AFSM_PCIE | 3275 R92C_APS_FSMCO_AFSM_HSUS)); 3276 3277 urtwn_write_4(sc, R92C_APS_FSMCO, urtwn_read_4(sc, 3278 R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 3279 urtwn_write_2(sc, R92C_APS_FSMCO, urtwn_read_2(sc, 3280 R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 3281 for (ntries = 0; ntries < 10000; ntries++) { 3282 val = urtwn_read_2(sc, R92C_APS_FSMCO) & 3283 R92C_APS_FSMCO_APFM_ONMAC; 3284 if (val == 0x0) 3285 break; 3286 DELAY(10); 3287 } 3288 if (ntries == 10000) { 3289 aprint_error_dev(sc->sc_dev, 3290 "timeout waiting for chip power up\n"); 3291 return ETIMEDOUT; 3292 } 3293 3294 urtwn_write_2(sc, R92C_CR, 0x00); 3295 reg = urtwn_read_2(sc, R92C_CR); 3296 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3297 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3298 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC; 3299 urtwn_write_2(sc, R92C_CR, reg); 3300 3301 return 0; 3302 } 3303 3304 static int 3305 urtwn_r88e_power_on(struct urtwn_softc *sc) 3306 { 3307 uint32_t reg; 3308 uint8_t val; 3309 int ntries; 3310 3311 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3312 3313 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3314 3315 /* Wait for power ready bit. */ 3316 for (ntries = 0; ntries < 5000; ntries++) { 3317 val = urtwn_read_1(sc, 0x6) & 0x2; 3318 if (val == 0x2) 3319 break; 3320 DELAY(10); 3321 } 3322 if (ntries == 5000) { 3323 aprint_error_dev(sc->sc_dev, 3324 "timeout waiting for chip power up\n"); 3325 return ETIMEDOUT; 3326 } 3327 3328 /* Reset BB. */ 3329 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3330 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 3331 R92C_SYS_FUNC_EN_BB_GLB_RST)); 3332 3333 urtwn_write_1(sc, 0x26, urtwn_read_1(sc, 0x26) | 0x80); 3334 3335 /* Disable HWPDN. */ 3336 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 3337 3338 /* Disable WL suspend. */ 3339 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x18); 3340 3341 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) | 0x1); 3342 for (ntries = 0; ntries < 5000; ntries++) { 3343 if (!(urtwn_read_1(sc, 0x5) & 0x1)) 3344 break; 3345 DELAY(10); 3346 } 3347 if (ntries == 5000) 3348 return ETIMEDOUT; 3349 3350 /* Enable LDO normal mode. */ 3351 urtwn_write_1(sc, 0x23, urtwn_read_1(sc, 0x23) & ~0x10); 3352 3353 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 3354 urtwn_write_2(sc, R92C_CR, 0); 3355 reg = urtwn_read_2(sc, R92C_CR); 3356 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3357 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3358 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 3359 urtwn_write_2(sc, R92C_CR, reg); 3360 3361 return 0; 3362 } 3363 3364 static int __noinline 3365 urtwn_llt_init(struct urtwn_softc *sc) 3366 { 3367 size_t i, page_count, pktbuf_count; 3368 uint32_t val; 3369 int error; 3370 3371 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3372 3373 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3374 3375 if (sc->chip & URTWN_CHIP_88E) 3376 page_count = R88E_TX_PAGE_COUNT; 3377 else if (sc->chip & URTWN_CHIP_92EU) 3378 page_count = R92E_TX_PAGE_COUNT; 3379 else 3380 page_count = R92C_TX_PAGE_COUNT; 3381 if (sc->chip & URTWN_CHIP_88E) 3382 pktbuf_count = R88E_TXPKTBUF_COUNT; 3383 else if (sc->chip & URTWN_CHIP_92EU) 3384 pktbuf_count = R92E_TXPKTBUF_COUNT; 3385 else 3386 pktbuf_count = R92C_TXPKTBUF_COUNT; 3387 3388 if (sc->chip & URTWN_CHIP_92EU) { 3389 val = urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN; 3390 urtwn_write_4(sc, R92E_AUTO_LLT, val); 3391 DELAY(100); 3392 val = urtwn_read_4(sc, R92E_AUTO_LLT); 3393 if (val & R92E_AUTO_LLT_EN) 3394 return EIO; 3395 return 0; 3396 } 3397 3398 /* Reserve pages [0; page_count]. */ 3399 for (i = 0; i < page_count; i++) { 3400 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3401 return error; 3402 } 3403 /* NB: 0xff indicates end-of-list. */ 3404 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 3405 return error; 3406 /* 3407 * Use pages [page_count + 1; pktbuf_count - 1] 3408 * as ring buffer. 3409 */ 3410 for (++i; i < pktbuf_count - 1; i++) { 3411 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 3412 return error; 3413 } 3414 /* Make the last page point to the beginning of the ring buffer. */ 3415 error = urtwn_llt_write(sc, i, pktbuf_count + 1); 3416 return error; 3417 } 3418 3419 static void 3420 urtwn_fw_reset(struct urtwn_softc *sc) 3421 { 3422 uint16_t reg; 3423 int ntries; 3424 3425 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3426 3427 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3428 3429 /* Tell 8051 to reset itself. */ 3430 mutex_enter(&sc->sc_fwcmd_mtx); 3431 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 3432 sc->fwcur = 0; 3433 mutex_exit(&sc->sc_fwcmd_mtx); 3434 3435 /* Wait until 8051 resets by itself. */ 3436 for (ntries = 0; ntries < 100; ntries++) { 3437 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3438 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 3439 return; 3440 DELAY(50); 3441 } 3442 /* Force 8051 reset. */ 3443 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3444 urtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 3445 } 3446 3447 static void 3448 urtwn_r88e_fw_reset(struct urtwn_softc *sc) 3449 { 3450 uint16_t reg; 3451 3452 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3453 3454 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3455 3456 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3457 reg = urtwn_read_2(sc, R92C_RSV_CTRL) & ~R92E_RSV_MIO_EN; 3458 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3459 } 3460 DELAY(50); 3461 3462 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 3463 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 3464 DELAY(50); 3465 3466 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 3467 DELAY(50); 3468 3469 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3470 reg = urtwn_read_2(sc, R92C_RSV_CTRL) | R92E_RSV_MIO_EN; 3471 urtwn_write_2(sc,R92C_RSV_CTRL, reg); 3472 } 3473 DELAY(50); 3474 3475 mutex_enter(&sc->sc_fwcmd_mtx); 3476 /* Init firmware commands ring. */ 3477 sc->fwcur = 0; 3478 mutex_exit(&sc->sc_fwcmd_mtx); 3479 3480 } 3481 3482 static int 3483 urtwn_fw_loadpage(struct urtwn_softc *sc, int page, uint8_t *buf, int len) 3484 { 3485 uint32_t reg; 3486 int off, mlen, error = 0; 3487 3488 URTWNHIST_FUNC(); 3489 URTWNHIST_CALLARGS("page=%jd, buf=%#jx, len=%jd", 3490 page, (uintptr_t)buf, len, 0); 3491 3492 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3493 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 3494 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3495 3496 off = R92C_FW_START_ADDR; 3497 while (len > 0) { 3498 if (len > 196) 3499 mlen = 196; 3500 else if (len > 4) 3501 mlen = 4; 3502 else 3503 mlen = 1; 3504 error = urtwn_write_region(sc, off, buf, mlen); 3505 if (error != 0) 3506 break; 3507 off += mlen; 3508 buf += mlen; 3509 len -= mlen; 3510 } 3511 return error; 3512 } 3513 3514 static int __noinline 3515 urtwn_load_firmware(struct urtwn_softc *sc) 3516 { 3517 firmware_handle_t fwh; 3518 const struct r92c_fw_hdr *hdr; 3519 const char *name; 3520 u_char *fw, *ptr; 3521 size_t len; 3522 uint32_t reg; 3523 int mlen, ntries, page, error; 3524 3525 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3526 3527 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3528 3529 /* Read firmware image from the filesystem. */ 3530 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3531 name = "rtl8188eufw.bin"; 3532 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3533 name = "rtl8192eefw.bin"; 3534 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 3535 URTWN_CHIP_UMC_A_CUT) 3536 name = "rtl8192cfwU.bin"; 3537 else 3538 name = "rtl8192cfw.bin"; 3539 if ((error = firmware_open("if_urtwn", name, &fwh)) != 0) { 3540 aprint_error_dev(sc->sc_dev, 3541 "failed load firmware of file %s (error %d)\n", name, 3542 error); 3543 return error; 3544 } 3545 const size_t fwlen = len = firmware_get_size(fwh); 3546 fw = firmware_malloc(len); 3547 if (fw == NULL) { 3548 aprint_error_dev(sc->sc_dev, 3549 "failed to allocate firmware memory\n"); 3550 firmware_close(fwh); 3551 return ENOMEM; 3552 } 3553 error = firmware_read(fwh, 0, fw, len); 3554 firmware_close(fwh); 3555 if (error != 0) { 3556 aprint_error_dev(sc->sc_dev, 3557 "failed to read firmware (error %d)\n", error); 3558 firmware_free(fw, fwlen); 3559 return error; 3560 } 3561 3562 len = fwlen; 3563 ptr = fw; 3564 hdr = (const struct r92c_fw_hdr *)ptr; 3565 /* Check if there is a valid FW header and skip it. */ 3566 if ((le16toh(hdr->signature) >> 4) == 0x88c || 3567 (le16toh(hdr->signature) >> 4) == 0x88e || 3568 (le16toh(hdr->signature) >> 4) == 0x92e || 3569 (le16toh(hdr->signature) >> 4) == 0x92c) { 3570 DPRINTFN(DBG_INIT, "FW V%jd.%jd", 3571 le16toh(hdr->version), le16toh(hdr->subversion), 0, 0); 3572 DPRINTFN(DBG_INIT, "%02jd-%02jd %02jd:%02jd", 3573 hdr->month, hdr->date, hdr->hour, hdr->minute); 3574 ptr += sizeof(*hdr); 3575 len -= sizeof(*hdr); 3576 } 3577 3578 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 3579 /* Reset MCU ready status */ 3580 urtwn_write_1(sc, R92C_MCUFWDL, 0); 3581 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3582 ISSET(sc->chip, URTWN_CHIP_92EU)) 3583 urtwn_r88e_fw_reset(sc); 3584 else 3585 urtwn_fw_reset(sc); 3586 } 3587 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3588 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3589 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3590 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3591 R92C_SYS_FUNC_EN_CPUEN); 3592 } 3593 3594 /* download enabled */ 3595 urtwn_write_1(sc, R92C_MCUFWDL, 3596 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 3597 urtwn_write_1(sc, R92C_MCUFWDL + 2, 3598 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 3599 3600 /* Reset the FWDL checksum. */ 3601 urtwn_write_1(sc, R92C_MCUFWDL, 3602 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 3603 3604 DELAY(50); 3605 /* download firmware */ 3606 for (page = 0; len > 0; page++) { 3607 mlen = MIN(len, R92C_FW_PAGE_SIZE); 3608 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 3609 if (error != 0) { 3610 aprint_error_dev(sc->sc_dev, 3611 "could not load firmware page %d\n", page); 3612 goto fail; 3613 } 3614 ptr += mlen; 3615 len -= mlen; 3616 } 3617 3618 /* download disable */ 3619 urtwn_write_1(sc, R92C_MCUFWDL, 3620 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 3621 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 3622 3623 /* Wait for checksum report. */ 3624 for (ntries = 0; ntries < 1000; ntries++) { 3625 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 3626 break; 3627 DELAY(5); 3628 } 3629 if (ntries == 1000) { 3630 aprint_error_dev(sc->sc_dev, 3631 "timeout waiting for checksum report\n"); 3632 error = ETIMEDOUT; 3633 goto fail; 3634 } 3635 3636 /* Wait for firmware readiness. */ 3637 reg = urtwn_read_4(sc, R92C_MCUFWDL); 3638 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 3639 urtwn_write_4(sc, R92C_MCUFWDL, reg); 3640 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3641 ISSET(sc->chip, URTWN_CHIP_92EU)) 3642 urtwn_r88e_fw_reset(sc); 3643 for (ntries = 0; ntries < 6000; ntries++) { 3644 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 3645 break; 3646 DELAY(5); 3647 } 3648 if (ntries == 6000) { 3649 aprint_error_dev(sc->sc_dev, 3650 "timeout waiting for firmware readiness\n"); 3651 error = ETIMEDOUT; 3652 goto fail; 3653 } 3654 fail: 3655 firmware_free(fw, fwlen); 3656 return error; 3657 } 3658 3659 static __inline int 3660 urtwn_dma_init(struct urtwn_softc *sc) 3661 { 3662 3663 return sc->sc_dma_init(sc); 3664 } 3665 3666 static int 3667 urtwn_r92c_dma_init(struct urtwn_softc *sc) 3668 { 3669 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 3670 uint32_t reg; 3671 int error; 3672 3673 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3674 3675 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3676 3677 /* Initialize LLT table. */ 3678 error = urtwn_llt_init(sc); 3679 if (error != 0) 3680 return error; 3681 3682 /* Get Tx queues to USB endpoints mapping. */ 3683 hashq = hasnq = haslq = 0; 3684 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 3685 DPRINTFN(DBG_INIT, "USB endpoints mapping %#jx", reg, 0, 0, 0); 3686 if (MS(reg, R92C_USB_EP_HQ) != 0) 3687 hashq = 1; 3688 if (MS(reg, R92C_USB_EP_NQ) != 0) 3689 hasnq = 1; 3690 if (MS(reg, R92C_USB_EP_LQ) != 0) 3691 haslq = 1; 3692 nqueues = hashq + hasnq + haslq; 3693 if (nqueues == 0) 3694 return EIO; 3695 /* Get the number of pages for each queue. */ 3696 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 3697 /* The remaining pages are assigned to the high priority queue. */ 3698 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 3699 3700 /* Set number of pages for normal priority queue. */ 3701 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 3702 urtwn_write_4(sc, R92C_RQPN, 3703 /* Set number of pages for public queue. */ 3704 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 3705 /* Set number of pages for high priority queue. */ 3706 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 3707 /* Set number of pages for low priority queue. */ 3708 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 3709 /* Load values. */ 3710 R92C_RQPN_LD); 3711 3712 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3713 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 3714 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 3715 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 3716 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 3717 3718 /* Set queue to USB pipe mapping. */ 3719 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3720 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3721 if (nqueues == 1) { 3722 if (hashq) { 3723 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 3724 } else if (hasnq) { 3725 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 3726 } else { 3727 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3728 } 3729 } else if (nqueues == 2) { 3730 /* All 2-endpoints configs have a high priority queue. */ 3731 if (!hashq) { 3732 return EIO; 3733 } 3734 if (hasnq) { 3735 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3736 } else { 3737 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 3738 } 3739 } else { 3740 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3741 } 3742 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3743 3744 /* Set Tx/Rx transfer page boundary. */ 3745 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 3746 3747 /* Set Tx/Rx transfer page size. */ 3748 urtwn_write_1(sc, R92C_PBP, 3749 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3750 return 0; 3751 } 3752 3753 static int 3754 urtwn_r88e_dma_init(struct urtwn_softc *sc) 3755 { 3756 usb_interface_descriptor_t *id; 3757 uint32_t reg; 3758 int nqueues; 3759 int error; 3760 3761 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3762 3763 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3764 3765 /* Initialize LLT table. */ 3766 error = urtwn_llt_init(sc); 3767 if (error != 0) 3768 return error; 3769 3770 /* Get Tx queues to USB endpoints mapping. */ 3771 id = usbd_get_interface_descriptor(sc->sc_iface); 3772 nqueues = id->bNumEndpoints - 1; 3773 if (nqueues == 0) 3774 return EIO; 3775 3776 /* Set number of pages for normal priority queue. */ 3777 urtwn_write_2(sc, R92C_RQPN_NPQ, 0); 3778 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 3779 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 3780 3781 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3782 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 3783 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 3784 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 3785 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 3786 3787 /* Set queue to USB pipe mapping. */ 3788 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 3789 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 3790 if (nqueues == 1) 3791 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 3792 else if (nqueues == 2) 3793 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 3794 else 3795 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 3796 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 3797 3798 /* Set Tx/Rx transfer page boundary. */ 3799 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 3800 3801 /* Set Tx/Rx transfer page size. */ 3802 urtwn_write_1(sc, R92C_PBP, 3803 SM(R92C_PBP_PSRX, R92C_PBP_128) | SM(R92C_PBP_PSTX, R92C_PBP_128)); 3804 3805 return 0; 3806 } 3807 3808 static void __noinline 3809 urtwn_mac_init(struct urtwn_softc *sc) 3810 { 3811 size_t i; 3812 3813 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3814 3815 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3816 3817 /* Write MAC initialization values. */ 3818 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3819 for (i = 0; i < __arraycount(rtl8188eu_mac); i++) 3820 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 3821 rtl8188eu_mac[i].val); 3822 } else if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3823 for (i = 0; i < __arraycount(rtl8192eu_mac); i++) 3824 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 3825 rtl8192eu_mac[i].val); 3826 } else { 3827 for (i = 0; i < __arraycount(rtl8192cu_mac); i++) 3828 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 3829 rtl8192cu_mac[i].val); 3830 } 3831 } 3832 3833 static void __noinline 3834 urtwn_bb_init(struct urtwn_softc *sc) 3835 { 3836 const struct rtwn_bb_prog *prog; 3837 uint32_t reg; 3838 uint8_t crystalcap; 3839 size_t i; 3840 3841 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 3842 3843 KASSERT(mutex_owned(&sc->sc_write_mtx)); 3844 3845 /* Enable BB and RF. */ 3846 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 3847 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 3848 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 3849 R92C_SYS_FUNC_EN_DIO_RF); 3850 3851 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3852 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3853 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x83); 3854 urtwn_write_1(sc, R92C_AFE_PLL_CTRL + 1, 0xdb); 3855 } 3856 3857 urtwn_write_1(sc, R92C_RF_CTRL, 3858 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 3859 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 3860 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 3861 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 3862 3863 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 3864 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 3865 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 3866 urtwn_write_1(sc, 0x15, 0xe9); 3867 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 3868 } 3869 3870 /* Select BB programming based on board type. */ 3871 if (ISSET(sc->chip, URTWN_CHIP_88E)) 3872 prog = &rtl8188eu_bb_prog; 3873 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 3874 prog = &rtl8192eu_bb_prog; 3875 else if (!(sc->chip & URTWN_CHIP_92C)) { 3876 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3877 prog = &rtl8188ce_bb_prog; 3878 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 3879 prog = &rtl8188ru_bb_prog; 3880 } else { 3881 prog = &rtl8188cu_bb_prog; 3882 } 3883 } else { 3884 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 3885 prog = &rtl8192ce_bb_prog; 3886 } else { 3887 prog = &rtl8192cu_bb_prog; 3888 } 3889 } 3890 /* Write BB initialization values. */ 3891 for (i = 0; i < prog->count; i++) { 3892 /* additional delay depend on registers */ 3893 switch (prog->regs[i]) { 3894 case 0xfe: 3895 urtwn_delay_ms(sc, 50); 3896 break; 3897 case 0xfd: 3898 urtwn_delay_ms(sc, 5); 3899 break; 3900 case 0xfc: 3901 urtwn_delay_ms(sc, 1); 3902 break; 3903 case 0xfb: 3904 DELAY(50); 3905 break; 3906 case 0xfa: 3907 DELAY(5); 3908 break; 3909 case 0xf9: 3910 DELAY(1); 3911 break; 3912 } 3913 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 3914 DELAY(1); 3915 } 3916 3917 if (sc->chip & URTWN_CHIP_92C_1T2R) { 3918 /* 8192C 1T only configuration. */ 3919 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 3920 reg = (reg & ~0x00000003) | 0x2; 3921 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 3922 3923 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 3924 reg = (reg & ~0x00300033) | 0x00200022; 3925 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 3926 3927 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 3928 reg = (reg & ~0xff000000) | (0x45 << 24); 3929 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 3930 3931 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 3932 reg = (reg & ~0x000000ff) | 0x23; 3933 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 3934 3935 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 3936 reg = (reg & ~0x00000030) | (1 << 4); 3937 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 3938 3939 reg = urtwn_bb_read(sc, 0xe74); 3940 reg = (reg & ~0x0c000000) | (2 << 26); 3941 urtwn_bb_write(sc, 0xe74, reg); 3942 reg = urtwn_bb_read(sc, 0xe78); 3943 reg = (reg & ~0x0c000000) | (2 << 26); 3944 urtwn_bb_write(sc, 0xe78, reg); 3945 reg = urtwn_bb_read(sc, 0xe7c); 3946 reg = (reg & ~0x0c000000) | (2 << 26); 3947 urtwn_bb_write(sc, 0xe7c, reg); 3948 reg = urtwn_bb_read(sc, 0xe80); 3949 reg = (reg & ~0x0c000000) | (2 << 26); 3950 urtwn_bb_write(sc, 0xe80, reg); 3951 reg = urtwn_bb_read(sc, 0xe88); 3952 reg = (reg & ~0x0c000000) | (2 << 26); 3953 urtwn_bb_write(sc, 0xe88, reg); 3954 } 3955 3956 /* Write AGC values. */ 3957 for (i = 0; i < prog->agccount; i++) { 3958 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, prog->agcvals[i]); 3959 DELAY(1); 3960 } 3961 3962 if (ISSET(sc->chip, URTWN_CHIP_88E) || 3963 ISSET(sc->chip, URTWN_CHIP_92EU)) { 3964 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 3965 DELAY(1); 3966 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 3967 DELAY(1); 3968 } 3969 3970 if (ISSET(sc->chip, URTWN_CHIP_92EU)) { 3971 crystalcap = sc->r88e_rom[0xb9]; 3972 if (crystalcap == 0x00) 3973 crystalcap = 0x20; 3974 crystalcap &= 0x3f; 3975 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 3976 urtwn_bb_write(sc, R92C_AFE_CTRL3, 3977 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3978 crystalcap | crystalcap << 6)); 3979 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0xf81fb); 3980 } else if (ISSET(sc->chip, URTWN_CHIP_88E)) { 3981 crystalcap = sc->r88e_rom[0xb9]; 3982 if (crystalcap == 0xff) 3983 crystalcap = 0x20; 3984 crystalcap &= 0x3f; 3985 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 3986 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 3987 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 3988 crystalcap | crystalcap << 6)); 3989 } else { 3990 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 3991 R92C_HSSI_PARAM2_CCK_HIPWR) { 3992 SET(sc->sc_flags, URTWN_FLAG_CCK_HIPWR); 3993 } 3994 } 3995 } 3996 3997 static void __noinline 3998 urtwn_rf_init(struct urtwn_softc *sc) 3999 { 4000 const struct rtwn_rf_prog *prog; 4001 uint32_t reg, mask, saved; 4002 size_t i, j, idx; 4003 4004 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4005 4006 /* Select RF programming based on board type. */ 4007 if (ISSET(sc->chip, URTWN_CHIP_88E)) 4008 prog = rtl8188eu_rf_prog; 4009 else if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4010 prog = rtl8192eu_rf_prog; 4011 else if (!(sc->chip & URTWN_CHIP_92C)) { 4012 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) { 4013 prog = rtl8188ce_rf_prog; 4014 } else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4015 prog = rtl8188ru_rf_prog; 4016 } else { 4017 prog = rtl8188cu_rf_prog; 4018 } 4019 } else { 4020 prog = rtl8192ce_rf_prog; 4021 } 4022 4023 for (i = 0; i < sc->nrxchains; i++) { 4024 /* Save RF_ENV control type. */ 4025 idx = i / 2; 4026 mask = 0xffffU << ((i % 2) * 16); 4027 saved = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & mask; 4028 4029 /* Set RF_ENV enable. */ 4030 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4031 reg |= 0x100000; 4032 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4033 DELAY(50); 4034 4035 /* Set RF_ENV output high. */ 4036 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 4037 reg |= 0x10; 4038 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 4039 DELAY(50); 4040 4041 /* Set address and data lengths of RF registers. */ 4042 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4043 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 4044 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4045 DELAY(50); 4046 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 4047 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 4048 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 4049 DELAY(50); 4050 4051 /* Write RF initialization values for this chain. */ 4052 for (j = 0; j < prog[i].count; j++) { 4053 if (prog[i].regs[j] >= 0xf9 && 4054 prog[i].regs[j] <= 0xfe) { 4055 /* 4056 * These are fake RF registers offsets that 4057 * indicate a delay is required. 4058 */ 4059 urtwn_delay_ms(sc, 50); 4060 continue; 4061 } 4062 urtwn_rf_write(sc, i, prog[i].regs[j], prog[i].vals[j]); 4063 DELAY(5); 4064 } 4065 4066 /* Restore RF_ENV control type. */ 4067 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)) & ~mask; 4068 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg | saved); 4069 } 4070 4071 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 4072 URTWN_CHIP_UMC_A_CUT) { 4073 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 4074 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 4075 } 4076 4077 /* Cache RF register CHNLBW. */ 4078 for (i = 0; i < 2; i++) { 4079 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 4080 } 4081 } 4082 4083 static void __noinline 4084 urtwn_cam_init(struct urtwn_softc *sc) 4085 { 4086 uint32_t content, command; 4087 uint8_t idx; 4088 size_t i; 4089 4090 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4091 4092 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4093 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4094 return; 4095 4096 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4097 content = (idx & 3) 4098 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4099 | R92C_CAM_VALID; 4100 4101 command = R92C_CAMCMD_POLLING 4102 | R92C_CAMCMD_WRITE 4103 | R92C_CAM_CTL0(idx); 4104 4105 urtwn_write_4(sc, R92C_CAMWRITE, content); 4106 urtwn_write_4(sc, R92C_CAMCMD, command); 4107 } 4108 4109 for (idx = 0; idx < R92C_CAM_ENTRY_COUNT; idx++) { 4110 for (i = 0; i < /* CAM_CONTENT_COUNT */ 8; i++) { 4111 if (i == 0) { 4112 content = (idx & 3) 4113 | (R92C_CAM_ALGO_AES << R92C_CAM_ALGO_S) 4114 | R92C_CAM_VALID; 4115 } else { 4116 content = 0; 4117 } 4118 4119 command = R92C_CAMCMD_POLLING 4120 | R92C_CAMCMD_WRITE 4121 | R92C_CAM_CTL0(idx) 4122 | i; 4123 4124 urtwn_write_4(sc, R92C_CAMWRITE, content); 4125 urtwn_write_4(sc, R92C_CAMCMD, command); 4126 } 4127 } 4128 4129 /* Invalidate all CAM entries. */ 4130 urtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 4131 } 4132 4133 static void __noinline 4134 urtwn_pa_bias_init(struct urtwn_softc *sc) 4135 { 4136 uint8_t reg; 4137 size_t i; 4138 4139 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4140 4141 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4142 4143 for (i = 0; i < sc->nrxchains; i++) { 4144 if (sc->pa_setting & (1U << i)) 4145 continue; 4146 4147 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 4148 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 4149 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 4150 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 4151 } 4152 if (!(sc->pa_setting & 0x10)) { 4153 reg = urtwn_read_1(sc, 0x16); 4154 reg = (reg & ~0xf0) | 0x90; 4155 urtwn_write_1(sc, 0x16, reg); 4156 } 4157 } 4158 4159 static void __noinline 4160 urtwn_rxfilter_init(struct urtwn_softc *sc) 4161 { 4162 4163 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4164 4165 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4166 4167 /* Initialize Rx filter. */ 4168 /* TODO: use better filter for monitor mode. */ 4169 urtwn_write_4(sc, R92C_RCR, 4170 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 4171 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 4172 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 4173 /* Accept all multicast frames. */ 4174 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 4175 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 4176 /* Accept all management frames. */ 4177 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 4178 /* Reject all control frames. */ 4179 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 4180 /* Accept all data frames. */ 4181 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 4182 } 4183 4184 static void __noinline 4185 urtwn_edca_init(struct urtwn_softc *sc) 4186 { 4187 4188 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4189 4190 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4191 4192 /* set spec SIFS (used in NAV) */ 4193 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 4194 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 4195 4196 /* set SIFS CCK/OFDM */ 4197 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 4198 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 4199 4200 /* TXOP */ 4201 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 4202 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 4203 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 4204 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 4205 } 4206 4207 static void 4208 urtwn_write_txpower(struct urtwn_softc *sc, int chain, 4209 uint16_t power[URTWN_RIDX_COUNT]) 4210 { 4211 uint32_t reg; 4212 4213 URTWNHIST_FUNC(); 4214 URTWNHIST_CALLARGS("chain=%jd", chain, 0, 0, 0); 4215 4216 /* Write per-CCK rate Tx power. */ 4217 if (chain == 0) { 4218 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 4219 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 4220 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 4221 4222 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4223 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 4224 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 4225 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 4226 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4227 } else { 4228 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 4229 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 4230 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 4231 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 4232 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 4233 4234 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 4235 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 4236 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 4237 } 4238 /* Write per-OFDM rate Tx power. */ 4239 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 4240 SM(R92C_TXAGC_RATE06, power[ 4]) | 4241 SM(R92C_TXAGC_RATE09, power[ 5]) | 4242 SM(R92C_TXAGC_RATE12, power[ 6]) | 4243 SM(R92C_TXAGC_RATE18, power[ 7])); 4244 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 4245 SM(R92C_TXAGC_RATE24, power[ 8]) | 4246 SM(R92C_TXAGC_RATE36, power[ 9]) | 4247 SM(R92C_TXAGC_RATE48, power[10]) | 4248 SM(R92C_TXAGC_RATE54, power[11])); 4249 /* Write per-MCS Tx power. */ 4250 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 4251 SM(R92C_TXAGC_MCS00, power[12]) | 4252 SM(R92C_TXAGC_MCS01, power[13]) | 4253 SM(R92C_TXAGC_MCS02, power[14]) | 4254 SM(R92C_TXAGC_MCS03, power[15])); 4255 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 4256 SM(R92C_TXAGC_MCS04, power[16]) | 4257 SM(R92C_TXAGC_MCS05, power[17]) | 4258 SM(R92C_TXAGC_MCS06, power[18]) | 4259 SM(R92C_TXAGC_MCS07, power[19])); 4260 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 4261 SM(R92C_TXAGC_MCS08, power[20]) | 4262 SM(R92C_TXAGC_MCS09, power[21]) | 4263 SM(R92C_TXAGC_MCS10, power[22]) | 4264 SM(R92C_TXAGC_MCS11, power[23])); 4265 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 4266 SM(R92C_TXAGC_MCS12, power[24]) | 4267 SM(R92C_TXAGC_MCS13, power[25]) | 4268 SM(R92C_TXAGC_MCS14, power[26]) | 4269 SM(R92C_TXAGC_MCS15, power[27])); 4270 } 4271 4272 static void 4273 urtwn_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, u_int ht40m, 4274 uint16_t power[URTWN_RIDX_COUNT]) 4275 { 4276 struct r92c_rom *rom = &sc->rom; 4277 uint16_t cckpow, ofdmpow, htpow, diff, maxpow; 4278 const struct rtwn_txpwr *base; 4279 int ridx, group; 4280 4281 URTWNHIST_FUNC(); 4282 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4283 4284 /* Determine channel group. */ 4285 if (chan <= 3) { 4286 group = 0; 4287 } else if (chan <= 9) { 4288 group = 1; 4289 } else { 4290 group = 2; 4291 } 4292 4293 /* Get original Tx power based on board type and RF chain. */ 4294 if (!(sc->chip & URTWN_CHIP_92C)) { 4295 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) { 4296 base = &rtl8188ru_txagc[chain]; 4297 } else { 4298 base = &rtl8192cu_txagc[chain]; 4299 } 4300 } else { 4301 base = &rtl8192cu_txagc[chain]; 4302 } 4303 4304 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4305 if (sc->regulatory == 0) { 4306 for (ridx = 0; ridx <= 3; ridx++) { 4307 power[ridx] = base->pwr[0][ridx]; 4308 } 4309 } 4310 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4311 if (sc->regulatory == 3) { 4312 power[ridx] = base->pwr[0][ridx]; 4313 /* Apply vendor limits. */ 4314 if (ht40m != IEEE80211_HTINFO_2NDCHAN_NONE) { 4315 maxpow = rom->ht40_max_pwr[group]; 4316 } else { 4317 maxpow = rom->ht20_max_pwr[group]; 4318 } 4319 maxpow = (maxpow >> (chain * 4)) & 0xf; 4320 if (power[ridx] > maxpow) { 4321 power[ridx] = maxpow; 4322 } 4323 } else if (sc->regulatory == 1) { 4324 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4325 power[ridx] = base->pwr[group][ridx]; 4326 } 4327 } else if (sc->regulatory != 2) { 4328 power[ridx] = base->pwr[0][ridx]; 4329 } 4330 } 4331 4332 /* Compute per-CCK rate Tx power. */ 4333 cckpow = rom->cck_tx_pwr[chain][group]; 4334 for (ridx = 0; ridx <= 3; ridx++) { 4335 power[ridx] += cckpow; 4336 if (power[ridx] > R92C_MAX_TX_PWR) { 4337 power[ridx] = R92C_MAX_TX_PWR; 4338 } 4339 } 4340 4341 htpow = rom->ht40_1s_tx_pwr[chain][group]; 4342 if (sc->ntxchains > 1) { 4343 /* Apply reduction for 2 spatial streams. */ 4344 diff = rom->ht40_2s_tx_pwr_diff[group]; 4345 diff = (diff >> (chain * 4)) & 0xf; 4346 htpow = (htpow > diff) ? htpow - diff : 0; 4347 } 4348 4349 /* Compute per-OFDM rate Tx power. */ 4350 diff = rom->ofdm_tx_pwr_diff[group]; 4351 diff = (diff >> (chain * 4)) & 0xf; 4352 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 4353 for (ridx = 4; ridx <= 11; ridx++) { 4354 power[ridx] += ofdmpow; 4355 if (power[ridx] > R92C_MAX_TX_PWR) { 4356 power[ridx] = R92C_MAX_TX_PWR; 4357 } 4358 } 4359 4360 /* Compute per-MCS Tx power. */ 4361 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) { 4362 diff = rom->ht20_tx_pwr_diff[group]; 4363 diff = (diff >> (chain * 4)) & 0xf; 4364 htpow += diff; /* HT40->HT20 correction. */ 4365 } 4366 for (ridx = 12; ridx < URTWN_RIDX_COUNT; ridx++) { 4367 power[ridx] += htpow; 4368 if (power[ridx] > R92C_MAX_TX_PWR) { 4369 power[ridx] = R92C_MAX_TX_PWR; 4370 } 4371 } 4372 #ifdef URTWN_DEBUG 4373 if (urtwn_debug & DBG_RF) { 4374 /* Dump per-rate Tx power values. */ 4375 DPRINTFN(DBG_RF, "Tx power for chain %jd:", chain, 0, 0, 0); 4376 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 4377 DPRINTFN(DBG_RF, "Rate %jd = %ju", ridx, power[ridx], 0, 0); 4378 } 4379 #endif 4380 } 4381 4382 void 4383 urtwn_r88e_get_txpower(struct urtwn_softc *sc, size_t chain, u_int chan, 4384 u_int ht40m, uint16_t power[URTWN_RIDX_COUNT]) 4385 { 4386 uint16_t cckpow, ofdmpow, bw20pow, htpow; 4387 const struct rtwn_r88e_txpwr *base; 4388 int ridx, group; 4389 4390 URTWNHIST_FUNC(); 4391 URTWNHIST_CALLARGS("chain=%jd, chan=%jd", chain, chan, 0, 0); 4392 4393 /* Determine channel group. */ 4394 if (chan <= 2) 4395 group = 0; 4396 else if (chan <= 5) 4397 group = 1; 4398 else if (chan <= 8) 4399 group = 2; 4400 else if (chan <= 11) 4401 group = 3; 4402 else if (chan <= 13) 4403 group = 4; 4404 else 4405 group = 5; 4406 4407 /* Get original Tx power based on board type and RF chain. */ 4408 base = &rtl8188eu_txagc[chain]; 4409 4410 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 4411 if (sc->regulatory == 0) { 4412 for (ridx = 0; ridx <= 3; ridx++) 4413 power[ridx] = base->pwr[0][ridx]; 4414 } 4415 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 4416 if (sc->regulatory == 3) 4417 power[ridx] = base->pwr[0][ridx]; 4418 else if (sc->regulatory == 1) { 4419 if (ht40m == IEEE80211_HTINFO_2NDCHAN_NONE) 4420 power[ridx] = base->pwr[group][ridx]; 4421 } else if (sc->regulatory != 2) 4422 power[ridx] = base->pwr[0][ridx]; 4423 } 4424 4425 /* Compute per-CCK rate Tx power. */ 4426 cckpow = sc->cck_tx_pwr[group]; 4427 for (ridx = 0; ridx <= 3; ridx++) { 4428 power[ridx] += cckpow; 4429 if (power[ridx] > R92C_MAX_TX_PWR) 4430 power[ridx] = R92C_MAX_TX_PWR; 4431 } 4432 4433 htpow = sc->ht40_tx_pwr[group]; 4434 4435 /* Compute per-OFDM rate Tx power. */ 4436 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 4437 for (ridx = 4; ridx <= 11; ridx++) { 4438 power[ridx] += ofdmpow; 4439 if (power[ridx] > R92C_MAX_TX_PWR) 4440 power[ridx] = R92C_MAX_TX_PWR; 4441 } 4442 4443 bw20pow = htpow + sc->bw20_tx_pwr_diff; 4444 for (ridx = 12; ridx <= 27; ridx++) { 4445 power[ridx] += bw20pow; 4446 if (power[ridx] > R92C_MAX_TX_PWR) 4447 power[ridx] = R92C_MAX_TX_PWR; 4448 } 4449 } 4450 4451 static void 4452 urtwn_set_txpower(struct urtwn_softc *sc, u_int chan, u_int ht40m) 4453 { 4454 uint16_t power[URTWN_RIDX_COUNT]; 4455 size_t i; 4456 4457 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4458 4459 for (i = 0; i < sc->ntxchains; i++) { 4460 /* Compute per-rate Tx power values. */ 4461 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4462 ISSET(sc->chip, URTWN_CHIP_92EU)) 4463 urtwn_r88e_get_txpower(sc, i, chan, ht40m, power); 4464 else 4465 urtwn_get_txpower(sc, i, chan, ht40m, power); 4466 /* Write per-rate Tx power values to hardware. */ 4467 urtwn_write_txpower(sc, i, power); 4468 } 4469 } 4470 4471 static void __noinline 4472 urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, u_int ht40m) 4473 { 4474 struct ieee80211com *ic = &sc->sc_ic; 4475 u_int chan; 4476 size_t i; 4477 4478 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 4479 4480 URTWNHIST_FUNC(); 4481 URTWNHIST_CALLARGS("chan=%jd", chan, 0, 0, 0); 4482 4483 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4484 4485 if (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE) { 4486 chan += 2; 4487 } else if (ht40m == IEEE80211_HTINFO_2NDCHAN_BELOW){ 4488 chan -= 2; 4489 } 4490 4491 /* Set Tx power for this new channel. */ 4492 urtwn_set_txpower(sc, chan, ht40m); 4493 4494 for (i = 0; i < sc->nrxchains; i++) { 4495 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 4496 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 4497 } 4498 4499 if (ht40m) { 4500 /* Is secondary channel below or above primary? */ 4501 int prichlo = (ht40m == IEEE80211_HTINFO_2NDCHAN_ABOVE); 4502 uint32_t reg; 4503 4504 urtwn_write_1(sc, R92C_BWOPMODE, 4505 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 4506 4507 reg = urtwn_read_1(sc, R92C_RRSR + 2); 4508 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 4509 urtwn_write_1(sc, R92C_RRSR + 2, (uint8_t)reg); 4510 4511 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4512 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 4513 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4514 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 4515 4516 /* Set CCK side band. */ 4517 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 4518 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 4519 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 4520 4521 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 4522 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 4523 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 4524 4525 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4526 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 4527 ~R92C_FPGA0_ANAPARAM2_CBW20); 4528 4529 reg = urtwn_bb_read(sc, 0x818); 4530 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 4531 urtwn_bb_write(sc, 0x818, reg); 4532 4533 /* Select 40MHz bandwidth. */ 4534 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4535 (sc->rf_chnlbw[0] & ~0xfff) | chan); 4536 } else { 4537 urtwn_write_1(sc, R92C_BWOPMODE, 4538 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 4539 4540 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 4541 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 4542 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 4543 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 4544 4545 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4546 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4547 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 4548 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 4549 R92C_FPGA0_ANAPARAM2_CBW20); 4550 } 4551 4552 /* Select 20MHz bandwidth. */ 4553 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4554 (sc->rf_chnlbw[0] & ~0xfff) | chan | 4555 (ISSET(sc->chip, URTWN_CHIP_88E) || 4556 ISSET(sc->chip, URTWN_CHIP_92EU) ? 4557 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 4558 } 4559 } 4560 4561 static void __noinline 4562 urtwn_iq_calib(struct urtwn_softc *sc, bool inited) 4563 { 4564 4565 URTWNHIST_FUNC(); 4566 URTWNHIST_CALLARGS("inited=%jd", inited, 0, 0, 0); 4567 4568 uint32_t addaBackup[16], iqkBackup[4], piMode; 4569 4570 #ifdef notyet 4571 uint32_t odfm0_agccore_regs[3]; 4572 uint32_t ant_regs[3]; 4573 uint32_t rf_regs[8]; 4574 #endif 4575 uint32_t reg0, reg1, reg2; 4576 int i, attempt; 4577 4578 #ifdef notyet 4579 urtwn_write_1(sc, R92E_STBC_SETTING + 2, urtwn_read_1(sc, 4580 R92E_STBC_SETTING + 2)); 4581 urtwn_write_1(sc, R92C_ACLK_MON, 0); 4582 /* Save AGCCORE regs. */ 4583 for (i = 0; i < sc->nrxchains; i++) { 4584 odfm0_agccore_regs[i] = urtwn_read_4(sc, 4585 R92C_OFDM0_AGCCORE1(i)); 4586 } 4587 #endif 4588 /* Save BB regs. */ 4589 reg0 = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 4590 reg1 = urtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 4591 reg2 = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 4592 4593 /* Save adda regs to be restored when finished. */ 4594 for (i = 0; i < __arraycount(addaReg); i++) 4595 addaBackup[i] = urtwn_bb_read(sc, addaReg[i]); 4596 /* Save mac regs. */ 4597 iqkBackup[0] = urtwn_read_1(sc, R92C_TXPAUSE); 4598 iqkBackup[1] = urtwn_read_1(sc, R92C_BCN_CTRL); 4599 iqkBackup[2] = urtwn_read_1(sc, R92C_BCN_CTRL1); 4600 iqkBackup[3] = urtwn_read_4(sc, R92C_GPIO_MUXCFG); 4601 4602 #ifdef notyet 4603 ant_regs[0] = urtwn_read_4(sc, R92C_CONFIG_ANT_A); 4604 ant_regs[1] = urtwn_read_4(sc, R92C_CONFIG_ANT_B); 4605 4606 rf_regs[0] = urtwn_read_4(sc, R92C_FPGA0_RFIFACESW(0)); 4607 for (i = 0; i < sc->nrxchains; i++) 4608 rf_regs[i+1] = urtwn_read_4(sc, R92C_FPGA0_RFIFACEOE(i)); 4609 reg4 = urtwn_read_4(sc, R92C_CCK0_AFESETTING); 4610 #endif 4611 4612 piMode = (urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4613 R92C_HSSI_PARAM1_PI); 4614 if (piMode == 0) { 4615 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4616 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0))| 4617 R92C_HSSI_PARAM1_PI); 4618 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4619 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1))| 4620 R92C_HSSI_PARAM1_PI); 4621 } 4622 4623 attempt = 1; 4624 4625 next_attempt: 4626 4627 /* Set mac regs for calibration. */ 4628 for (i = 0; i < __arraycount(addaReg); i++) { 4629 urtwn_bb_write(sc, addaReg[i], 4630 addaReg[__arraycount(addaReg) - 1]); 4631 } 4632 urtwn_write_2(sc, R92C_CCK0_AFESETTING, urtwn_read_2(sc, 4633 R92C_CCK0_AFESETTING)); 4634 urtwn_write_2(sc, R92C_OFDM0_TRXPATHENA, R92C_IQK_TRXPATHENA); 4635 urtwn_write_2(sc, R92C_OFDM0_TRMUXPAR, R92C_IQK_TRMUXPAR); 4636 urtwn_write_2(sc, R92C_FPGA0_RFIFACESW(1), R92C_IQK_RFIFACESW1); 4637 urtwn_write_4(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_PARAM); 4638 4639 if (sc->ntxchains > 1) 4640 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_PARAM); 4641 4642 urtwn_write_1(sc, R92C_TXPAUSE, (~R92C_TXPAUSE_BCN) & R92C_TXPAUSE_ALL); 4643 urtwn_write_1(sc, R92C_BCN_CTRL, (iqkBackup[1] & 4644 ~R92C_BCN_CTRL_EN_BCN)); 4645 urtwn_write_1(sc, R92C_BCN_CTRL1, (iqkBackup[2] & 4646 ~R92C_BCN_CTRL_EN_BCN)); 4647 4648 urtwn_write_1(sc, R92C_GPIO_MUXCFG, (iqkBackup[3] & 4649 ~R92C_GPIO_MUXCFG_ENBT)); 4650 4651 urtwn_bb_write(sc, R92C_CONFIG_ANT_A, R92C_IQK_CONFIG_ANT); 4652 4653 if (sc->ntxchains > 1) 4654 urtwn_bb_write(sc, R92C_CONFIG_ANT_B, R92C_IQK_CONFIG_ANT); 4655 urtwn_bb_write(sc, R92C_FPGA0_IQK, R92C_FPGA0_IQK_SETTING); 4656 urtwn_bb_write(sc, R92C_TX_IQK, R92C_TX_IQK_SETTING); 4657 urtwn_bb_write(sc, R92C_RX_IQK, R92C_RX_IQK_SETTING); 4658 4659 /* Restore BB regs. */ 4660 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg0); 4661 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), reg2); 4662 urtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, reg1); 4663 4664 urtwn_bb_write(sc, R92C_FPGA0_IQK, 0x0); 4665 urtwn_bb_write(sc, R92C_LSSI_PARAM(0), R92C_IQK_LSSI_RESTORE); 4666 if (sc->nrxchains > 1) 4667 urtwn_bb_write(sc, R92C_LSSI_PARAM(1), R92C_IQK_LSSI_RESTORE); 4668 4669 if (attempt-- > 0) 4670 goto next_attempt; 4671 4672 /* Restore mode. */ 4673 if (piMode == 0) { 4674 urtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 4675 urtwn_bb_read(sc, R92C_HSSI_PARAM1(0)) & 4676 ~R92C_HSSI_PARAM1_PI); 4677 urtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 4678 urtwn_bb_read(sc, R92C_HSSI_PARAM1(1)) & 4679 ~R92C_HSSI_PARAM1_PI); 4680 } 4681 4682 #ifdef notyet 4683 for (i = 0; i < sc->nrxchains; i++) { 4684 urtwn_write_4(sc, R92C_OFDM0_AGCCORE1(i), 4685 odfm0_agccore_regs[i]); 4686 } 4687 #endif 4688 4689 /* Restore adda regs. */ 4690 for (i = 0; i < __arraycount(addaReg); i++) 4691 urtwn_bb_write(sc, addaReg[i], addaBackup[i]); 4692 /* Restore mac regs. */ 4693 urtwn_write_1(sc, R92C_TXPAUSE, iqkBackup[0]); 4694 urtwn_write_1(sc, R92C_BCN_CTRL, iqkBackup[1]); 4695 urtwn_write_1(sc, R92C_USTIME_TSF, iqkBackup[2]); 4696 urtwn_write_4(sc, R92C_GPIO_MUXCFG, iqkBackup[3]); 4697 4698 #ifdef notyet 4699 urtwn_write_4(sc, R92C_CONFIG_ANT_A, ant_regs[0]); 4700 urtwn_write_4(sc, R92C_CONFIG_ANT_B, ant_regs[1]); 4701 4702 urtwn_write_4(sc, R92C_FPGA0_RFIFACESW(0), rf_regs[0]); 4703 for (i = 0; i < sc->nrxchains; i++) 4704 urtwn_write_4(sc, R92C_FPGA0_RFIFACEOE(i), rf_regs[i+1]); 4705 urtwn_write_4(sc, R92C_CCK0_AFESETTING, reg4); 4706 #endif 4707 } 4708 4709 static void 4710 urtwn_lc_calib(struct urtwn_softc *sc) 4711 { 4712 uint32_t rf_ac[2]; 4713 uint8_t txmode; 4714 size_t i; 4715 4716 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4717 4718 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4719 4720 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 4721 if ((txmode & 0x70) != 0) { 4722 /* Disable all continuous Tx. */ 4723 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 4724 4725 /* Set RF mode to standby mode. */ 4726 for (i = 0; i < sc->nrxchains; i++) { 4727 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 4728 urtwn_rf_write(sc, i, R92C_RF_AC, 4729 RW(rf_ac[i], R92C_RF_AC_MODE, 4730 R92C_RF_AC_MODE_STANDBY)); 4731 } 4732 } else { 4733 /* Block all Tx queues. */ 4734 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 4735 } 4736 /* Start calibration. */ 4737 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 4738 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 4739 4740 /* Give calibration the time to complete. */ 4741 urtwn_delay_ms(sc, 100); 4742 4743 /* Restore configuration. */ 4744 if ((txmode & 0x70) != 0) { 4745 /* Restore Tx mode. */ 4746 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 4747 /* Restore RF mode. */ 4748 for (i = 0; i < sc->nrxchains; i++) { 4749 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 4750 } 4751 } else { 4752 /* Unblock all Tx queues. */ 4753 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 4754 } 4755 } 4756 4757 static void 4758 urtwn_temp_calib(struct urtwn_softc *sc) 4759 { 4760 int temp, t_meter_reg; 4761 4762 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4763 4764 KASSERT(mutex_owned(&sc->sc_write_mtx)); 4765 4766 if (!ISSET(sc->chip, URTWN_CHIP_92EU)) 4767 t_meter_reg = R92C_RF_T_METER; 4768 else 4769 t_meter_reg = R92E_RF_T_METER; 4770 4771 if (sc->thcal_state == 0) { 4772 /* Start measuring temperature. */ 4773 DPRINTFN(DBG_RF, "start measuring temperature", 0, 0, 0, 0); 4774 urtwn_rf_write(sc, 0, t_meter_reg, 0x60); 4775 sc->thcal_state = 1; 4776 return; 4777 } 4778 sc->thcal_state = 0; 4779 4780 /* Read measured temperature. */ 4781 temp = urtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 4782 DPRINTFN(DBG_RF, "temperature=%jd", temp, 0, 0, 0); 4783 if (temp == 0) /* Read failed, skip. */ 4784 return; 4785 4786 /* 4787 * Redo LC calibration if temperature changed significantly since 4788 * last calibration. 4789 */ 4790 if (sc->thcal_lctemp == 0) { 4791 /* First LC calibration is performed in urtwn_init(). */ 4792 sc->thcal_lctemp = temp; 4793 } else if (abs(temp - sc->thcal_lctemp) > 1) { 4794 DPRINTFN(DBG_RF, "LC calib triggered by temp: %jd -> %jd", 4795 sc->thcal_lctemp, temp, 0, 0); 4796 urtwn_lc_calib(sc); 4797 /* Record temperature of last LC calibration. */ 4798 sc->thcal_lctemp = temp; 4799 } 4800 } 4801 4802 static int 4803 urtwn_init(struct ifnet *ifp) 4804 { 4805 struct urtwn_softc *sc = ifp->if_softc; 4806 struct ieee80211com *ic = &sc->sc_ic; 4807 struct urtwn_rx_data *data; 4808 uint32_t reg; 4809 size_t i; 4810 int error; 4811 4812 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 4813 4814 urtwn_stop(ifp, 0); 4815 4816 mutex_enter(&sc->sc_write_mtx); 4817 4818 mutex_enter(&sc->sc_task_mtx); 4819 /* Init host async commands ring. */ 4820 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4821 mutex_exit(&sc->sc_task_mtx); 4822 4823 mutex_enter(&sc->sc_fwcmd_mtx); 4824 /* Init firmware commands ring. */ 4825 sc->fwcur = 0; 4826 mutex_exit(&sc->sc_fwcmd_mtx); 4827 4828 /* Allocate Tx/Rx buffers. */ 4829 error = urtwn_alloc_rx_list(sc); 4830 if (error != 0) { 4831 aprint_error_dev(sc->sc_dev, 4832 "could not allocate Rx buffers\n"); 4833 goto fail; 4834 } 4835 error = urtwn_alloc_tx_list(sc); 4836 if (error != 0) { 4837 aprint_error_dev(sc->sc_dev, 4838 "could not allocate Tx buffers\n"); 4839 goto fail; 4840 } 4841 4842 /* Power on adapter. */ 4843 error = urtwn_power_on(sc); 4844 if (error != 0) 4845 goto fail; 4846 4847 /* Initialize DMA. */ 4848 error = urtwn_dma_init(sc); 4849 if (error != 0) 4850 goto fail; 4851 4852 /* Set info size in Rx descriptors (in 64-bit words). */ 4853 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 4854 4855 /* Init interrupts. */ 4856 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4857 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4858 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 4859 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 4860 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 4861 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 4862 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 4863 if (ISSET(sc->chip, URTWN_CHIP_88E)) { 4864 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4865 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 4866 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 4867 } 4868 if (ISSET(sc->chip, URTWN_CHIP_92EU)) 4869 urtwn_write_1(sc, R92C_USB_HRPWM, 0); 4870 } else { 4871 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 4872 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 4873 } 4874 4875 /* Set MAC address. */ 4876 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4877 urtwn_write_region(sc, R92C_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); 4878 4879 /* Set initial network type. */ 4880 reg = urtwn_read_4(sc, R92C_CR); 4881 switch (ic->ic_opmode) { 4882 case IEEE80211_M_STA: 4883 default: 4884 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 4885 break; 4886 4887 case IEEE80211_M_IBSS: 4888 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_ADHOC); 4889 break; 4890 } 4891 urtwn_write_4(sc, R92C_CR, reg); 4892 4893 /* Set response rate */ 4894 reg = urtwn_read_4(sc, R92C_RRSR); 4895 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 4896 urtwn_write_4(sc, R92C_RRSR, reg); 4897 4898 /* SIFS (used in NAV) */ 4899 urtwn_write_2(sc, R92C_SPEC_SIFS, 4900 SM(R92C_SPEC_SIFS_CCK, 0x10) | SM(R92C_SPEC_SIFS_OFDM, 0x10)); 4901 4902 /* Set short/long retry limits. */ 4903 urtwn_write_2(sc, R92C_RL, 4904 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 4905 4906 /* Initialize EDCA parameters. */ 4907 urtwn_edca_init(sc); 4908 4909 /* Setup rate fallback. */ 4910 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4911 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4912 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 4913 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 4914 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 4915 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 4916 } 4917 4918 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 4919 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 4920 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 4921 /* Set ACK timeout. */ 4922 urtwn_write_1(sc, R92C_ACKTO, 0x40); 4923 4924 /* Setup USB aggregation. */ 4925 /* Tx */ 4926 reg = urtwn_read_4(sc, R92C_TDECTRL); 4927 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 4928 urtwn_write_4(sc, R92C_TDECTRL, reg); 4929 /* Rx */ 4930 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 4931 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 4932 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 4933 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 4934 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 4935 ~R92C_USB_SPECIAL_OPTION_AGG_EN); 4936 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 4937 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4938 ISSET(sc->chip, URTWN_CHIP_92EU)) 4939 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 4940 else 4941 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 4942 4943 /* Initialize beacon parameters. */ 4944 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 4945 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 4946 urtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 4947 urtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 4948 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 4949 4950 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 4951 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 4952 /* Setup AMPDU aggregation. */ 4953 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 4954 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 4955 urtwn_write_2(sc, 0x4ca, 0x0708); 4956 4957 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 4958 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 4959 } 4960 4961 /* Load 8051 microcode. */ 4962 error = urtwn_load_firmware(sc); 4963 if (error != 0) 4964 goto fail; 4965 SET(sc->sc_flags, URTWN_FLAG_FWREADY); 4966 4967 /* Initialize MAC/BB/RF blocks. */ 4968 /* 4969 * XXX: urtwn_mac_init() sets R92C_RCR[0:15] = R92C_RCR_APM | 4970 * R92C_RCR_AM | R92C_RCR_AB | R92C_RCR_AICV | R92C_RCR_AMF. 4971 * XXX: This setting should be removed from rtl8192cu_mac[]. 4972 */ 4973 urtwn_mac_init(sc); // sets R92C_RCR[0:15] 4974 urtwn_rxfilter_init(sc); // reset R92C_RCR 4975 urtwn_bb_init(sc); 4976 urtwn_rf_init(sc); 4977 4978 if (ISSET(sc->chip, URTWN_CHIP_88E) || 4979 ISSET(sc->chip, URTWN_CHIP_92EU)) { 4980 urtwn_write_2(sc, R92C_CR, 4981 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 4982 R92C_CR_MACRXEN); 4983 } 4984 4985 /* Turn CCK and OFDM blocks on. */ 4986 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4987 reg |= R92C_RFMOD_CCK_EN; 4988 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4989 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 4990 reg |= R92C_RFMOD_OFDM_EN; 4991 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 4992 4993 /* Clear per-station keys table. */ 4994 urtwn_cam_init(sc); 4995 4996 /* Enable hardware sequence numbering. */ 4997 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 4998 4999 /* Perform LO and IQ calibrations. */ 5000 urtwn_iq_calib(sc, sc->iqk_inited); 5001 sc->iqk_inited = true; 5002 5003 /* Perform LC calibration. */ 5004 urtwn_lc_calib(sc); 5005 5006 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5007 !ISSET(sc->chip, URTWN_CHIP_92EU)) { 5008 /* Fix USB interference issue. */ 5009 urtwn_write_1(sc, 0xfe40, 0xe0); 5010 urtwn_write_1(sc, 0xfe41, 0x8d); 5011 urtwn_write_1(sc, 0xfe42, 0x80); 5012 urtwn_write_4(sc, 0x20c, 0xfd0320); 5013 5014 urtwn_pa_bias_init(sc); 5015 } 5016 5017 if (!(sc->chip & (URTWN_CHIP_92C | URTWN_CHIP_92C_1T2R)) || 5018 !(sc->chip & URTWN_CHIP_92EU)) { 5019 /* 1T1R */ 5020 urtwn_bb_write(sc, R92C_FPGA0_RFPARAM(0), 5021 urtwn_bb_read(sc, R92C_FPGA0_RFPARAM(0)) | __BIT(13)); 5022 } 5023 5024 /* Initialize GPIO setting. */ 5025 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 5026 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 5027 5028 /* Fix for lower temperature. */ 5029 if (!ISSET(sc->chip, URTWN_CHIP_88E) && 5030 !ISSET(sc->chip, URTWN_CHIP_92EU)) 5031 urtwn_write_1(sc, 0x15, 0xe9); 5032 5033 /* Set default channel. */ 5034 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5035 5036 /* Queue Rx xfers. */ 5037 for (size_t j = 0; j < sc->rx_npipe; j++) { 5038 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 5039 data = &sc->rx_data[j][i]; 5040 usbd_setup_xfer(data->xfer, data, data->buf, 5041 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, 5042 urtwn_rxeof); 5043 error = usbd_transfer(data->xfer); 5044 if (__predict_false(error != USBD_NORMAL_COMPLETION && 5045 error != USBD_IN_PROGRESS)) 5046 goto fail; 5047 } 5048 } 5049 5050 /* We're ready to go. */ 5051 ifp->if_flags &= ~IFF_OACTIVE; 5052 ifp->if_flags |= IFF_RUNNING; 5053 sc->sc_running = true; 5054 5055 mutex_exit(&sc->sc_write_mtx); 5056 5057 if (ic->ic_opmode == IEEE80211_M_MONITOR) 5058 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 5059 else if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 5060 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 5061 urtwn_wait_async(sc); 5062 5063 return 0; 5064 5065 fail: 5066 mutex_exit(&sc->sc_write_mtx); 5067 5068 urtwn_stop(ifp, 1); 5069 return error; 5070 } 5071 5072 static void __noinline 5073 urtwn_stop(struct ifnet *ifp, int disable) 5074 { 5075 struct urtwn_softc *sc = ifp->if_softc; 5076 struct ieee80211com *ic = &sc->sc_ic; 5077 size_t i; 5078 int s; 5079 5080 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5081 5082 s = splusb(); 5083 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 5084 urtwn_wait_async(sc); 5085 splx(s); 5086 5087 sc->tx_timer = 0; 5088 ifp->if_timer = 0; 5089 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 5090 5091 callout_stop(&sc->sc_scan_to); 5092 callout_stop(&sc->sc_calib_to); 5093 5094 /* Abort Tx. */ 5095 for (i = 0; i < sc->tx_npipe; i++) { 5096 if (sc->tx_pipe[i] != NULL) 5097 usbd_abort_pipe(sc->tx_pipe[i]); 5098 } 5099 5100 /* Stop Rx pipe. */ 5101 for (i = 0; i < sc->rx_npipe; i++) { 5102 if (sc->rx_pipe[i] != NULL) 5103 usbd_abort_pipe(sc->rx_pipe[i]); 5104 } 5105 5106 /* Free Tx/Rx buffers. */ 5107 urtwn_free_tx_list(sc); 5108 urtwn_free_rx_list(sc); 5109 5110 sc->sc_running = false; 5111 if (disable) 5112 urtwn_chip_stop(sc); 5113 } 5114 5115 static int 5116 urtwn_reset(struct ifnet *ifp) 5117 { 5118 struct urtwn_softc *sc = ifp->if_softc; 5119 struct ieee80211com *ic = &sc->sc_ic; 5120 5121 if (ic->ic_opmode != IEEE80211_M_MONITOR) 5122 return ENETRESET; 5123 5124 urtwn_set_chan(sc, ic->ic_curchan, IEEE80211_HTINFO_2NDCHAN_NONE); 5125 5126 return 0; 5127 } 5128 5129 static void 5130 urtwn_chip_stop(struct urtwn_softc *sc) 5131 { 5132 uint32_t reg; 5133 bool disabled = true; 5134 5135 URTWNHIST_FUNC(); URTWNHIST_CALLED(); 5136 5137 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5138 ISSET(sc->chip, URTWN_CHIP_92EU)) 5139 return; 5140 5141 mutex_enter(&sc->sc_write_mtx); 5142 5143 /* 5144 * RF Off Sequence 5145 */ 5146 /* Pause MAC TX queue */ 5147 urtwn_write_1(sc, R92C_TXPAUSE, 0xFF); 5148 5149 /* Disable RF */ 5150 urtwn_rf_write(sc, 0, 0, 0); 5151 5152 urtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF); 5153 5154 /* Reset BB state machine */ 5155 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5156 R92C_SYS_FUNC_EN_USBD | 5157 R92C_SYS_FUNC_EN_USBA | 5158 R92C_SYS_FUNC_EN_BB_GLB_RST); 5159 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 5160 R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA); 5161 5162 /* 5163 * Reset digital sequence 5164 */ 5165 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) { 5166 /* Reset MCU ready status */ 5167 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5168 /* If firmware in ram code, do reset */ 5169 if (ISSET(sc->sc_flags, URTWN_FLAG_FWREADY)) { 5170 if (ISSET(sc->chip, URTWN_CHIP_88E) || 5171 ISSET(sc->chip, URTWN_CHIP_92EU)) 5172 urtwn_r88e_fw_reset(sc); 5173 else 5174 urtwn_fw_reset(sc); 5175 CLR(sc->sc_flags, URTWN_FLAG_FWREADY); 5176 } 5177 } 5178 5179 /* Reset MAC and Enable 8051 */ 5180 urtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 5181 5182 /* Reset MCU ready status */ 5183 urtwn_write_1(sc, R92C_MCUFWDL, 0); 5184 5185 if (disabled) { 5186 /* Disable MAC clock */ 5187 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5188 /* Disable AFE PLL */ 5189 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80); 5190 /* Gated AFE DIG_CLOCK */ 5191 urtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F); 5192 /* Isolated digital to PON */ 5193 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 0xF9); 5194 } 5195 5196 /* 5197 * Pull GPIO PIN to balance level and LED control 5198 */ 5199 /* 1. Disable GPIO[7:0] */ 5200 urtwn_write_2(sc, R92C_GPIO_PIN_CTRL + 2, 0x0000); 5201 5202 reg = urtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00; 5203 reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000; 5204 urtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg); 5205 5206 /* Disable GPIO[10:8] */ 5207 urtwn_write_1(sc, R92C_GPIO_MUXCFG + 3, 0x00); 5208 5209 reg = urtwn_read_2(sc, R92C_GPIO_MUXCFG + 2) & ~0x00f0; 5210 reg |= (((reg & 0x000f) << 4) | 0x0780); 5211 urtwn_write_2(sc, R92C_GPIO_MUXCFG + 2, reg); 5212 5213 /* Disable LED0 & 1 */ 5214 urtwn_write_2(sc, R92C_LEDCFG0, 0x8080); 5215 5216 /* 5217 * Reset digital sequence 5218 */ 5219 if (disabled) { 5220 /* Disable ELDR clock */ 5221 urtwn_write_2(sc, R92C_SYS_CLKR, 0x70A3); 5222 /* Isolated ELDR to PON */ 5223 urtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1, 0x82); 5224 } 5225 5226 /* 5227 * Disable analog sequence 5228 */ 5229 if (disabled) { 5230 /* Disable A15 power */ 5231 urtwn_write_1(sc, R92C_LDOA15_CTRL, 0x04); 5232 /* Disable digital core power */ 5233 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 5234 urtwn_read_1(sc, R92C_LDOV12D_CTRL) & 5235 ~R92C_LDOV12D_CTRL_LDV12_EN); 5236 } 5237 5238 /* Enter PFM mode */ 5239 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); 5240 5241 /* Set USB suspend */ 5242 urtwn_write_2(sc, R92C_APS_FSMCO, 5243 R92C_APS_FSMCO_APDM_HOST | 5244 R92C_APS_FSMCO_AFSM_HSUS | 5245 R92C_APS_FSMCO_PFM_ALDN); 5246 5247 urtwn_write_1(sc, R92C_RSV_CTRL, 0x0E); 5248 5249 mutex_exit(&sc->sc_write_mtx); 5250 } 5251 5252 static void 5253 urtwn_delay_ms(struct urtwn_softc *sc, int ms) 5254 { 5255 if (sc->sc_running == false) 5256 DELAY(ms * 1000); 5257 else 5258 usbd_delay_ms(sc->sc_udev, ms); 5259 } 5260 5261 MODULE(MODULE_CLASS_DRIVER, if_urtwn, NULL); 5262 5263 #ifdef _MODULE 5264 #include "ioconf.c" 5265 #endif 5266 5267 static int 5268 if_urtwn_modcmd(modcmd_t cmd, void *aux) 5269 { 5270 int error = 0; 5271 5272 switch (cmd) { 5273 case MODULE_CMD_INIT: 5274 #ifdef _MODULE 5275 error = config_init_component(cfdriver_ioconf_urtwn, 5276 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5277 #endif 5278 return error; 5279 case MODULE_CMD_FINI: 5280 #ifdef _MODULE 5281 error = config_fini_component(cfdriver_ioconf_urtwn, 5282 cfattach_ioconf_urtwn, cfdata_ioconf_urtwn); 5283 #endif 5284 return error; 5285 default: 5286 return ENOTTY; 5287 } 5288 } 5289
Indexes created Sun Oct 25 00:26:45 UTC 2026