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      1 /* $NetBSD: xilinx_ml40x.c,v 1.4 2016/07/11 16:18:56 matt Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2010 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code was written by Alessandro Forin and Neil Pittman
      8  * at Microsoft Research and contributed to The NetBSD Foundation
      9  * by Microsoft Corporation.
     10  *
     11  * Redistribution and use in source and binary forms, with or without
     12  * modification, are permitted provided that the following conditions
     13  * are met:
     14  * 1. Redistributions of source code must retain the above copyright
     15  *    notice, this list of conditions and the following disclaimer.
     16  * 2. Redistributions in binary form must reproduce the above copyright
     17  *    notice, this list of conditions and the following disclaimer in the
     18  *    documentation and/or other materials provided with the distribution.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30  * POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 #include <sys/cdefs.h>
     34 __KERNEL_RCSID(0, "$NetBSD: xilinx_ml40x.c,v 1.4 2016/07/11 16:18:56 matt Exp $");
     35 
     36 #define __INTR_PRIVATE
     37 
     38 #include <sys/param.h>
     39 #include <sys/systm.h>
     40 #include <sys/device.h>
     41 #include <sys/cpu.h>
     42 
     43 #include <uvm/uvm_extern.h>
     44 
     45 #include <machine/cpu.h>
     46 #include <machine/intr.h>
     47 #include <machine/sysconf.h>
     48 #include <machine/locore.h>
     49 
     50 #include <emips/emips/machdep.h>
     51 #include <emips/emips/cons.h>
     52 #include <emips/emips/emipstype.h>
     53 #include <machine/emipsreg.h>
     54 
     55 
     56 void		xilinx_ml40x_init (void);
     57 static void	xilinx_ml40x_cons_init (void);
     58 
     59 #if 0
     60 #define NOINTS (MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
     61 #else
     62 #define NOINTS MIPS_INT_MASK
     63 #endif
     64 
     65 /* BUGBUG Rewrite this to go off to the interrupt controller masks */
     66 #if 0
     67 	splvec.splbio = MIPS_SPL0; // 0x700
     68 	splvec.splnet = MIPS_SPL_0_1; // 0xf00
     69 	splvec.spltty = MIPS_SPL_0_1_2; // 0x1f00
     70 	splvec.splvm = MIPS_SPLHIGH; // 0xff00
     71 	splvec.splclock = MIPS_SPL_0_1_2_3; //0x3f00
     72 	splvec.splstatclock = MIPS_SPL_0_1_2_3; //0x3f00
     73 #endif
     74 
     75 static const struct ipl_sr_map xilinx_ml40x_ipl_sr_map = {
     76     .sr_bits = {
     77 	[IPL_NONE] = 0,
     78 	[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
     79 	[IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
     80 	[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
     81 	[IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
     82 	[IPL_VM] = NOINTS,
     83 	[IPL_SCHED] = NOINTS,
     84 	[IPL_DDB] = NOINTS,
     85 	[IPL_HIGH] = NOINTS,
     86     },
     87 };
     88 
     89 void
     90 xilinx_ml40x_init(void)
     91 {
     92 	platform.iobus = "baseboard";
     93 	platform.bus_reset = noop;
     94 	platform.cons_init = xilinx_ml40x_cons_init;
     95 	platform.iointr = emips_aic_intr;
     96 	platform.intr_establish = emips_intr_establish;
     97 	platform.memsize = memsize_pmt;
     98 	/* no high resolution timer available (actually we do?) */
     99 
    100 	/* calibrate cpu_mhz value */
    101 	//cpu_mhz = 10;
    102 	cpuspeed = 8; /* xxx */
    103 
    104 	cpu_setmodel("Xilinx ML%s (eMIPS)",
    105 	    (systype == XS_ML40x) ? "40x" : "50x");
    106 
    107 	ipl_sr_map = xilinx_ml40x_ipl_sr_map;
    108 }
    109 
    110 static void
    111 xilinx_ml40x_cons_init(void)
    112 {
    113 	/*
    114 	 * Map the USART 1:1, we just turned on the TLB.
    115 	 * NB: This must be a wired TLB entry lest we lose it before autoconf().
    116 	 */
    117 #if 0
    118 	pmap_kenter_pa(USART_DEFAULT_ADDRESS,
    119 	    USART_DEFAULT_ADDRESS,VM_PROT_WRITE|VM_PROT_READ);
    120 #else
    121 	struct tlbmask tlb;
    122 
    123 	tlb.tlb_hi = USART_DEFAULT_ADDRESS;
    124 	tlb.tlb_lo0 = USART_DEFAULT_ADDRESS | 0xf02;
    125 	tlb_write_entry(3, &tlb);
    126 #endif
    127 
    128 	dz_ebus_cnsetup(USART_DEFAULT_ADDRESS);
    129 }
    130