1 /* $NetBSD: ata_wdc.c,v 1.121 2026/07/03 21:27:40 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ata_wdc.c,v 1.121 2026/07/03 21:27:40 thorpej Exp $"); 58 59 #include "opt_ata.h" 60 #include "opt_wdc.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/file.h> 66 #include <sys/stat.h> 67 #include <sys/buf.h> 68 #include <sys/bufq.h> 69 #include <sys/device.h> 70 #include <sys/disklabel.h> 71 #include <sys/dkbad.h> 72 #include <sys/syslog.h> 73 #include <sys/proc.h> 74 75 #include <sys/intr.h> 76 #include <sys/bus.h> 77 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 78 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 79 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 80 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 81 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 82 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 83 84 #include <dev/ata/ataconf.h> 85 #include <dev/ata/atareg.h> 86 #include <dev/ata/atavar.h> 87 #include <dev/ic/wdcreg.h> 88 #include <dev/ic/wdcvar.h> 89 90 #define DEBUG_INTR 0x01 91 #define DEBUG_XFERS 0x02 92 #define DEBUG_STATUS 0x04 93 #define DEBUG_FUNCS 0x08 94 #define DEBUG_PROBE 0x10 95 #ifdef ATADEBUG 96 extern int wdcdebug_wd_mask; /* inited in wd.c */ 97 #define ATADEBUG_PRINT(args, level) \ 98 if (wdcdebug_wd_mask & (level)) \ 99 printf args 100 #else 101 #define ATADEBUG_PRINT(args, level) 102 #endif 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 106 static void wdc_ata_bio(struct ata_drive_datas*, struct ata_xfer *); 107 static int wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 108 static int _wdc_ata_bio_start(struct ata_channel *,struct ata_xfer *); 109 static int wdc_ata_bio_poll(struct ata_channel *,struct ata_xfer *); 110 static int wdc_ata_bio_intr(struct ata_channel *, struct ata_xfer *, 111 int); 112 static void wdc_ata_bio_kill_xfer(struct ata_channel *, 113 struct ata_xfer *, int); 114 static void wdc_ata_bio_done(struct ata_channel *, struct ata_xfer *); 115 static int wdc_ata_err(struct ata_drive_datas *, struct ata_bio *, int); 116 #define WDC_ATA_NOERR 0x00 /* Drive doesn't report an error */ 117 #define WDC_ATA_RECOV 0x01 /* There was a recovered error */ 118 #define WDC_ATA_ERR 0x02 /* Drive reports an error */ 119 static int wdc_ata_addref(struct ata_drive_datas *); 120 static void wdc_ata_delref(struct ata_drive_datas *); 121 122 const struct ata_bustype wdc_ata_bustype = { 123 .bustype_type = SCSIPI_BUSTYPE_ATA, 124 .ata_bio = wdc_ata_bio, 125 .ata_reset_drive = wdc_reset_drive, 126 .ata_reset_channel = wdc_reset_channel, 127 .ata_exec_command = wdc_exec_command, 128 .ata_get_params = ata_get_params, 129 .ata_addref = wdc_ata_addref, 130 .ata_delref = wdc_ata_delref, 131 .ata_killpending = ata_kill_pending, 132 .ata_recovery = NULL, 133 }; 134 135 static const struct ata_xfer_ops wdc_bio_xfer_ops = { 136 .c_start = wdc_ata_bio_start, 137 .c_poll = wdc_ata_bio_poll, 138 .c_abort = wdc_ata_bio_done, 139 .c_intr = wdc_ata_bio_intr, 140 .c_kill_xfer = wdc_ata_bio_kill_xfer 141 }; 142 143 /* 144 * Handle block I/O operation. 145 */ 146 static void 147 wdc_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 148 { 149 struct ata_channel *chp = drvp->chnl_softc; 150 struct atac_softc *atac = chp->ch_atac; 151 struct ata_bio *ata_bio = &xfer->c_bio; 152 153 if (atac->atac_cap & ATAC_CAP_NOIRQ) 154 ata_bio->flags |= ATA_POLL; 155 if (ata_bio->flags & ATA_POLL) 156 xfer->c_flags |= C_POLL; 157 #if NATA_DMA 158 if ((drvp->drive_flags & (ATA_DRIVE_DMA | ATA_DRIVE_UDMA)) && 159 (ata_bio->flags & ATA_SINGLE) == 0) 160 xfer->c_flags |= C_DMA; 161 #endif 162 #if NATA_DMA && NATA_PIOBM 163 else 164 #endif 165 #if NATA_PIOBM 166 if (atac->atac_cap & ATAC_CAP_PIOBM) 167 xfer->c_flags |= C_PIOBM; 168 #endif 169 xfer->c_drive = drvp->drive; 170 xfer->c_databuf = ata_bio->databuf; 171 xfer->c_bcount = ata_bio->bcount; 172 xfer->ops = &wdc_bio_xfer_ops; 173 ata_exec_xfer(chp, xfer); 174 } 175 176 static int 177 wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 178 { 179 struct atac_softc *atac = chp->ch_atac; 180 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 181 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 182 struct ata_bio *ata_bio = &xfer->c_bio; 183 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 184 int wait_flags, tfd; 185 const char *errstring; 186 #ifdef WDC_NO_IDS 187 wait_flags = AT_POLL; 188 #else 189 wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 190 #endif 191 192 ATADEBUG_PRINT(("wdc_ata_bio_start %s:%d:%d state %d drive_flags 0x%x " 193 "c_flags 0x%x ch_flags 0x%x\n", 194 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 195 drvp->state, drvp->drive_flags, xfer->c_flags, chp->ch_flags), 196 DEBUG_XFERS); 197 198 ata_channel_lock_owned(chp); 199 200 /* Do control operations specially. */ 201 if (__predict_false(drvp->state < READY)) { 202 /* 203 * Actually, we want to be careful not to mess with the control 204 * state if the device is currently busy, but we can assume 205 * that we never get to this point if that's the case. 206 */ 207 /* If it's not a polled command, we need the kernel thread */ 208 if ((xfer->c_flags & C_POLL) == 0 && !ata_is_thread_run(chp)) 209 return ATASTART_TH; 210 211 /* 212 * disable interrupts, all commands here should be quick 213 * enough to be able to poll, and we don't go here that often 214 */ 215 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 216 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 217 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 218 if (wdc->select) 219 wdc->select(chp, xfer->c_drive); 220 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 221 WDSD_IBM | (xfer->c_drive << 4)); 222 DELAY(10); 223 errstring = "wait"; 224 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 225 &tfd)) 226 goto ctrltimeout; 227 wdccommandshort(chp, xfer->c_drive, WDCC_RECAL); 228 /* Wait for at last 400ns for status bit to be valid */ 229 DELAY(1); 230 errstring = "recal"; 231 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 232 &tfd)) 233 goto ctrltimeout; 234 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 235 goto ctrlerror; 236 /* Don't try to set modes if controller can't be adjusted */ 237 if (atac->atac_set_modes == NULL) 238 goto geometry; 239 /* Also don't try if the drive didn't report its mode */ 240 if ((drvp->drive_flags & ATA_DRIVE_MODE) == 0) 241 goto geometry; 242 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 243 0x08 | drvp->PIO_mode, WDSF_SET_MODE); 244 errstring = "piomode"; 245 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 246 &tfd)) 247 goto ctrltimeout; 248 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 249 goto ctrlerror; 250 #if NATA_DMA 251 #if NATA_UDMA 252 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 253 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 254 0x40 | drvp->UDMA_mode, WDSF_SET_MODE); 255 } else 256 #endif 257 if (drvp->drive_flags & ATA_DRIVE_DMA) { 258 wdccommand(chp, drvp->drive, SET_FEATURES, 0, 0, 0, 259 0x20 | drvp->DMA_mode, WDSF_SET_MODE); 260 } else { 261 goto geometry; 262 } 263 errstring = "dmamode"; 264 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 265 &tfd)) 266 goto ctrltimeout; 267 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 268 goto ctrlerror; 269 #endif /* NATA_DMA */ 270 geometry: 271 if (ata_bio->flags & ATA_LBA) 272 goto multimode; 273 wdccommand(chp, xfer->c_drive, WDCC_IDP, 274 drvp->lp->d_ncylinders, 275 drvp->lp->d_ntracks - 1, 0, drvp->lp->d_nsectors, 276 (drvp->lp->d_type == DKTYPE_ST506) ? 277 drvp->lp->d_precompcyl / 4 : 0); 278 errstring = "geometry"; 279 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 280 &tfd)) 281 goto ctrltimeout; 282 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 283 goto ctrlerror; 284 multimode: 285 if (drvp->multi == 1) 286 goto ready; 287 wdccommand(chp, xfer->c_drive, WDCC_SETMULTI, 0, 0, 0, 288 drvp->multi, 0); 289 errstring = "setmulti"; 290 if (wdcwait(chp, WDCS_DRDY, WDCS_DRDY, ATA_DELAY, wait_flags, 291 &tfd)) 292 goto ctrltimeout; 293 if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF)) 294 goto ctrlerror; 295 ready: 296 drvp->state = READY; 297 /* 298 * The drive is usable now 299 */ 300 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 301 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 302 wd_aux_ctlr, WDCTL_4BIT); 303 delay(10); /* some drives need a little delay here */ 304 } 305 306 return _wdc_ata_bio_start(chp, xfer); 307 ctrltimeout: 308 printf("%s:%d:%d: %s timed out\n", 309 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 310 errstring); 311 ata_bio->error = TIMEOUT; 312 goto ctrldone; 313 ctrlerror: 314 printf("%s:%d:%d: %s ", 315 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 316 errstring); 317 if (ATACH_ST(tfd) & WDCS_DWF) { 318 printf("drive fault\n"); 319 ata_bio->error = ERR_DF; 320 } else { 321 ata_bio->r_error = ATACH_ERR(tfd); 322 ata_bio->error = ERROR; 323 printf("error (%x)\n", ata_bio->r_error); 324 } 325 ctrldone: 326 drvp->state = 0; 327 328 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 329 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 330 WDCTL_4BIT); 331 return ATASTART_ABORT; 332 } 333 334 static int 335 _wdc_ata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 336 { 337 struct atac_softc *atac = chp->ch_atac; 338 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 339 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 340 struct ata_bio *ata_bio = &xfer->c_bio; 341 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 342 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 343 uint16_t cyl; 344 uint8_t head, sect, cmd = 0; 345 int nblks, tfd; 346 #if NATA_DMA || NATA_PIOBM 347 int error, dma_flags = 0; 348 #endif 349 350 ATADEBUG_PRINT(("_wdc_ata_bio_start %s:%d:%d\n", 351 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 352 DEBUG_INTR | DEBUG_XFERS); 353 354 #if NATA_DMA || NATA_PIOBM 355 if (xfer->c_flags & (C_DMA | C_PIOBM)) { 356 #if NATA_DMA 357 if (drvp->n_xfers <= NXFER) 358 drvp->n_xfers++; 359 #endif 360 dma_flags = (ata_bio->flags & ATA_READ) ? WDC_DMA_READ : 0; 361 if (ata_bio->flags & ATA_LBA48) 362 dma_flags |= WDC_DMA_LBA48; 363 } 364 #endif 365 /* 366 * When starting a multi-sector transfer, or doing single-sector 367 * transfers... 368 */ 369 if (xfer->c_skip == 0 || (ata_bio->flags & ATA_SINGLE) != 0) { 370 int i, distance; 371 372 if (ata_bio->flags & ATA_SINGLE) 373 nblks = 1; 374 else 375 nblks = xfer->c_bcount / drvp->lp->d_secsize; 376 /* Check for bad sectors and adjust transfer, if necessary. */ 377 if (drvp->bad144 != NULL && 378 (i = bad144_isbad_lba(drvp->bad144, 379 ata_bio->blkno, nblks, 380 &distance)) != -1) { 381 /* 382 * The bad block appears somewhere in this 383 * transfer, so degrade to single-sector mode. 384 */ 385 ata_bio->flags |= ATA_SINGLE; 386 nblks = 1; 387 if (distance == 0) { 388 /* Replace current block of transfer. */ 389 ata_bio->blkno = 390 drvp->lp->d_secperunit - 391 drvp->lp->d_nsectors - i - 1; 392 } 393 } 394 if (ata_bio->flags & ATA_LBA48) { 395 sect = 0; 396 cyl = 0; 397 head = 0; 398 } else if (ata_bio->flags & ATA_LBA) { 399 sect = (ata_bio->blkno >> 0) & 0xff; 400 cyl = (ata_bio->blkno >> 8) & 0xffff; 401 head = (ata_bio->blkno >> 24) & 0x0f; 402 head |= WDSD_LBA; 403 } else { 404 int blkno = ata_bio->blkno; 405 sect = blkno % drvp->lp->d_nsectors; 406 sect++; /* Sectors begin with 1, not 0. */ 407 blkno /= drvp->lp->d_nsectors; 408 head = blkno % drvp->lp->d_ntracks; 409 blkno /= drvp->lp->d_ntracks; 410 cyl = blkno; 411 head |= WDSD_CHS; 412 } 413 #if NATA_DMA 414 if (xfer->c_flags & C_DMA) { 415 uint16_t count = nblks, features = 0; 416 417 ata_bio->nblks = nblks; 418 ata_bio->nbytes = xfer->c_bcount; 419 cmd = (ata_bio->flags & ATA_READ) ? 420 WDCC_READDMA : WDCC_WRITEDMA; 421 /* Init the DMA channel. */ 422 error = (*wdc->dma_init)(wdc->dma_arg, 423 chp->ch_channel, xfer->c_drive, 424 (char *)xfer->c_databuf + xfer->c_skip, 425 ata_bio->nbytes, dma_flags); 426 if (error) { 427 if (error == EINVAL) { 428 /* 429 * We can't do DMA on this transfer 430 * for some reason. Fall back to 431 * PIO. 432 */ 433 xfer->c_flags &= ~C_DMA; 434 error = 0; 435 goto do_pio; 436 } 437 ata_bio->error = ERR_DMA; 438 ata_bio->r_error = 0; 439 return ATASTART_ABORT; 440 } 441 /* Initiate command */ 442 if (wdc->select) 443 wdc->select(chp, xfer->c_drive); 444 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 445 0, WDSD_IBM | (xfer->c_drive << 4)); 446 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, 447 &tfd)) { 448 case WDCWAIT_OK: 449 break; 450 case WDCWAIT_TOUT: 451 goto timeout; 452 case WDCWAIT_THR: 453 return ATASTART_TH; 454 } 455 /* start the DMA channel before */ 456 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) != 0) 457 (*wdc->dma_start)(wdc->dma_arg, 458 chp->ch_channel, xfer->c_drive); 459 if (ata_bio->flags & ATA_LBA48) { 460 uint8_t device = WDSD_LBA; 461 cmd = atacmd_to48(cmd); 462 463 atacmd_toncq(xfer, &cmd, &count, &features, 464 &device); 465 466 wdccommandext(chp, xfer->c_drive, cmd, 467 ata_bio->blkno, count, features, device); 468 } else { 469 wdccommand(chp, xfer->c_drive, cmd, cyl, 470 head, sect, count, features); 471 } 472 /* start the DMA channel after */ 473 if ((chp->ch_flags & ATACH_DMA_BEFORE_CMD) == 0) 474 (*wdc->dma_start)(wdc->dma_arg, 475 chp->ch_channel, xfer->c_drive); 476 chp->ch_flags |= ATACH_DMA_WAIT; 477 /* wait for irq */ 478 goto intr; 479 } /* else not DMA */ 480 do_pio: 481 #endif /* NATA_DMA */ 482 #if NATA_PIOBM 483 if ((xfer->c_flags & C_PIOBM) && xfer->c_skip == 0) { 484 if (ata_bio->flags & ATA_POLL) { 485 /* XXX not supported yet --- fall back to PIO */ 486 xfer->c_flags &= ~C_PIOBM; 487 } else { 488 /* Init the DMA channel. */ 489 error = (*wdc->dma_init)(wdc->dma_arg, 490 chp->ch_channel, xfer->c_drive, 491 (char *)xfer->c_databuf + xfer->c_skip, 492 xfer->c_bcount, 493 dma_flags | WDC_DMA_PIOBM_ATA); 494 if (error) { 495 if (error == EINVAL) { 496 /* 497 * We can't do DMA on this 498 * transfer for some reason. 499 * Fall back to PIO. 500 */ 501 xfer->c_flags &= ~C_PIOBM; 502 error = 0; 503 } else { 504 ata_bio->error = ERR_DMA; 505 ata_bio->r_error = 0; 506 return ATASTART_ABORT; 507 } 508 } 509 } 510 } 511 #endif 512 ata_bio->nblks = uimin(nblks, drvp->multi); 513 ata_bio->nbytes = ata_bio->nblks * drvp->lp->d_secsize; 514 KASSERT(nblks == 1 || (ata_bio->flags & ATA_SINGLE) == 0); 515 if (ata_bio->nblks > 1) { 516 cmd = (ata_bio->flags & ATA_READ) ? 517 WDCC_READMULTI : WDCC_WRITEMULTI; 518 } else { 519 cmd = (ata_bio->flags & ATA_READ) ? 520 WDCC_READ : WDCC_WRITE; 521 } 522 /* Initiate command! */ 523 if (wdc->select) 524 wdc->select(chp, xfer->c_drive); 525 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 526 WDSD_IBM | (xfer->c_drive << 4)); 527 switch(wdc_wait_for_ready(chp, ATA_DELAY, wait_flags, &tfd)) { 528 case WDCWAIT_OK: 529 break; 530 case WDCWAIT_TOUT: 531 goto timeout; 532 case WDCWAIT_THR: 533 return ATASTART_TH; 534 } 535 if (ata_bio->flags & ATA_LBA48) { 536 wdccommandext(chp, xfer->c_drive, atacmd_to48(cmd), 537 ata_bio->blkno, nblks, 0, WDSD_LBA); 538 } else { 539 wdccommand(chp, xfer->c_drive, cmd, cyl, 540 head, sect, nblks, 541 (drvp->lp->d_type == DKTYPE_ST506) ? 542 drvp->lp->d_precompcyl / 4 : 0); 543 } 544 } else if (ata_bio->nblks > 1) { 545 /* The number of blocks in the last stretch may be smaller. */ 546 nblks = xfer->c_bcount / drvp->lp->d_secsize; 547 if (ata_bio->nblks > nblks) { 548 ata_bio->nblks = nblks; 549 ata_bio->nbytes = xfer->c_bcount; 550 } 551 } 552 /* If this was a write and not using DMA, push the data. */ 553 if ((ata_bio->flags & ATA_READ) == 0) { 554 /* 555 * we have to busy-wait here, we can't rely on running in 556 * thread context. 557 */ 558 if (wdc_wait_for_drq(chp, ATA_DELAY, AT_POLL, &tfd) != 0) { 559 printf("%s:%d:%d: timeout waiting for DRQ, " 560 "st=0x%02x, err=0x%02x\n", 561 device_xname(atac->atac_dev), chp->ch_channel, 562 xfer->c_drive, 563 ATACH_ST(tfd), ATACH_ERR(tfd)); 564 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 565 ata_bio->error = TIMEOUT; 566 return ATASTART_ABORT; 567 } 568 if (wdc_ata_err(drvp, ata_bio, tfd) == WDC_ATA_ERR) { 569 return ATASTART_ABORT; 570 } 571 #if NATA_PIOBM 572 if (xfer->c_flags & C_PIOBM) { 573 /* start the busmastering PIO */ 574 (*wdc->piobm_start)(wdc->dma_arg, 575 chp->ch_channel, xfer->c_drive, 576 xfer->c_skip, ata_bio->nbytes, 0); 577 chp->ch_flags |= ATACH_DMA_WAIT; 578 } else 579 #endif 580 581 wdc->dataout_pio(chp, drvp->drive_flags, 582 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 583 } 584 585 #if NATA_DMA 586 intr: 587 #endif 588 /* Wait for IRQ (either real or polled) */ 589 if ((xfer->c_flags & C_POLL) == 0) { 590 /* start timeout machinery */ 591 callout_reset(&chp->c_timo_callout, 592 ATA_DELAY / 1000 * hz, wdctimeout, chp); 593 chp->ch_flags |= ATACH_IRQ_WAIT; 594 return ATASTART_STARTED; 595 } else { 596 return ATASTART_POLL; 597 } 598 599 timeout: 600 printf("%s:%d:%d: not ready, st=0x%02x, err=0x%02x\n", 601 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 602 ATACH_ST(tfd), ATACH_ERR(tfd)); 603 if (wdc_ata_err(drvp, ata_bio, tfd) != WDC_ATA_ERR) 604 ata_bio->error = TIMEOUT; 605 return ATASTART_ABORT; 606 } 607 608 static int 609 wdc_ata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 610 { 611 /* Wait for at last 400ns for status bit to be valid */ 612 delay(1); 613 #if NATA_DMA 614 if (chp->ch_flags & ATACH_DMA_WAIT) { 615 wdc_dmawait(chp, xfer, ATA_DELAY); 616 chp->ch_flags &= ~ATACH_DMA_WAIT; 617 } 618 #endif 619 wdc_ata_bio_intr(chp, xfer, 0); 620 return (xfer->c_bio.flags & ATA_ITSDONE) ? ATAPOLL_DONE : ATAPOLL_AGAIN; 621 } 622 623 static int 624 wdc_ata_bio_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 625 { 626 struct atac_softc *atac = chp->ch_atac; 627 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 628 struct ata_bio *ata_bio = &xfer->c_bio; 629 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 630 int drv_err, tfd; 631 632 ATADEBUG_PRINT(("wdc_ata_bio_intr %s:%d:%d\n", 633 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive), 634 DEBUG_INTR | DEBUG_XFERS); 635 636 ata_channel_lock(chp); 637 638 /* Is it not a transfer, but a control operation? */ 639 if (drvp->state < READY) { 640 printf("%s:%d:%d: bad state %d in wdc_ata_bio_intr\n", 641 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 642 drvp->state); 643 panic("wdc_ata_bio_intr: bad state"); 644 } 645 646 /* 647 * if we missed an interrupt in a PIO transfer, reset and restart. 648 * Don't try to continue transfer, we may have missed cycles. 649 */ 650 if ((xfer->c_flags & (C_TIMEOU | C_DMA)) == C_TIMEOU) { 651 ata_bio->error = TIMEOUT; 652 goto err; 653 } 654 655 #if NATA_PIOBM 656 /* Transfer-done interrupt for busmastering PIO read */ 657 if ((xfer->c_flags & C_PIOBM) && (chp->ch_flags & ATACH_PIOBM_WAIT)) { 658 chp->ch_flags &= ~ATACH_PIOBM_WAIT; 659 goto end; 660 } 661 #endif 662 663 /* Ack interrupt done by wdc_wait_for_unbusy */ 664 if (wdc_wait_for_unbusy(chp, 665 (irq == 0) ? ATA_DELAY : 0, AT_POLL, &tfd) < 0) { 666 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 667 ata_channel_unlock(chp); 668 return 0; /* IRQ was not for us */ 669 } 670 printf("%s:%d:%d: device timeout, c_bcount=%d, c_skip%d\n", 671 device_xname(atac->atac_dev), chp->ch_channel, 672 xfer->c_drive, xfer->c_bcount, xfer->c_skip); 673 ata_bio->error = TIMEOUT; 674 goto err; 675 } 676 if (wdc->irqack) 677 wdc->irqack(chp); 678 679 drv_err = wdc_ata_err(drvp, ata_bio, tfd); 680 681 #if NATA_DMA 682 /* If we were using DMA, Turn off the DMA channel and check for error */ 683 if (xfer->c_flags & C_DMA) { 684 if (ata_bio->flags & ATA_POLL) { 685 /* 686 * IDE drives deassert WDCS_BSY before transfer is 687 * complete when using DMA. Polling for DRQ to deassert 688 * is not enough DRQ is not required to be 689 * asserted for DMA transfers, so poll for DRDY. 690 */ 691 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 692 ATA_DELAY, ATA_POLL, &tfd) == WDCWAIT_TOUT) { 693 printf("%s:%d:%d: polled transfer timed out " 694 "(st=0x%x)\n", 695 device_xname(atac->atac_dev), 696 chp->ch_channel, xfer->c_drive, 697 ATACH_ST(tfd)); 698 ata_bio->error = TIMEOUT; 699 drv_err = WDC_ATA_ERR; 700 } 701 } 702 if (wdc->dma_status != 0) { 703 if (drv_err != WDC_ATA_ERR) { 704 ata_bio->error = ERR_DMA; 705 drv_err = WDC_ATA_ERR; 706 } 707 } 708 if (ATACH_ST(tfd) & WDCS_DRQ) { 709 if (drv_err != WDC_ATA_ERR) { 710 printf("%s:%d:%d: intr with DRQ (st=0x%x)\n", 711 device_xname(atac->atac_dev), 712 chp->ch_channel, 713 xfer->c_drive, ATACH_ST(tfd)); 714 ata_bio->error = TIMEOUT; 715 drv_err = WDC_ATA_ERR; 716 } 717 } 718 if (drv_err != WDC_ATA_ERR) 719 goto end; 720 if (ata_bio->r_error & WDCE_CRC || ata_bio->error == ERR_DMA) { 721 ata_dmaerr(drvp, 722 (xfer->c_flags & C_POLL) ? AT_POLL : 0); 723 goto err; 724 } 725 } 726 #endif /* NATA_DMA */ 727 728 /* if we had an error, end */ 729 if (drv_err == WDC_ATA_ERR) 730 goto err; 731 732 /* If this was a read and not using DMA, fetch the data. */ 733 if ((ata_bio->flags & ATA_READ) != 0) { 734 if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) { 735 printf("%s:%d:%d: read intr before drq\n", 736 device_xname(atac->atac_dev), chp->ch_channel, 737 xfer->c_drive); 738 ata_bio->error = TIMEOUT; 739 goto err; 740 } 741 #if NATA_PIOBM 742 if (xfer->c_flags & C_PIOBM) { 743 /* start the busmastering PIO */ 744 (*wdc->piobm_start)(wdc->dma_arg, 745 chp->ch_channel, xfer->c_drive, 746 xfer->c_skip, ata_bio->nbytes, 747 WDC_PIOBM_XFER_IRQ); 748 chp->ch_flags |= ATACH_DMA_WAIT | ATACH_PIOBM_WAIT; 749 ata_channel_unlock(chp); 750 return 1; 751 } 752 #endif 753 wdc->datain_pio(chp, drvp->drive_flags, 754 (char *)xfer->c_databuf + xfer->c_skip, ata_bio->nbytes); 755 } 756 757 #if NATA_DMA || NATA_PIOBM 758 end: 759 #endif 760 ata_bio->blkno += ata_bio->nblks; 761 ata_bio->blkdone += ata_bio->nblks; 762 xfer->c_skip += ata_bio->nbytes; 763 xfer->c_bcount -= ata_bio->nbytes; 764 765 /* See if this transfer is complete. */ 766 if (xfer->c_bcount > 0) { 767 if ((ata_bio->flags & ATA_POLL) == 0) { 768 /* Start the next operation */ 769 KASSERT((chp->ch_flags & ATACH_IRQ_WAIT) == 0); 770 callout_stop(&chp->c_timo_callout); 771 ata_xfer_start(xfer); 772 } else { 773 /* 774 * Let ata_xfer_start() do the loop; 775 * see wdc_ata_bio_poll(). 776 */ 777 } 778 ata_channel_unlock(chp); 779 return 1; 780 } 781 782 /* Done with this transfer */ 783 ata_bio->error = NOERROR; 784 err: ata_channel_unlock(chp); 785 wdc_ata_bio_done(chp, xfer); 786 return 1; 787 } 788 789 static void 790 wdc_ata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 791 int reason) 792 { 793 struct ata_bio *ata_bio = &xfer->c_bio; 794 int drive = xfer->c_drive; 795 bool deactivate = true; 796 797 ata_bio->flags |= ATA_ITSDONE; 798 switch (reason) { 799 case KILL_GONE_INACTIVE: 800 deactivate = false; 801 /* FALLTHROUGH */ 802 case KILL_GONE: 803 ata_bio->error = ERR_NODEV; 804 break; 805 case KILL_RESET: 806 ata_bio->error = ERR_RESET; 807 break; 808 default: 809 printf("wdc_ata_bio_kill_xfer: unknown reason %d\n", 810 reason); 811 panic("wdc_ata_bio_kill_xfer"); 812 } 813 ata_bio->r_error = WDCE_ABRT; 814 815 if (deactivate) 816 ata_deactivate_xfer(chp, xfer); 817 818 ATADEBUG_PRINT(("wdc_ata_bio_kill_xfer: drv_done\n"), DEBUG_XFERS); 819 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 820 } 821 822 static void 823 wdc_ata_bio_done(struct ata_channel *chp, struct ata_xfer *xfer) 824 { 825 struct ata_bio *ata_bio = &xfer->c_bio; 826 int drive = xfer->c_drive; 827 828 ATADEBUG_PRINT(("wdc_ata_bio_done %s:%d:%d: flags 0x%x\n", 829 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 830 xfer->c_drive, (u_int)xfer->c_flags), 831 DEBUG_XFERS); 832 833 if (ata_waitdrain_xfer_check(chp, xfer)) 834 return; 835 836 /* feed back residual bcount to our caller */ 837 ata_bio->bcount = xfer->c_bcount; 838 839 /* mark controller inactive and free xfer */ 840 ata_deactivate_xfer(chp, xfer); 841 842 ata_bio->flags |= ATA_ITSDONE; 843 ATADEBUG_PRINT(("wdc_ata_done: drv_done\n"), DEBUG_XFERS); 844 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 845 ATADEBUG_PRINT(("atastart from wdc_ata_done, flags 0x%x\n", 846 chp->ch_flags), DEBUG_XFERS); 847 atastart(chp); 848 } 849 850 static int 851 wdc_ata_err(struct ata_drive_datas *drvp, struct ata_bio *ata_bio, int tfd) 852 { 853 ata_bio->error = 0; 854 if (ATACH_ST(tfd) & WDCS_BSY) { 855 ata_bio->error = TIMEOUT; 856 return WDC_ATA_ERR; 857 } 858 859 if (ATACH_ST(tfd) & WDCS_DWF) { 860 ata_bio->error = ERR_DF; 861 return WDC_ATA_ERR; 862 } 863 864 if (ATACH_ST(tfd) & WDCS_ERR) { 865 ata_bio->error = ERROR; 866 ata_bio->r_error = ATACH_ERR(tfd); 867 if (ata_bio->r_error & (WDCE_BBK | WDCE_UNC | WDCE_IDNF | 868 WDCE_ABRT | WDCE_TK0NF | WDCE_AMNF)) 869 return WDC_ATA_ERR; 870 return WDC_ATA_NOERR; 871 } 872 873 if (ATACH_ST(tfd) & WDCS_CORR) 874 ata_bio->flags |= ATA_CORR; 875 return WDC_ATA_NOERR; 876 } 877 878 static int 879 wdc_ata_addref(struct ata_drive_datas *drvp) 880 { 881 struct ata_channel *chp = drvp->chnl_softc; 882 883 return (ata_addref(chp)); 884 } 885 886 static void 887 wdc_ata_delref(struct ata_drive_datas *drvp) 888 { 889 struct ata_channel *chp = drvp->chnl_softc; 890 891 ata_delref(chp); 892 } 893
Indexes created Sun Oct 25 00:26:45 UTC 2026