1 /* $NetBSD: am18xx_sdmmc.c,v 1.2 2026/10/18 09:17:08 yurix Exp $ */ 2 3 /*- 4 * Copyright (c) 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Yuri Honegger. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the sd card port on the TI AM18XX. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/cdefs.h> 39 #include <sys/device.h> 40 #include <sys/mutex.h> 41 42 #include <dev/fdt/fdtvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmcreg.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 struct am18xx_sdmmc_softc { 48 /* bus_space io */ 49 bus_space_tag_t sc_bst; 50 bus_space_handle_t sc_bsh; 51 52 device_t sc_dev; 53 device_t sc_sdmmc; 54 55 /* driver internals */ 56 kmutex_t sc_lock; 57 kcondvar_t sc_intr_cv; 58 struct sdmmc_command *sc_cmd; 59 struct clk *sc_clk; 60 61 /* edma */ 62 bus_addr_t sc_phys_base_addr; 63 struct fdtbus_dma *sc_rx_dma; 64 struct fdtbus_dma *sc_tx_dma; 65 struct fdtbus_dma_req sc_dma_req; 66 67 /* status flags */ 68 bool sc_irq_wait; 69 bool sc_command_done; 70 bool sc_transfer_done; 71 bool sc_dma_done; 72 bool sc_opendrain; 73 bool sc_firstcmd; 74 bool sc_use_dma; 75 bool sc_have_dma; 76 }; 77 78 static int am18xx_sdmmc_match(device_t, cfdata_t, void *); 79 static void am18xx_sdmmc_attach(device_t, device_t, void *); 80 static void am18xx_sdmmc_init(struct am18xx_sdmmc_softc *); 81 static int am18xx_sdmmc_host_reset(sdmmc_chipset_handle_t); 82 static uint32_t am18xx_sdmmc_host_ocr(sdmmc_chipset_handle_t); 83 static int am18xx_sdmmc_host_maxblklen(sdmmc_chipset_handle_t); 84 static int am18xx_sdmmc_card_detect(sdmmc_chipset_handle_t); 85 static int am18xx_sdmmc_write_protect(sdmmc_chipset_handle_t); 86 static int am18xx_sdmmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 87 static int am18xx_sdmmc_bus_clock(sdmmc_chipset_handle_t, int); 88 static int am18xx_sdmmc_bus_width(sdmmc_chipset_handle_t, int); 89 static int am18xx_sdmmc_bus_rod(sdmmc_chipset_handle_t, int); 90 static void am18xx_sdmmc_exec_command(sdmmc_chipset_handle_t, 91 struct sdmmc_command *); 92 static int am18xx_sdmmc_initiate_command(struct am18xx_sdmmc_softc *, 93 struct sdmmc_command *); 94 static void am18xx_sdmmc_check_completion(struct am18xx_sdmmc_softc *, 95 bool); 96 static void am18xx_sdmmc_card_enable_intr(sdmmc_chipset_handle_t, int); 97 static void am18xx_sdmmc_card_intr_ack(sdmmc_chipset_handle_t); 98 static void am18xx_sdmmc_cpu_data_transfer(struct am18xx_sdmmc_softc *sc); 99 static int am18xx_sdmmc_intr(void *); 100 static void am18xx_sdmmc_dma_callback(void *priv); 101 102 #define SDMMC_READ(sc, reg) \ 103 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg) 104 #define SDMMC_WRITE(sc, reg, val) \ 105 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val) 106 107 #define AM18XX_SDMMC_MMCCTL 0x0 108 #define AM18XX_SDMMC_MMCCLK 0x4 109 #define AM18XX_SDMMC_MMCST0 0x8 110 #define AM18XX_SDMMC_MMCST1 0xC 111 #define AM18XX_SDMMC_MMCIM 0x10 112 #define AM18XX_SDMMC_MMCTOR 0x14 113 #define AM18XX_SDMMC_MMCTOD 0x18 114 #define AM18XX_SDMMC_MMCBLEN 0x1C 115 #define AM18XX_SDMMC_MMCNBLK 0x20 116 #define AM18XX_SDMMC_MMCDRR 0x28 117 #define AM18XX_SDMMC_MMCDXR 0x2C 118 #define AM18XX_SDMMC_MMCCMD 0x30 119 #define AM18XX_SDMMC_MMCARGHL 0x34 120 #define AM18XX_SDMMC_MMCRSP01 0x38 121 #define AM18XX_SDMMC_MMCRSP23 0x3C 122 #define AM18XX_SDMMC_MMCRSP45 0x40 123 #define AM18XX_SDMMC_MMCRSP67 0x44 124 #define AM18XX_SDMMC_FIFOCTL 0x74 125 126 #define AM18XX_SDMMC_MMCCTL_DATARST __BIT(0) 127 #define AM18XX_SDMMC_MMCCTL_CMDRST __BIT(1) 128 #define AM18XX_SDMMC_MMCCTL_WIDTH0 __BIT(2) 129 #define AM18XX_SDMMC_MMCCTL_DATEG __BITS(7,6) 130 #define AM18XX_SDMMC_MMCCTL_WIDTH1 __BIT(8) 131 #define AM18XX_SDMMC_MMCCTL_PERMDR __BIT(9) 132 #define AM18XX_SDMMC_MMCCTL_PERMDX __BIT(10) 133 134 #define AM18XX_SDMMC_MMCCLK_CLKRT __BITS(7,0) 135 #define AM18XX_SDMMC_MMCCLK_CLKEN __BIT(8) 136 #define AM18XX_SDMMC_MMCCLK_DIV4 __BIT(9) 137 138 #define AM18XX_SDMMC_MMCST0_DATDNE __BIT(0) 139 #define AM18XX_SDMMC_MMCST0_BSYDNE __BIT(1) 140 #define AM18XX_SDMMC_MMCST0_RSPDNE __BIT(2) 141 #define AM18XX_SDMMC_MMCST0_TOUTRD __BIT(3) 142 #define AM18XX_SDMMC_MMCST0_TOUTRS __BIT(4) 143 #define AM18XX_SDMMC_MMCST0_CRCWR __BIT(5) 144 #define AM18XX_SDMMC_MMCST0_CRCRD __BIT(6) 145 #define AM18XX_SDMMC_MMCST0_CRCRS __BIT(7) 146 #define AM18XX_SDMMC_MMCST0_DXRDY __BIT(9) 147 #define AM18XX_SDMMC_MMCST0_DRRDY __BIT(10) 148 #define AM18XX_SDMMC_MMCST0_TRNDNE __BIT(12) 149 150 #define AM18XX_SDMMC_MMCST0_ERRMASK (AM18XX_SDMMC_MMCST0_TOUTRD | \ 151 AM18XX_SDMMC_MMCST0_TOUTRS | \ 152 AM18XX_SDMMC_MMCST0_CRCWR | \ 153 AM18XX_SDMMC_MMCST0_CRCRD | \ 154 AM18XX_SDMMC_MMCST0_CRCRS) 155 156 #define AM18XX_SDMMC_MMCST1_BUSY __BIT(0) 157 158 #define AM18XX_SDMMC_MMCIM_EDATDNE __BIT(0) 159 #define AM18XX_SDMMC_MMCIM_ERSPDNE __BIT(2) 160 #define AM18XX_SDMMC_MMCIM_ETOUTRD __BIT(3) 161 #define AM18XX_SDMMC_MMCIM_ETOUTRS __BIT(4) 162 #define AM18XX_SDMMC_MMCIM_ECRCWR __BIT(5) 163 #define AM18XX_SDMMC_MMCIM_ECRCRD __BIT(6) 164 #define AM18XX_SDMMC_MMCIM_ECRCRS __BIT(7) 165 #define AM18XX_SDMMC_MMCIM_EDXRDY __BIT(9) 166 #define AM18XX_SDMMC_MMCIM_EDRRDY __BIT(10) 167 168 #define AM18XX_SDMMC_MMCCMD_CMD __BITS(5,0) 169 #define AM18XX_SDMMC_MMCCMD_PPLEN __BIT(7) 170 #define AM18XX_SDMMC_MMCCMD_BSYEXP __BIT(8) 171 #define AM18XX_SDMMC_MMCCMD_RSPFMT __BITS(10,9) 172 #define AM18XX_SDMMC_MMCCMD_DTRW __BIT(11) 173 #define AM18XX_SDMMC_MMCCMD_WDATX __BIT(13) 174 #define AM18XX_SDMMC_MMCCMD_INITCK __BIT(14) 175 #define AM18XX_SDMMC_MMCCMD_DMATRIG __BIT(16) 176 177 #define AM18XX_SDMMC_MMCCMD_RSPFMT_R0 0 178 #define AM18XX_SDMMC_MMCCMD_RSPFMT_R1456 1 179 #define AM18XX_SDMMC_MMCCMD_RSPFMT_R2 2 180 #define AM18XX_SDMMC_MMCCMD_RSPFMT_R3 3 181 182 #define AM18XX_SDMMC_FIFOCTL_FIFORST __BIT(0) 183 #define AM18XX_SDMMC_FIFOCTL_FIFODIRW __BIT(1) 184 #define AM18XX_SDMMC_FIFOCTL_FIFOLEV64 __BIT(2) 185 186 #define AM18XX_SDMMC_MAX_CLOCK_DIVIDER (2 * (0xFF + 1)) 187 #define AM18XX_SDMMC_MIN_CLOCK_DIVIDER (2 * (0x00 + 1)) 188 189 CFATTACH_DECL_NEW(am18xxsdmmc, sizeof(struct am18xx_sdmmc_softc), 190 am18xx_sdmmc_match, am18xx_sdmmc_attach, NULL, NULL); 191 192 static const struct device_compatible_entry compat_data[] = { 193 {.compat = "ti,da830-mmc"}, DEVICE_COMPAT_EOL}; 194 195 static struct sdmmc_chip_functions am18xx_sdmmc_functions = { 196 .host_reset = am18xx_sdmmc_host_reset, 197 .host_ocr = am18xx_sdmmc_host_ocr, 198 .host_maxblklen = am18xx_sdmmc_host_maxblklen, 199 .card_detect = am18xx_sdmmc_card_detect, 200 .write_protect = am18xx_sdmmc_write_protect, 201 .bus_power = am18xx_sdmmc_bus_power, 202 .bus_clock = am18xx_sdmmc_bus_clock, 203 .bus_width = am18xx_sdmmc_bus_width, 204 .bus_rod = am18xx_sdmmc_bus_rod, 205 .exec_command = am18xx_sdmmc_exec_command, 206 .card_enable_intr = am18xx_sdmmc_card_enable_intr, 207 .card_intr_ack = am18xx_sdmmc_card_intr_ack 208 }; 209 210 static int 211 am18xx_sdmmc_host_reset(sdmmc_chipset_handle_t sch) 212 { 213 struct am18xx_sdmmc_softc *sc = sch; 214 215 am18xx_sdmmc_init(sc); 216 217 return 0; 218 } 219 220 static uint32_t 221 am18xx_sdmmc_host_ocr(sdmmc_chipset_handle_t sch) 222 { 223 return MMC_OCR_3_2V_3_3V; 224 } 225 226 static int 227 am18xx_sdmmc_host_maxblklen(sdmmc_chipset_handle_t sch) 228 { 229 return 2048; 230 } 231 232 static int 233 am18xx_sdmmc_card_detect(sdmmc_chipset_handle_t sch) 234 { 235 return 1; 236 } 237 238 static int 239 am18xx_sdmmc_write_protect(sdmmc_chipset_handle_t sch) 240 { 241 return 0; 242 } 243 244 static int 245 am18xx_sdmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 246 { 247 /* do nothing */ 248 return 0; 249 } 250 251 static int 252 am18xx_sdmmc_bus_clock(sdmmc_chipset_handle_t sch, int clock) 253 { 254 struct am18xx_sdmmc_softc *sc = sch; 255 256 if (clock > 0) { 257 int ref_clk = clk_get_rate(sc->sc_clk); 258 259 /* calculate divider */ 260 int divider = (ref_clk / (2 * 1000 * clock)) - 1; 261 if (divider < 0) { 262 divider = 0; 263 } 264 265 /* round divider */ 266 int effective_rate = ref_clk / (2 * (divider + 1)); 267 if (effective_rate > clock * 1000) { 268 divider++; 269 } 270 if (divider > 255) { 271 divider = 255; 272 } 273 274 device_printf(sc->sc_dev, "requested %d Hz, using %d Hz\n", 275 1000 * clock, ref_clk / (2 * (divider + 1))); 276 277 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCCLK, 278 divider | AM18XX_SDMMC_MMCCLK_CLKEN); 279 } else { 280 device_printf(sc->sc_dev, "clocks off\n"); 281 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCCLK, 0); 282 } 283 284 return 0; 285 } 286 287 static int 288 am18xx_sdmmc_bus_width(sdmmc_chipset_handle_t sch, int width) 289 { 290 struct am18xx_sdmmc_softc *sc = sch; 291 292 /* compute bit flags for new width */ 293 uint32_t val; 294 switch (width) { 295 case 1: 296 val = 0; 297 break; 298 case 4: 299 val = AM18XX_SDMMC_MMCCTL_WIDTH0; 300 break; 301 case 8: 302 val = AM18XX_SDMMC_MMCCTL_WIDTH1; 303 break; 304 default: 305 return 1; 306 } 307 308 /* change bus bit width bits in MMCCTL */ 309 uint32_t regval = SDMMC_READ(sc, AM18XX_SDMMC_MMCCTL); 310 regval = val | (regval & (~(AM18XX_SDMMC_MMCCTL_WIDTH0 | 311 AM18XX_SDMMC_MMCCTL_WIDTH1))); 312 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCCTL, regval); 313 314 return 0; 315 } 316 317 static int 318 am18xx_sdmmc_bus_rod(sdmmc_chipset_handle_t sch, int rod) 319 { 320 struct am18xx_sdmmc_softc *sc = sch; 321 322 mutex_enter(&sc->sc_lock); 323 if (rod) { 324 sc->sc_opendrain = true; 325 } else { 326 sc->sc_opendrain = false; 327 } 328 mutex_exit(&sc->sc_lock); 329 330 return 0; 331 } 332 333 static void 334 am18xx_sdmmc_card_enable_intr(sdmmc_chipset_handle_t sch, int irq) 335 { 336 struct am18xx_sdmmc_softc *sc = sch; 337 device_printf(sc->sc_dev, "SDIO interrupts not implemented\n"); 338 } 339 340 static void 341 am18xx_sdmmc_card_intr_ack(sdmmc_chipset_handle_t sch) 342 { 343 struct am18xx_sdmmc_softc *sc = sch; 344 device_printf(sc->sc_dev, "SDIO interrupts not implemented\n"); 345 } 346 347 static void 348 am18xx_sdmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 349 { 350 struct am18xx_sdmmc_softc *sc = sch; 351 int err; 352 353 mutex_enter(&sc->sc_lock); 354 KASSERT(sc->sc_cmd == NULL); 355 sc->sc_cmd = cmd; 356 357 /* wait for the card to be ready */ 358 int timeout = 1000000; 359 while (SDMMC_READ(sc, AM18XX_SDMMC_MMCST1) & AM18XX_SDMMC_MMCST1_BUSY) { 360 delay(10); 361 if (timeout-- == 0) { 362 device_printf(sc->sc_dev, "mmcst1 timeout\n"); 363 cmd->c_error = ETIMEDOUT; 364 goto out; 365 } 366 } 367 368 /* send the command to the controller */ 369 err = am18xx_sdmmc_initiate_command(sc, cmd); 370 if (err != 0) { 371 cmd->c_error = err; 372 goto out; 373 } 374 375 /* wait for a response */ 376 err = 0; 377 while (sc->sc_irq_wait) { 378 err = cv_timedwait(&sc->sc_intr_cv, &sc->sc_lock, mstohz(1000)); 379 if (err == EWOULDBLOCK) { 380 device_printf(sc->sc_dev, "command timeout\n"); 381 cmd->c_error = ETIMEDOUT; 382 break; 383 } 384 } 385 sc->sc_irq_wait = false; 386 387 /* 388 * Signal the DMA controller we are done. For some reason, the HW also 389 * generates DMA events for PIO transfers, meaning we also have to 390 * signal the DMA controller after a PIO transfer when DMA is available. 391 */ 392 if (sc->sc_rx_dma != NULL && ISSET(cmd->c_flags, SCF_CMD_READ)) { 393 fdtbus_dma_halt(sc->sc_rx_dma); 394 } else if (sc->sc_tx_dma != NULL) { 395 fdtbus_dma_halt(sc->sc_tx_dma); 396 } 397 398 if (cmd->c_error) { 399 goto out; 400 } 401 402 /* read the command response */ 403 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 404 if (cmd->c_flags & SCF_RSP_136) { 405 cmd->c_resp[3] = SDMMC_READ(sc, AM18XX_SDMMC_MMCRSP67); 406 cmd->c_resp[2] = SDMMC_READ(sc, AM18XX_SDMMC_MMCRSP45); 407 cmd->c_resp[1] = SDMMC_READ(sc, AM18XX_SDMMC_MMCRSP23); 408 cmd->c_resp[0] = SDMMC_READ(sc, AM18XX_SDMMC_MMCRSP01); 409 410 cmd->c_resp[0] >>= 8; /* Remove CRC7 + LSB. */ 411 cmd->c_resp[0] |= (0x000000FF & cmd->c_resp[1]) << 24; 412 cmd->c_resp[1] >>= 8; 413 cmd->c_resp[1] |= (0x000000FF & cmd->c_resp[2]) << 24; 414 cmd->c_resp[2] >>= 8; 415 cmd->c_resp[2] |= (0x000000FF & cmd->c_resp[3]) << 24; 416 cmd->c_resp[3] >>= 8; 417 } else { 418 cmd->c_resp[0] = SDMMC_READ(sc, AM18XX_SDMMC_MMCRSP67); 419 } 420 } 421 422 sc->sc_firstcmd = false; 423 out: 424 sc->sc_cmd = NULL; 425 mutex_exit(&sc->sc_lock); 426 } 427 428 static int am18xx_sdmmc_initiate_command(struct am18xx_sdmmc_softc *sc, 429 struct sdmmc_command *cmd) 430 { 431 sc->sc_use_dma = cmd->c_data != NULL && cmd->c_datalen >= 64 && 432 sc->sc_have_dma; 433 434 /* write block size settings */ 435 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCBLEN, cmd->c_blklen); 436 if (cmd->c_blklen != 0) { 437 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCNBLK, 438 cmd->c_datalen / cmd->c_blklen); 439 } else { 440 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCNBLK, 0); 441 } 442 443 /* write command */ 444 uint32_t command = __SHIFTIN(cmd->c_opcode, AM18XX_SDMMC_MMCCMD_CMD); 445 uint32_t command_type; 446 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 447 /* no response */ 448 command_type = AM18XX_SDMMC_MMCCMD_RSPFMT_R0; 449 } else if (ISSET(cmd->c_flags, SCF_RSP_136)) { 450 /* 136 bits, CRC */ 451 command_type = AM18XX_SDMMC_MMCCMD_RSPFMT_R2; 452 } else if (ISSET(cmd->c_flags, SCF_RSP_CRC)) { 453 /* 48 bits, CRC */ 454 command_type = AM18XX_SDMMC_MMCCMD_RSPFMT_R1456; 455 } else { 456 /* 48 bits, no CRC */ 457 command_type = AM18XX_SDMMC_MMCCMD_RSPFMT_R3; 458 } 459 command |= __SHIFTIN(command_type, AM18XX_SDMMC_MMCCMD_RSPFMT); 460 if (sc->sc_opendrain) { 461 command |= AM18XX_SDMMC_MMCCMD_PPLEN; 462 } 463 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) { 464 command |= AM18XX_SDMMC_MMCCMD_BSYEXP; 465 } 466 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 467 command |= AM18XX_SDMMC_MMCCMD_DTRW; 468 } 469 if (cmd->c_data != NULL && cmd->c_datalen > 0) { 470 /* command has data transfer */ 471 command |= AM18XX_SDMMC_MMCCMD_WDATX; 472 command |= AM18XX_SDMMC_MMCCMD_DMATRIG; 473 } 474 if (sc->sc_firstcmd) { 475 command |= AM18XX_SDMMC_MMCCMD_INITCK; 476 } 477 478 /* configure FIFO register */ 479 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 480 /* read */ 481 SDMMC_WRITE(sc, AM18XX_SDMMC_FIFOCTL, 482 AM18XX_SDMMC_FIFOCTL_FIFOLEV64 | 483 AM18XX_SDMMC_FIFOCTL_FIFORST); 484 SDMMC_WRITE(sc, AM18XX_SDMMC_FIFOCTL, 485 AM18XX_SDMMC_FIFOCTL_FIFOLEV64); 486 } else { 487 /* write */ 488 SDMMC_WRITE(sc, AM18XX_SDMMC_FIFOCTL, 489 AM18XX_SDMMC_FIFOCTL_FIFOLEV64 | 490 AM18XX_SDMMC_FIFOCTL_FIFODIRW | 491 AM18XX_SDMMC_FIFOCTL_FIFORST); 492 SDMMC_WRITE(sc, AM18XX_SDMMC_FIFOCTL, 493 AM18XX_SDMMC_FIFOCTL_FIFOLEV64 | 494 AM18XX_SDMMC_FIFOCTL_FIFODIRW); 495 } 496 497 sc->sc_command_done = false; 498 sc->sc_transfer_done = cmd->c_datalen == 0 || cmd->c_data == NULL; 499 sc->sc_dma_done = !sc->sc_use_dma; 500 501 if (sc->sc_use_dma) { 502 cmd->c_resid = 0; 503 504 /* data access is a multiple of fifo size */ 505 KASSERT((cmd->c_datalen & 0x3f) == 0); 506 /* transfer needs to be bigger than the FIFO size */ 507 KASSERT(cmd->c_datalen >= 64); 508 509 /* initiate DMA transfer */ 510 sc->sc_dma_req.dreq_segs = cmd->c_dmamap->dm_segs; 511 sc->sc_dma_req.dreq_nsegs = cmd->c_dmamap->dm_nsegs; 512 513 int err; 514 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 515 sc->sc_dma_req.dreq_dev_phys = 516 sc->sc_phys_base_addr + AM18XX_SDMMC_MMCDRR; 517 sc->sc_dma_req.dreq_dir = FDT_DMA_READ; 518 err = fdtbus_dma_transfer(sc->sc_rx_dma, 519 &sc->sc_dma_req); 520 } else { 521 sc->sc_dma_req.dreq_dev_phys = 522 sc->sc_phys_base_addr + AM18XX_SDMMC_MMCDXR; 523 sc->sc_dma_req.dreq_dir = FDT_DMA_WRITE; 524 err = fdtbus_dma_transfer(sc->sc_tx_dma, 525 &sc->sc_dma_req); 526 } 527 528 if (err) { 529 return err; 530 } 531 532 } else if (cmd->c_data != NULL) { 533 /* transfer size must be multiple of fifo port width */ 534 KASSERT((cmd->c_datalen & 0x3) == 0); 535 536 cmd->c_buf = cmd->c_data; 537 cmd->c_resid = cmd->c_datalen; 538 539 /* writes: shovel first load of data */ 540 if (!ISSET(cmd->c_flags, SCF_CMD_READ) && cmd->c_datalen > 0) { 541 am18xx_sdmmc_cpu_data_transfer(sc); 542 } 543 } 544 545 /* write command arguments */ 546 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCTOR, 0x1FFF); 547 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCARGHL, cmd->c_arg); 548 549 /* send the command */ 550 sc->sc_irq_wait = true; 551 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCCMD, command); 552 553 return 0; 554 } 555 556 static void am18xx_sdmmc_init(struct am18xx_sdmmc_softc *sc) 557 { 558 /* reset the controller */ 559 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCCTL, AM18XX_SDMMC_MMCCTL_DATARST | 560 AM18XX_SDMMC_MMCCTL_CMDRST); 561 SDMMC_READ(sc, AM18XX_SDMMC_MMCST0); 562 SDMMC_READ(sc, AM18XX_SDMMC_MMCST1); 563 delay(10); 564 565 /* clocks off */ 566 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCCLK, 0); 567 568 /* disable all interrupts */ 569 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCIM, 0); 570 /* write timeout values to maximum */ 571 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCTOR, 0x3FFFF); 572 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCTOD, 0xFFFF); 573 574 sc->sc_irq_wait = false; 575 sc->sc_opendrain = true; 576 sc->sc_firstcmd = true; 577 sc->sc_cmd = NULL; 578 579 /* take the controller out of reset */ 580 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCCTL, 0); 581 582 /* enable the clock */ 583 am18xx_sdmmc_bus_clock(sc, 400); 584 585 /* enable interrupts */ 586 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCIM, AM18XX_SDMMC_MMCIM_EDATDNE | 587 AM18XX_SDMMC_MMCIM_ERSPDNE | 588 AM18XX_SDMMC_MMCIM_ETOUTRD | 589 AM18XX_SDMMC_MMCIM_ETOUTRS | 590 AM18XX_SDMMC_MMCIM_ECRCWR | 591 AM18XX_SDMMC_MMCIM_ECRCRD | 592 AM18XX_SDMMC_MMCIM_ECRCRS | 593 AM18XX_SDMMC_MMCIM_EDXRDY | 594 AM18XX_SDMMC_MMCIM_EDRRDY); 595 } 596 597 static void 598 am18xx_sdmmc_cpu_data_transfer(struct am18xx_sdmmc_softc *sc) 599 { 600 /* process one FIFOfull of data */ 601 for (int i = 0; i < (64 / 4) && sc->sc_cmd->c_resid > 0; i++) { 602 KASSERT((sc->sc_cmd->c_resid & 0x3) == 0); 603 604 if (ISSET(sc->sc_cmd->c_flags, SCF_CMD_READ)) { 605 *((uint32_t *)sc->sc_cmd->c_buf) = SDMMC_READ( 606 sc, AM18XX_SDMMC_MMCDRR); 607 } else { 608 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCDXR, 609 *((uint32_t *)sc->sc_cmd->c_buf)); 610 } 611 612 sc->sc_cmd->c_resid -= 4; 613 sc->sc_cmd->c_buf += 4; 614 } 615 } 616 617 static int 618 am18xx_sdmmc_intr(void *arg) 619 { 620 bool cmd_failed = false; 621 struct am18xx_sdmmc_softc *sc = arg; 622 623 uint32_t cause = SDMMC_READ(sc, AM18XX_SDMMC_MMCST0); 624 if (cause == 0) 625 return 1; 626 627 mutex_enter(&sc->sc_lock); 628 629 if (!sc->sc_irq_wait) { 630 mutex_exit(&sc->sc_lock); 631 device_printf(sc->sc_dev, "spurious interrupt\n"); 632 return 1; 633 } 634 635 /* 636 * Disable interrupts during cpu transfer. This allows us to capture new 637 * interrupts and handle them in this interrupt instead of generating a 638 * second interrupt. 639 */ 640 uint32_t mmcim = SDMMC_READ(sc, AM18XX_SDMMC_MMCIM); 641 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCIM, 0); 642 643 /* 644 * 1. Service the FIFO until it is empty/full (depending on if we are 645 * reading or writing). We can complete multiple FIFO loads in one 646 * interrupts if the FIFO clears fast enough. After servicing the 647 * FIFO, am18xx_sdmmc_cpu_data_transfer checks for new interrupt 648 * requests like CRC errors or command completion events so we can 649 * deal with them without generating a second interrupt. We service 650 * the FIFO first so we can deal with these new events later on. 651 */ 652 if (cause & (AM18XX_SDMMC_MMCST0_DRRDY | AM18XX_SDMMC_MMCST0_DXRDY)) { 653 /* transfer one fido load for as long as there is space */ 654 uint32_t status = 0; 655 do { 656 am18xx_sdmmc_cpu_data_transfer(sc); 657 status = SDMMC_READ(sc, AM18XX_SDMMC_MMCST0); 658 cause |= status; 659 } while (status & (AM18XX_SDMMC_MMCST0_DRRDY 660 | AM18XX_SDMMC_MMCST0_DXRDY)); 661 } 662 663 /* 664 * 2. DATDNE indicates the data transfer is complete. If the data size 665 * is not a multiple of the FIFO, we don't get a DXRDY|DRRDY irq, 666 * but the data will be ready to transfer. 667 * This step is the second because the FIFO transfer might still 668 * generate events like CRC errors. 669 */ 670 if (cause & AM18XX_SDMMC_MMCST0_DATDNE) { 671 if (sc->sc_cmd->c_resid > 0) { 672 /* transfer remaining outstanding data */ 673 am18xx_sdmmc_cpu_data_transfer(sc); 674 cause |= SDMMC_READ(sc, AM18XX_SDMMC_MMCST0); 675 } 676 sc->sc_transfer_done = true; 677 } 678 679 /* 680 * 3. Check if any operation failed (CRC errors, timeouts). By now, all 681 * FIFO transfers that could generate new events have happened. 682 */ 683 if (cause & AM18XX_SDMMC_MMCST0_ERRMASK) { 684 if (cause & (AM18XX_SDMMC_MMCST0_TOUTRS 685 | AM18XX_SDMMC_MMCST0_TOUTRD)) { 686 sc->sc_cmd->c_error = ETIMEDOUT; 687 } else { 688 sc->sc_cmd->c_error = EIO; 689 } 690 691 cmd_failed = true; 692 } 693 694 /* 4. Check if the command has been fully transmitted. */ 695 if (cause & AM18XX_SDMMC_MMCST0_RSPDNE) { 696 sc->sc_command_done = true; 697 } 698 699 /* re-enable data receive/transmit interrupts */ 700 SDMMC_WRITE(sc, AM18XX_SDMMC_MMCIM, mmcim); 701 702 /* signal the main thread if we are done */ 703 am18xx_sdmmc_check_completion(sc, cmd_failed); 704 705 mutex_exit(&sc->sc_lock); 706 return 1; /* acknowledge IRQ */ 707 } 708 709 static void 710 am18xx_sdmmc_dma_callback(void *priv) 711 { 712 struct am18xx_sdmmc_softc *sc = priv; 713 714 /* ensure we have the lock while touching the softcore */ 715 mutex_enter(&sc->sc_lock); 716 717 sc->sc_dma_done = true; 718 am18xx_sdmmc_check_completion(sc, false); 719 720 mutex_exit(&sc->sc_lock); 721 } 722 723 static void 724 am18xx_sdmmc_check_completion(struct am18xx_sdmmc_softc *sc, bool has_err) 725 { 726 bool completed = sc->sc_command_done 727 && sc->sc_transfer_done 728 && sc->sc_dma_done; 729 730 if (completed || has_err) { 731 KASSERT(sc->sc_cmd->c_resid == 0 || has_err); 732 sc->sc_irq_wait = false; 733 cv_signal(&sc->sc_intr_cv); 734 } 735 } 736 737 int 738 am18xx_sdmmc_match(device_t parent, cfdata_t cf, void *aux) 739 { 740 struct fdt_attach_args *const faa = aux; 741 742 return of_compatible_match(faa->faa_phandle, compat_data); 743 } 744 745 void 746 am18xx_sdmmc_attach(device_t parent, device_t self, void *aux) 747 { 748 struct am18xx_sdmmc_softc *const sc = device_private(self); 749 struct fdt_attach_args *const faa = aux; 750 const int phandle = faa->faa_phandle; 751 struct sdmmcbus_attach_args saa; 752 bus_addr_t addr; 753 bus_size_t size; 754 char intrstr[128]; 755 756 sc->sc_bst = faa->faa_bst; 757 sc->sc_dev = self; 758 759 /* we need a spin mutex for intr->lwp synchronization */ 760 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 761 cv_init(&sc->sc_intr_cv, "sdmmc_intr"); 762 763 /* enable host controller clock */ 764 sc->sc_clk = fdtbus_clock_get_index(phandle, 0); 765 if (sc->sc_clk == NULL) { 766 aprint_error(": failed to get sdmmc clk\n"); 767 return; 768 } 769 if (clk_enable(sc->sc_clk) != 0) { 770 aprint_error(": failed to enable sdmmc clk\n"); 771 return; 772 } 773 u_int clk_rate = clk_get_rate(sc->sc_clk); 774 775 /* map bus space */ 776 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 777 aprint_error(": couldn't get registers\n"); 778 return; 779 } 780 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh)) { 781 aprint_error(": couldn't map registers\n"); 782 return; 783 } 784 sc->sc_phys_base_addr = addr; 785 786 /* establish interrupt */ 787 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 788 aprint_error(": failed to decode interrupt\n"); 789 return; 790 } 791 void *ih = fdtbus_intr_establish_xname(phandle, 0, IPL_SDMMC, IST_LEVEL, 792 am18xx_sdmmc_intr, sc, device_xname(self)); 793 if (ih == NULL) { 794 aprint_error(": couldn't install interrupt\n"); 795 return; 796 } 797 798 799 /* prepare DMA request */ 800 memset(&sc->sc_dma_req, 0, sizeof(sc->sc_dma_req)); 801 sc->sc_dma_req.dreq_block_irq = 1; 802 sc->sc_dma_req.dreq_block_multi = 0; 803 sc->sc_dma_req.dreq_dev_opt.opt_bus_width = 4; 804 sc->sc_dma_req.dreq_dev_opt.opt_burst_len = 64; 805 /* rx dma channels */ 806 sc->sc_rx_dma = fdtbus_dma_get(phandle, "rx", 807 am18xx_sdmmc_dma_callback, sc); 808 if (sc->sc_rx_dma == NULL) { 809 aprint_error(": couldn't get rx dma handle\n"); 810 } 811 /* tx dma channels */ 812 sc->sc_tx_dma = fdtbus_dma_get(phandle, "tx", 813 am18xx_sdmmc_dma_callback, sc); 814 if (sc->sc_tx_dma == NULL) { 815 aprint_error(": couldn't get tx dma handle\n"); 816 } 817 sc->sc_have_dma = sc->sc_rx_dma != NULL && sc->sc_tx_dma != NULL; 818 819 aprint_normal("\n"); 820 821 /* reset the controller */ 822 am18xx_sdmmc_init(sc); 823 824 /* attach us as an sdmmc device */ 825 memset(&saa, 0, sizeof(saa)); 826 saa.saa_busname = "sdmmc"; 827 saa.saa_sct = &am18xx_sdmmc_functions; 828 saa.saa_spi_sct = NULL; 829 saa.saa_sch = sc; 830 saa.saa_dmat = faa->faa_dmat; 831 saa.saa_clkmin = clk_rate / AM18XX_SDMMC_MAX_CLOCK_DIVIDER / 1000; 832 u_int clkmax; 833 if (of_getprop_uint32(phandle, "max-frequency", &clkmax) == 0) { 834 saa.saa_clkmax = clkmax / 1000; /* Hz to kHz */ 835 } else { 836 saa.saa_clkmax = 25000; /* 25MHz is always okay */ 837 } 838 saa.saa_caps = SMC_CAPS_DMA; 839 840 if (of_hasprop(phandle, "cap-sd-highspeed")) { 841 saa.saa_caps |= SMC_CAPS_SD_HIGHSPEED; 842 } 843 if (of_hasprop(phandle, "cap-mmc-highspeed")) { 844 saa.saa_caps |= SMC_CAPS_MMC_HIGHSPEED; 845 } 846 847 uint32_t bus_width; 848 if (of_getprop_uint32(phandle, "bus-width", &bus_width)) { 849 bus_width = 1; 850 } 851 switch (bus_width) { 852 case 8: 853 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 854 break; 855 case 4: 856 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 857 break; 858 default: 859 /* use 1-bit mode */ 860 break; 861 } 862 863 sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL, CFARGS_NONE); 864 if (sc->sc_sdmmc == NULL) { 865 aprint_error_dev(sc->sc_dev, "unable to attach sdmmc\n"); 866 return; 867 } 868 } 869
Indexes created Sun Oct 25 00:26:45 UTC 2026