1 /* $NetBSD: pmap_motorola.c,v 1.111 2026/08/23 22:08:40 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991, 1993 34 * The Regents of the University of California. All rights reserved. 35 * 36 * This code is derived from software contributed to Berkeley by 37 * the Systems Programming Group of the University of Utah Computer 38 * Science Department. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. Neither the name of the University nor the names of its contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * @(#)pmap.c 8.6 (Berkeley) 5/27/94 65 */ 66 67 /* 68 * Motorola m68k-family physical map management code. 69 * 70 * Supports: 71 * 68020 with 68851 MMU 72 * 68020 with HP MMU 73 * 68030 with on-chip MMU 74 * 68040 with on-chip MMU 75 * 68060 with on-chip MMU 76 * 77 * Notes: 78 * Don't even pay lip service to multiprocessor support. 79 * 80 * We assume TLB entries don't have process tags (except for the 81 * supervisor/user distinction) so we only invalidate TLB entries 82 * when changing mappings for the current (or kernel) pmap. This is 83 * technically not true for the 68851 but we flush the TLB on every 84 * context switch, so it effectively winds up that way. 85 * 86 * Bitwise and/or operations are significantly faster than bitfield 87 * references so we use them when accessing STE/PTEs in the pmap_pte_* 88 * macros. Note also that the two are not always equivalent; e.g.: 89 * (*pte & PG_PROT) [4] != pte->pg_prot [1] 90 * and a couple of routines that deal with protection and wiring take 91 * some shortcuts that assume the and/or definitions. 92 */ 93 94 /* 95 * Manages physical address maps. 96 * 97 * In addition to hardware address maps, this 98 * module is called upon to provide software-use-only 99 * maps which may or may not be stored in the same 100 * form as hardware maps. These pseudo-maps are 101 * used to store intermediate results from copy 102 * operations to and from address spaces. 103 * 104 * Since the information managed by this module is 105 * also stored by the logical address mapping module, 106 * this module may throw away valid virtual-to-physical 107 * mappings at almost any time. However, invalidations 108 * of virtual-to-physical mappings must be done as 109 * requested. 110 * 111 * In order to cope with hardware architectures which 112 * make virtual-to-physical map invalidates expensive, 113 * this module may delay invalidate or reduced protection 114 * operations until such time as they are actually 115 * necessary. This module is given full information as 116 * to which processors are currently using which maps, 117 * and to when physical maps must be made correct. 118 */ 119 120 #include "opt_ddb.h" 121 #include "opt_kgdb.h" 122 #include "opt_m68k_arch.h" 123 124 #include <sys/cdefs.h> 125 __KERNEL_RCSID(0, "$NetBSD: pmap_motorola.c,v 1.111 2026/08/23 22:08:40 riastradh Exp $"); 126 127 #include <sys/param.h> 128 #include <sys/systm.h> 129 #include <sys/proc.h> 130 #include <sys/pool.h> 131 #include <sys/cpu.h> 132 #ifndef __HAVE_M68K_BROKEN_RMC 133 #include <sys/atomic.h> 134 #endif 135 136 #include <machine/pcb.h> 137 138 #include <uvm/uvm.h> 139 #include <uvm/uvm_physseg.h> 140 141 #include <m68k/cacheops.h> 142 #include <m68k/mmu.h> 143 144 #if !defined(M68K_MMU_MOTOROLA) && !defined(M68K_MMU_HP) 145 #error Hit the road, Jack... 146 #endif 147 148 #ifdef DEBUG 149 #define PDB_FOLLOW 0x0001 150 #define PDB_INIT 0x0002 151 #define PDB_ENTER 0x0004 152 #define PDB_REMOVE 0x0008 153 #define PDB_CREATE 0x0010 154 #define PDB_PTPAGE 0x0020 155 #define PDB_CACHE 0x0040 156 #define PDB_BITS 0x0080 157 #define PDB_COLLECT 0x0100 158 #define PDB_PROTECT 0x0200 159 #define PDB_SEGTAB 0x0400 160 #define PDB_MULTIMAP 0x0800 161 #define PDB_PARANOIA 0x2000 162 #define PDB_WIRING 0x4000 163 #define PDB_PVDUMP 0x8000 164 165 int debugmap = 0; 166 int pmapdebug = PDB_PARANOIA; 167 168 #define PMAP_DPRINTF(l, x) if (pmapdebug & (l)) printf x 169 #else /* ! DEBUG */ 170 #define PMAP_DPRINTF(l, x) /* nothing */ 171 #endif /* DEBUG */ 172 173 /* 174 * Get STEs and PTEs for user/kernel address space 175 */ 176 #if defined(M68040) || defined(M68060) 177 #define pmap_ste1(m, v) \ 178 (&((m)->pm_stab[(vaddr_t)(v) >> SG4_SHIFT1])) 179 /* XXX assumes physically contiguous ST pages (if more than one) */ 180 #define pmap_ste2(m, v) \ 181 (&((m)->pm_stab[(st_entry_t *)(*(u_int *)pmap_ste1(m, v) & SG4_ADDR1) \ 182 - (m)->pm_stpa + (((v) & SG4_MASK2) >> SG4_SHIFT2)])) 183 #if defined(M68020) || defined(M68030) 184 #define pmap_ste(m, v) \ 185 (&((m)->pm_stab[(vaddr_t)(v) \ 186 >> (mmutype == MMU_68040 ? SG4_SHIFT1 : SG_ISHIFT)])) 187 #define pmap_ste_v(m, v) \ 188 (mmutype == MMU_68040 \ 189 ? ((*pmap_ste1(m, v) & SG_V) && \ 190 (*pmap_ste2(m, v) & SG_V)) \ 191 : (*pmap_ste(m, v) & SG_V)) 192 #else 193 #define pmap_ste(m, v) \ 194 (&((m)->pm_stab[(vaddr_t)(v) >> SG4_SHIFT1])) 195 #define pmap_ste_v(m, v) \ 196 ((*pmap_ste1(m, v) & SG_V) && (*pmap_ste2(m, v) & SG_V)) 197 #endif 198 #else 199 #define pmap_ste(m, v) (&((m)->pm_stab[(vaddr_t)(v) >> SG_ISHIFT])) 200 #define pmap_ste_v(m, v) (*pmap_ste(m, v) & SG_V) 201 #endif 202 203 #define pmap_pte(m, v) (&((m)->pm_ptab[(vaddr_t)(v) >> PG_SHIFT])) 204 #define pmap_pte_pa(pte) (*(pte) & PG_FRAME) 205 #define pmap_pte_w(pte) (*(pte) & PG_W) 206 #define pmap_pte_ci(pte) (*(pte) & PG_CI) 207 #define pmap_pte_m(pte) (*(pte) & PG_M) 208 #define pmap_pte_u(pte) (*(pte) & PG_U) 209 #define pmap_pte_prot(pte) (*(pte) & PG_PROT) 210 #define pmap_pte_v(pte) (*(pte) & PG_V) 211 212 #define pmap_pte_set_w(pte, v) \ 213 if (v) *(pte) |= PG_W; else *(pte) &= ~PG_W 214 #define pmap_pte_set_prot(pte, v) \ 215 if (v) *(pte) |= PG_PROT; else *(pte) &= ~PG_PROT 216 #define pmap_pte_w_chg(pte, nw) ((nw) ^ pmap_pte_w(pte)) 217 #define pmap_pte_prot_chg(pte, np) ((np) ^ pmap_pte_prot(pte)) 218 219 /* 220 * Given a map and a machine independent protection code, 221 * convert to an m68k protection code. 222 */ 223 #define pte_prot(m, p) (protection_codes[p]) 224 static u_int protection_codes[8]; 225 226 /* 227 * Kernel page table page management. 228 */ 229 struct kpt_page { 230 struct kpt_page *kpt_next; /* link on either used or free list */ 231 vaddr_t kpt_va; /* always valid kernel VA */ 232 paddr_t kpt_pa; /* PA of this page (for speed) */ 233 }; 234 struct kpt_page *kpt_free_list, *kpt_used_list; 235 struct kpt_page *kpt_pages; 236 237 /* 238 * Kernel segment/page table and page table map. 239 * The page table map gives us a level of indirection we need to dynamically 240 * expand the page table. It is essentially a copy of the segment table 241 * with PTEs instead of STEs. All are initialized in locore at boot time. 242 * Sysmap will initially contain VM_KERNEL_PT_PAGES pages of PTEs. 243 * Segtabzero is an empty segment table which all processes share til they 244 * reference something. 245 */ 246 paddr_t Sysseg_pa; 247 st_entry_t *Sysseg; 248 pt_entry_t *Sysmap, *Sysptmap; 249 st_entry_t *Segtabzero, *Segtabzeropa; 250 251 /* # of kernel PT pages (initial only, can grow dynamically) */ 252 #ifndef VM_KERNEL_PT_PAGES 253 #define VM_KERNEL_PT_PAGES ((vsize_t)2) 254 #endif 255 vsize_t Sysptsize = VM_KERNEL_PT_PAGES; 256 257 static struct pmap kernel_pmap_store; 258 struct pmap *const kernel_pmap_ptr = &kernel_pmap_store; 259 struct vm_map *st_map, *pt_map; 260 struct vm_map st_map_store, pt_map_store; 261 262 vaddr_t lwp0uarea; /* lwp0 u-area VA, initialized in bootstrap */ 263 264 paddr_t avail_start; /* PA of first available physical page */ 265 paddr_t avail_end; /* PA of last available physical page */ 266 vaddr_t virtual_avail; /* VA of first avail page (after kernel bss)*/ 267 vaddr_t virtual_end; /* VA of last avail page (end of kernel AS) */ 268 int page_cnt; /* number of pages managed by VM system */ 269 270 bool pmap_initialized = false; /* Has pmap_init completed? */ 271 272 vaddr_t m68k_uptbase = M68K_PTBASE; 273 274 /* Sysmap begins where the managed kernel virtual space ends. */ 275 vaddr_t kernel_virtual_max = SYSMAP_VA; 276 277 struct pv_header { 278 struct pv_entry pvh_first; /* first PV entry */ 279 uint32_t pvh_attrs; /* attributes: 280 bits 0-7: PTE bits 281 bits 8-15: flags */ 282 }; 283 284 #define PVH_CI 0x10 /* all entries are cache-inhibited */ 285 #define PVH_PTPAGE 0x20 /* entry maps a page table page */ 286 287 struct pv_header *pv_table; 288 TAILQ_HEAD(pv_page_list, pv_page) pv_page_freelist; 289 int pv_nfree; 290 291 #ifdef M68K_EC_VAC 292 static u_int pmap_aliasmask; /* separation at which VA aliasing ok */ 293 #endif 294 #if defined(M68040) || defined(M68060) 295 u_int protostfree; /* prototype (default) free ST map */ 296 #endif 297 298 pt_entry_t *caddr1_pte; /* PTE for CADDR1 */ 299 pt_entry_t *caddr2_pte; /* PTE for CADDR2 */ 300 301 struct pool pmap_pmap_pool; /* memory pool for pmap structures */ 302 struct pool pmap_pv_pool; /* memory pool for pv entries */ 303 304 #define pmap_alloc_pv() pool_get(&pmap_pv_pool, PR_NOWAIT) 305 #define pmap_free_pv(pv) pool_put(&pmap_pv_pool, (pv)) 306 307 #define PAGE_IS_MANAGED(pa) (pmap_initialized && uvm_pageismanaged(pa)) 308 309 static inline struct pv_header * 310 pa_to_pvh(paddr_t pa) 311 { 312 uvm_physseg_t bank = 0; /* XXX gcc4 -Wuninitialized */ 313 psize_t pg = 0; 314 315 bank = uvm_physseg_find(atop((pa)), &pg); 316 return &uvm_physseg_get_pmseg(bank)->pvheader[pg]; 317 } 318 319 /* 320 * Internal routines 321 */ 322 void pmap_remove_mapping(pmap_t, vaddr_t, pt_entry_t *, int, 323 struct pv_entry **); 324 bool pmap_testbit(paddr_t, int); 325 bool pmap_changebit(paddr_t, pt_entry_t, pt_entry_t); 326 int pmap_enter_ptpage(pmap_t, vaddr_t, bool); 327 void pmap_ptpage_addref(vaddr_t); 328 int pmap_ptpage_delref(vaddr_t); 329 void pmap_pinit(pmap_t); 330 void pmap_release(pmap_t); 331 332 #ifdef DEBUG 333 void pmap_pvdump(paddr_t); 334 void pmap_check_wiring(const char *, vaddr_t); 335 #endif 336 337 /* pmap_remove_mapping flags */ 338 #define PRM_TFLUSH 0x01 339 #define PRM_CFLUSH 0x02 340 #define PRM_KEEPPTPAGE 0x04 341 342 #define active_pmap(pm) \ 343 ((pm) == pmap_kernel() || (pm) == curproc->p_vmspace->vm_map.pmap) 344 345 #define active_user_pmap(pm) \ 346 (curproc && \ 347 (pm) != pmap_kernel() && (pm) == curproc->p_vmspace->vm_map.pmap) 348 349 static void (*pmap_load_urp_func)(paddr_t); 350 351 /* 352 * pmap_load_urp: 353 * 354 * Load the user root table into the MMU. 355 */ 356 static inline void 357 pmap_load_urp(paddr_t urp) 358 { 359 (*pmap_load_urp_func)(urp); 360 } 361 362 #ifdef M68K_EC_VAC 363 /* 364 * pmap_init_vac: 365 * 366 * Set up virtually-addressed cache information. Only relevant 367 * for the HP MMU. 368 */ 369 void 370 pmap_init_vac(size_t vacsize) 371 { 372 KASSERT(pmap_aliasmask == 0); 373 KASSERT(powerof2(vacsize)); 374 pmap_aliasmask = vacsize - 1; 375 } 376 #endif /* M68K_EC_VAC */ 377 378 /* 379 * PAGE_SIZE should always evaluate to a compile-time constant in this 380 * context. 381 */ 382 __CTASSERT(PAGE_SIZE != 0); 383 384 /* 385 * pmap_bootstrap2: [ INTERFACE ] 386 * 387 * Phase 2 of pmap bootstrap. (Phase 1 is system-specific.) 388 * 389 * Initialize lwp0 uarea, curlwp, and curpcb after MMU is turned on, 390 * using lwp0uarea variable saved during pmap_bootstrap(). 391 * 392 * Returns the new kernel %sp value for lwp0. 393 */ 394 void * 395 pmap_bootstrap2(void) 396 { 397 398 uvmexp.pagesize = PAGE_SIZE; 399 uvm_md_init(); 400 401 /* 402 * Initialize protection array. 403 * XXX: Could this have port specific values? Can't this be static? 404 */ 405 protection_codes[VM_PROT_NONE|VM_PROT_NONE|VM_PROT_NONE] = 0; 406 protection_codes[VM_PROT_READ|VM_PROT_NONE|VM_PROT_NONE] = PG_RO; 407 protection_codes[VM_PROT_READ|VM_PROT_NONE|VM_PROT_EXECUTE] = PG_RO; 408 protection_codes[VM_PROT_NONE|VM_PROT_NONE|VM_PROT_EXECUTE] = PG_RO; 409 protection_codes[VM_PROT_NONE|VM_PROT_WRITE|VM_PROT_NONE] = PG_RW; 410 protection_codes[VM_PROT_NONE|VM_PROT_WRITE|VM_PROT_EXECUTE] = PG_RW; 411 protection_codes[VM_PROT_READ|VM_PROT_WRITE|VM_PROT_NONE] = PG_RW; 412 protection_codes[VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE] = PG_RW; 413 414 /* 415 * Initialize pmap_kernel(). 416 */ 417 pmap_kernel()->pm_stpa = (st_entry_t *)Sysseg_pa; 418 pmap_kernel()->pm_stab = Sysseg; 419 pmap_kernel()->pm_ptab = Sysmap; 420 #if defined(M68040) || defined(M68060) 421 if (mmutype == MMU_68040) 422 pmap_kernel()->pm_stfree = protostfree; 423 #endif 424 pmap_kernel()->pm_count = 1; 425 426 /* 427 * Initialize lwp0 uarea, curlwp, and curpcb. 428 */ 429 memset((void *)lwp0uarea, 0, USPACE); 430 uvm_lwp_setuarea(&lwp0, lwp0uarea); 431 curlwp = &lwp0; 432 curpcb = lwp_getpcb(&lwp0); 433 434 /* Create a fake exception frame so that cpu_lwp_fork() can copy it. */ 435 struct trapframe *tf = (struct trapframe *)(lwp0uarea + USPACE) - 1; 436 tf->tf_sr = PSL_USER; 437 lwp0.l_md.md_regs = (int *)tf; 438 439 /* 440 * Initialize the source/destination control registers for 441 * movs. 442 */ 443 setsfc(FC_USERD); 444 setdfc(FC_USERD); 445 446 return tf; 447 } 448 449 /* 450 * pmap_virtual_space: [ INTERFACE ] 451 * 452 * Report the range of available kernel virtual address 453 * space to the VM system during bootstrap. 454 * 455 * This is only an interface function if we do not use 456 * pmap_steal_memory()! 457 * 458 * Note: no locking is necessary in this function. 459 */ 460 void 461 pmap_virtual_space(vaddr_t *vstartp, vaddr_t *vendp) 462 { 463 464 *vstartp = virtual_avail; 465 *vendp = virtual_end; 466 } 467 468 /* 469 * pmap_init: [ INTERFACE ] 470 * 471 * Initialize the pmap module. Called by vm_init(), to initialize any 472 * structures that the pmap system needs to map virtual memory. 473 * 474 * Note: no locking is necessary in this function. 475 */ 476 void 477 pmap_init(void) 478 { 479 vaddr_t addr, addr2; 480 vsize_t s; 481 struct pv_header *pvh; 482 int rv; 483 int npages; 484 uvm_physseg_t bank; 485 486 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_init()\n")); 487 488 /* 489 * Before we do anything else, initialize the PTE pointers 490 * used by pmap_zero_page() and pmap_copy_page(). 491 */ 492 caddr1_pte = pmap_pte(pmap_kernel(), CADDR1); 493 caddr2_pte = pmap_pte(pmap_kernel(), CADDR2); 494 495 PMAP_DPRINTF(PDB_INIT, 496 ("pmap_init: Sysseg %p, Sysmap %p, Sysptmap %p\n", 497 Sysseg, Sysmap, Sysptmap)); 498 PMAP_DPRINTF(PDB_INIT, 499 (" pstart %lx, pend %lx, vstart %lx, vend %lx\n", 500 avail_start, avail_end, virtual_avail, virtual_end)); 501 502 /* 503 * Allocate memory for random pmap data structures. Includes the 504 * initial segment table, pv_head_table and pmap_attributes. 505 */ 506 for (page_cnt = 0, bank = uvm_physseg_get_first(); 507 uvm_physseg_valid_p(bank); 508 bank = uvm_physseg_get_next(bank)) 509 page_cnt += uvm_physseg_get_end(bank) - uvm_physseg_get_start(bank); 510 s = M68K_STSIZE; /* Segtabzero */ 511 s += page_cnt * sizeof(struct pv_header); /* pv table */ 512 s = round_page(s); 513 addr = uvm_km_alloc(kernel_map, s, 0, UVM_KMF_WIRED | UVM_KMF_ZERO); 514 if (addr == 0) 515 panic("pmap_init: can't allocate data structures"); 516 517 Segtabzero = (st_entry_t *)addr; 518 (void)pmap_extract(pmap_kernel(), addr, 519 (paddr_t *)(void *)&Segtabzeropa); 520 addr += M68K_STSIZE; 521 522 pv_table = (struct pv_header *) addr; 523 addr += page_cnt * sizeof(struct pv_header); 524 525 PMAP_DPRINTF(PDB_INIT, ("pmap_init: %lx bytes: page_cnt %x s0 %p(%p) " 526 "tbl %p\n", 527 s, page_cnt, Segtabzero, Segtabzeropa, 528 pv_table)); 529 530 /* 531 * Now that the pv and attribute tables have been allocated, 532 * assign them to the memory segments. 533 */ 534 pvh = pv_table; 535 for (bank = uvm_physseg_get_first(); 536 uvm_physseg_valid_p(bank); 537 bank = uvm_physseg_get_next(bank)) { 538 npages = uvm_physseg_get_end(bank) - uvm_physseg_get_start(bank); 539 uvm_physseg_get_pmseg(bank)->pvheader = pvh; 540 pvh += npages; 541 } 542 543 /* 544 * Allocate physical memory for kernel PT pages and their management. 545 * We need 1 PT page per possible task plus some slop. 546 */ 547 npages = uimin(atop(M68K_MAX_KPTSIZE), maxproc+16); 548 s = ptoa(npages) + round_page(npages * sizeof(struct kpt_page)); 549 550 /* 551 * Verify that space will be allocated in region for which 552 * we already have kernel PT pages. 553 */ 554 addr = 0; 555 rv = uvm_map(kernel_map, &addr, s, NULL, UVM_UNKNOWN_OFFSET, 0, 556 UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, 557 UVM_ADV_RANDOM, UVM_FLAG_NOMERGE)); 558 if (rv != 0 || (addr + s) >= (vaddr_t)Sysmap) 559 panic("pmap_init: kernel PT too small"); 560 uvm_unmap(kernel_map, addr, addr + s); 561 562 /* 563 * Now allocate the space and link the pages together to 564 * form the KPT free list. 565 */ 566 addr = uvm_km_alloc(kernel_map, s, 0, UVM_KMF_WIRED | UVM_KMF_ZERO); 567 if (addr == 0) 568 panic("pmap_init: cannot allocate KPT free list"); 569 s = ptoa(npages); 570 addr2 = addr + s; 571 kpt_pages = &((struct kpt_page *)addr2)[npages]; 572 kpt_free_list = NULL; 573 do { 574 addr2 -= PAGE_SIZE; 575 (--kpt_pages)->kpt_next = kpt_free_list; 576 kpt_free_list = kpt_pages; 577 kpt_pages->kpt_va = addr2; 578 (void) pmap_extract(pmap_kernel(), addr2, 579 (paddr_t *)&kpt_pages->kpt_pa); 580 } while (addr != addr2); 581 582 PMAP_DPRINTF(PDB_INIT, ("pmap_init: KPT: %ld pages from %lx to %lx\n", 583 atop(s), addr, addr + s)); 584 585 /* 586 * Allocate the segment table map and the page table map. 587 */ 588 s = maxproc * M68K_STSIZE; 589 st_map = uvm_km_suballoc(kernel_map, &addr, &addr2, s, 0, false, 590 &st_map_store); 591 592 addr = m68k_uptbase; 593 if ((M68K_PTMAXSIZE / M68K_MAX_PTSIZE) < maxproc) { 594 s = M68K_PTMAXSIZE; 595 /* 596 * XXX We don't want to hang when we run out of 597 * page tables, so we lower maxproc so that fork() 598 * will fail instead. Note that root could still raise 599 * this value via sysctl(3). 600 */ 601 maxproc = (M68K_PTMAXSIZE / M68K_MAX_PTSIZE); 602 } else 603 s = (maxproc * M68K_MAX_PTSIZE); 604 pt_map = uvm_km_suballoc(kernel_map, &addr, &addr2, s, 0, 605 true, &pt_map_store); 606 607 #if defined(M68040) || defined(M68060) 608 if (mmutype == MMU_68040) { 609 protostfree = ~l2tobm(0); 610 for (rv = MAXUL2SIZE; rv < sizeof(protostfree)*NBBY; rv++) 611 protostfree &= ~l2tobm(rv); 612 } 613 #endif 614 615 /* 616 * Initialize the pmap pools. 617 */ 618 pool_init(&pmap_pmap_pool, sizeof(struct pmap), 0, 0, 0, "pmappl", 619 &pool_allocator_nointr, IPL_NONE); 620 621 /* 622 * Initialize the pv_entry pools. 623 */ 624 pool_init(&pmap_pv_pool, sizeof(struct pv_entry), 0, 0, 0, "pvpl", 625 &pool_allocator_meta, IPL_NONE); 626 627 /* 628 * Now that this is done, mark the pages shared with the 629 * hardware page table search as non-CCB (actually, as CI). 630 * 631 * XXX Hm. Given that this is in the kernel map, can't we just 632 * use the va's? 633 */ 634 #ifdef M68060 635 #if defined(M68020) || defined(M68030) || defined(M68040) 636 if (cputype == CPU_68060) 637 #endif 638 { 639 struct kpt_page *kptp = kpt_free_list; 640 paddr_t paddr; 641 642 while (kptp) { 643 pmap_changebit(kptp->kpt_pa, PG_CI, 644 (pt_entry_t)~PG_CCB); 645 kptp = kptp->kpt_next; 646 } 647 648 paddr = (paddr_t)Segtabzeropa; 649 while (paddr < (paddr_t)Segtabzeropa + M68K_STSIZE) { 650 pmap_changebit(paddr, PG_CI, 651 (pt_entry_t)~PG_CCB); 652 paddr += PAGE_SIZE; 653 } 654 655 DCIS(); 656 } 657 #endif 658 659 /* 660 * Set up the routine that loads the MMU root table pointer. 661 */ 662 switch (cputype) { 663 #if defined(M68020) 664 case CPU_68020: 665 #ifdef M68K_MMU_MOTOROLA 666 if (mmutype == MMU_68851) { 667 protorp[0] = MMU51_CRP_BITS; 668 pmap_load_urp_func = mmu_load_urp51; 669 } 670 #endif 671 #ifdef M68K_MMU_HP 672 if (mmutype == MMU_HP) { 673 pmap_load_urp_func = mmu_load_urp20hp; 674 } 675 #endif 676 break; 677 #endif /* M68020 */ 678 #if defined(M68030) 679 case CPU_68030: 680 protorp[0] = MMU51_CRP_BITS; 681 pmap_load_urp_func = mmu_load_urp51; 682 break; 683 #endif /* M68030 */ 684 #if defined(M68040) 685 case CPU_68040: 686 pmap_load_urp_func = mmu_load_urp40; 687 break; 688 #endif /* M68040 */ 689 #if defined(M68060) 690 case CPU_68060: 691 pmap_load_urp_func = mmu_load_urp60; 692 break; 693 #endif /* M68060 */ 694 default: 695 break; 696 } 697 if (pmap_load_urp_func == NULL) { 698 panic("pmap_init: No mmu_load_*() for cpu=%d mmu=%d", 699 cputype, mmutype); 700 } 701 702 /* 703 * Now it is safe to enable pv_table recording. 704 */ 705 pmap_initialized = true; 706 } 707 708 /* 709 * pmap_create: [ INTERFACE ] 710 * 711 * Create and return a physical map. 712 * 713 * Note: no locking is necessary in this function. 714 */ 715 pmap_t 716 pmap_create(void) 717 { 718 struct pmap *pmap; 719 720 PMAP_DPRINTF(PDB_FOLLOW|PDB_CREATE, 721 ("pmap_create()\n")); 722 723 pmap = pool_get(&pmap_pmap_pool, PR_WAITOK); 724 memset(pmap, 0, sizeof(*pmap)); 725 pmap_pinit(pmap); 726 return pmap; 727 } 728 729 /* 730 * pmap_pinit: 731 * 732 * Initialize a preallocated and zeroed pmap structure. 733 * 734 * Note: THIS FUNCTION SHOULD BE MOVED INTO pmap_create()! 735 */ 736 void 737 pmap_pinit(struct pmap *pmap) 738 { 739 740 PMAP_DPRINTF(PDB_FOLLOW|PDB_CREATE, 741 ("pmap_pinit(%p)\n", pmap)); 742 743 /* 744 * No need to allocate page table space yet but we do need a 745 * valid segment table. Initially, we point everyone at the 746 * "null" segment table. On the first pmap_enter, a real 747 * segment table will be allocated. 748 */ 749 pmap->pm_stab = Segtabzero; 750 pmap->pm_stpa = Segtabzeropa; 751 #if defined(M68040) || defined(M68060) 752 #if defined(M68020) || defined(M68030) 753 if (mmutype == MMU_68040) 754 #endif 755 pmap->pm_stfree = protostfree; 756 #endif 757 pmap->pm_count = 1; 758 } 759 760 /* 761 * pmap_destroy: [ INTERFACE ] 762 * 763 * Drop the reference count on the specified pmap, releasing 764 * all resources if the reference count drops to zero. 765 */ 766 void 767 pmap_destroy(pmap_t pmap) 768 { 769 int count; 770 771 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_destroy(%p)\n", pmap)); 772 773 #ifdef __HAVE_M68K_BROKEN_RMC 774 count = --pmap->pm_count; 775 #else 776 count = atomic_dec_uint_nv(&pmap->pm_count); 777 #endif 778 if (count == 0) { 779 pmap_release(pmap); 780 pool_put(&pmap_pmap_pool, pmap); 781 } 782 } 783 784 /* 785 * pmap_release: 786 * 787 * Release the resources held by a pmap. 788 * 789 * Note: THIS FUNCTION SHOULD BE MOVED INTO pmap_destroy(). 790 */ 791 void 792 pmap_release(pmap_t pmap) 793 { 794 795 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_release(%p)\n", pmap)); 796 797 #ifdef notdef /* DIAGNOSTIC */ 798 /* count would be 0 from pmap_destroy... */ 799 if (pmap->pm_count != 1) 800 panic("pmap_release count"); 801 #endif 802 803 if (pmap->pm_ptab) { 804 pmap_remove(pmap_kernel(), (vaddr_t)pmap->pm_ptab, 805 (vaddr_t)pmap->pm_ptab + M68K_MAX_PTSIZE); 806 uvm_km_pgremove((vaddr_t)pmap->pm_ptab, 807 (vaddr_t)pmap->pm_ptab + M68K_MAX_PTSIZE); 808 uvm_km_free(pt_map, (vaddr_t)pmap->pm_ptab, 809 M68K_MAX_PTSIZE, UVM_KMF_VAONLY); 810 } 811 KASSERT(pmap->pm_stab == Segtabzero); 812 } 813 814 /* 815 * pmap_reference: [ INTERFACE ] 816 * 817 * Add a reference to the specified pmap. 818 */ 819 void 820 pmap_reference(pmap_t pmap) 821 { 822 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_reference(%p)\n", pmap)); 823 824 #ifdef __HAVE_M68K_BROKEN_RMC 825 pmap->pm_count++; 826 #else 827 atomic_inc_uint(&pmap->pm_count); 828 #endif 829 } 830 831 /* 832 * pmap_activate: [ INTERFACE ] 833 * 834 * Activate the pmap used by the specified process. This includes 835 * reloading the MMU context if the current process, and marking 836 * the pmap in use by the processor. 837 * 838 * Note: we may only use spin locks here, since we are called 839 * by a critical section in cpu_switch()! 840 */ 841 void 842 pmap_activate(struct lwp *l) 843 { 844 pmap_t pmap = l->l_proc->p_vmspace->vm_map.pmap; 845 846 PMAP_DPRINTF(PDB_FOLLOW|PDB_SEGTAB, 847 ("pmap_activate(%p)\n", l)); 848 849 KASSERT(l == curlwp); 850 851 /* 852 * Because the kernel has a separate root pointer, we don't 853 * need to activate the kernel pmap. 854 */ 855 if (pmap != pmap_kernel()) { 856 pmap_load_urp((paddr_t)pmap->pm_stpa); 857 } 858 } 859 860 /* 861 * pmap_deactivate: [ INTERFACE ] 862 * 863 * Mark that the pmap used by the specified process is no longer 864 * in use by the processor. 865 * 866 * The comment above pmap_activate() wrt. locking applies here, 867 * as well. 868 */ 869 void 870 pmap_deactivate(struct lwp *l) 871 { 872 873 /* No action necessary in this pmap implementation. */ 874 } 875 876 /* 877 * pmap_remove: [ INTERFACE ] 878 * 879 * Remove the given range of addresses from the specified map. 880 * 881 * It is assumed that the start and end are properly 882 * rounded to the page size. 883 */ 884 void 885 pmap_remove(pmap_t pmap, vaddr_t sva, vaddr_t eva) 886 { 887 vaddr_t nssva; 888 pt_entry_t *pte; 889 int flags; 890 #ifdef M68K_EC_VAC 891 bool firstpage = true, needcflush = false; 892 #endif 893 894 PMAP_DPRINTF(PDB_FOLLOW|PDB_REMOVE|PDB_PROTECT, 895 ("pmap_remove(%p, %lx, %lx)\n", pmap, sva, eva)); 896 897 flags = active_pmap(pmap) ? PRM_TFLUSH : 0; 898 while (sva < eva) { 899 nssva = m68k_trunc_seg(sva) + NBSEG; 900 if (nssva == 0 || nssva > eva) 901 nssva = eva; 902 903 /* 904 * Invalidate every valid mapping within this segment. 905 */ 906 907 pte = pmap_pte(pmap, sva); 908 while (sva < nssva) { 909 910 /* 911 * If this segment is unallocated, 912 * skip to the next segment boundary. 913 */ 914 915 if (!pmap_ste_v(pmap, sva)) { 916 sva = nssva; 917 break; 918 } 919 920 if (pmap_pte_v(pte)) { 921 #ifdef M68K_EC_VAC 922 if (pmap_aliasmask) { 923 924 /* 925 * Purge kernel side of VAC to ensure 926 * we get the correct state of any 927 * hardware maintained bits. 928 */ 929 930 if (firstpage) { 931 DCIS(); 932 } 933 934 /* 935 * Remember if we may need to 936 * flush the VAC due to a non-CI 937 * mapping. 938 */ 939 940 if (!needcflush && !pmap_pte_ci(pte)) 941 needcflush = true; 942 943 } 944 firstpage = false; 945 #endif 946 pmap_remove_mapping(pmap, sva, pte, flags, NULL); 947 } 948 pte++; 949 sva += PAGE_SIZE; 950 } 951 } 952 953 #ifdef M68K_EC_VAC 954 955 /* 956 * Didn't do anything, no need for cache flushes 957 */ 958 959 if (firstpage) 960 return; 961 962 /* 963 * In a couple of cases, we don't need to worry about flushing 964 * the VAC: 965 * 1. if this is a kernel mapping, 966 * we have already done it 967 * 2. if it is a user mapping not for the current process, 968 * it won't be there 969 */ 970 971 if (pmap_aliasmask && !active_user_pmap(pmap)) 972 needcflush = false; 973 if (needcflush) { 974 if (pmap == pmap_kernel()) { 975 DCIS(); 976 } else { 977 DCIU(); 978 } 979 } 980 #endif 981 } 982 983 /* 984 * pmap_page_protect: [ INTERFACE ] 985 * 986 * Lower the permission for all mappings to a given page to 987 * the permissions specified. 988 */ 989 void 990 pmap_page_protect(struct vm_page *pg, vm_prot_t prot) 991 { 992 paddr_t pa = VM_PAGE_TO_PHYS(pg); 993 struct pv_header *pvh; 994 struct pv_entry *pv; 995 pt_entry_t *pte; 996 int s; 997 998 #ifdef DEBUG 999 if ((pmapdebug & (PDB_FOLLOW|PDB_PROTECT)) || 1000 (prot == VM_PROT_NONE && (pmapdebug & PDB_REMOVE))) 1001 printf("pmap_page_protect(%p, %x)\n", pg, prot); 1002 #endif 1003 1004 switch (prot) { 1005 case VM_PROT_READ|VM_PROT_WRITE: 1006 case VM_PROT_ALL: 1007 return; 1008 1009 /* copy_on_write */ 1010 case VM_PROT_READ: 1011 case VM_PROT_READ|VM_PROT_EXECUTE: 1012 pmap_changebit(pa, PG_RO, ~0); 1013 return; 1014 1015 /* remove_all */ 1016 default: 1017 break; 1018 } 1019 1020 pvh = pa_to_pvh(pa); 1021 pv = &pvh->pvh_first; 1022 s = splvm(); 1023 while (pv->pv_pmap != NULL) { 1024 1025 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1026 #ifdef DEBUG 1027 if (!pmap_ste_v(pv->pv_pmap, pv->pv_va) || 1028 pmap_pte_pa(pte) != pa) 1029 panic("pmap_page_protect: bad mapping"); 1030 #endif 1031 pmap_remove_mapping(pv->pv_pmap, pv->pv_va, 1032 pte, PRM_TFLUSH|PRM_CFLUSH, NULL); 1033 } 1034 splx(s); 1035 } 1036 1037 /* 1038 * pmap_protect: [ INTERFACE ] 1039 * 1040 * Set the physical protection on the specified range of this map 1041 * as requested. 1042 */ 1043 void 1044 pmap_protect(pmap_t pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot) 1045 { 1046 vaddr_t nssva; 1047 pt_entry_t *pte; 1048 bool firstpage __unused, needtflush; 1049 int isro; 1050 1051 PMAP_DPRINTF(PDB_FOLLOW|PDB_PROTECT, 1052 ("pmap_protect(%p, %lx, %lx, %x)\n", 1053 pmap, sva, eva, prot)); 1054 1055 #ifdef PMAPSTATS 1056 protect_stats.calls++; 1057 #endif 1058 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1059 pmap_remove(pmap, sva, eva); 1060 return; 1061 } 1062 isro = pte_prot(pmap, prot); 1063 needtflush = active_pmap(pmap); 1064 firstpage = true; 1065 while (sva < eva) { 1066 nssva = m68k_trunc_seg(sva) + NBSEG; 1067 if (nssva == 0 || nssva > eva) 1068 nssva = eva; 1069 1070 /* 1071 * If VA belongs to an unallocated segment, 1072 * skip to the next segment boundary. 1073 */ 1074 1075 if (!pmap_ste_v(pmap, sva)) { 1076 sva = nssva; 1077 continue; 1078 } 1079 1080 /* 1081 * Change protection on mapping if it is valid and doesn't 1082 * already have the correct protection. 1083 */ 1084 1085 pte = pmap_pte(pmap, sva); 1086 while (sva < nssva) { 1087 if (pmap_pte_v(pte) && pmap_pte_prot_chg(pte, isro)) { 1088 #ifdef M68K_EC_VAC 1089 1090 /* 1091 * Purge kernel side of VAC to ensure we 1092 * get the correct state of any hardware 1093 * maintained bits. 1094 * 1095 * XXX do we need to clear the VAC in 1096 * general to reflect the new protection? 1097 */ 1098 1099 if (firstpage && pmap_aliasmask) 1100 DCIS(); 1101 #endif 1102 1103 #if defined(M68040) || defined(M68060) 1104 1105 /* 1106 * Clear caches if making RO (see section 1107 * "7.3 Cache Coherency" in the manual). 1108 */ 1109 1110 #if defined(M68020) || defined(M68030) 1111 if (isro && mmutype == MMU_68040) 1112 #else 1113 if (isro) 1114 #endif 1115 { 1116 paddr_t pa = pmap_pte_pa(pte); 1117 1118 DCFP(pa); 1119 ICPP(pa); 1120 } 1121 #endif 1122 pmap_pte_set_prot(pte, isro); 1123 if (needtflush) 1124 TBIS(sva); 1125 firstpage = false; 1126 } 1127 pte++; 1128 sva += PAGE_SIZE; 1129 } 1130 } 1131 } 1132 1133 /* 1134 * pmap_enter: [ INTERFACE ] 1135 * 1136 * Insert the given physical page (pa) at 1137 * the specified virtual address (va) in the 1138 * target physical map with the protection requested. 1139 * 1140 * If specified, the page will be wired down, meaning 1141 * that the related pte cannot be reclaimed. 1142 * 1143 * Note: This is the only routine which MAY NOT lazy-evaluate 1144 * or lose information. Thatis, this routine must actually 1145 * insert this page into the given map NOW. 1146 */ 1147 int 1148 pmap_enter(pmap_t pmap, vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 1149 { 1150 pt_entry_t *pte; 1151 struct pv_entry *opv = NULL; 1152 int npte; 1153 paddr_t opa; 1154 bool cacheable = true; 1155 bool checkpv = true; 1156 bool wired = (flags & PMAP_WIRED) != 0; 1157 bool can_fail = (flags & PMAP_CANFAIL) != 0; 1158 1159 PMAP_DPRINTF(PDB_FOLLOW|PDB_ENTER, 1160 ("pmap_enter(%p, %lx, %lx, %x, %x)\n", 1161 pmap, va, pa, prot, wired)); 1162 1163 #ifdef DIAGNOSTIC 1164 /* 1165 * pmap_enter() should never be used for CADDR1 and CADDR2. 1166 */ 1167 if (pmap == pmap_kernel() && 1168 (va == (vaddr_t)CADDR1 || va == (vaddr_t)CADDR2)) 1169 panic("pmap_enter: used for CADDR1 or CADDR2"); 1170 #endif 1171 1172 /* 1173 * For user mapping, allocate kernel VM resources if necessary. 1174 */ 1175 if (pmap->pm_ptab == NULL) { 1176 pmap->pm_ptab = (pt_entry_t *) 1177 uvm_km_alloc(pt_map, M68K_MAX_PTSIZE, 0, 1178 UVM_KMF_VAONLY | 1179 (can_fail ? UVM_KMF_NOWAIT : UVM_KMF_WAITVA)); 1180 if (pmap->pm_ptab == NULL) 1181 return ENOMEM; 1182 } 1183 1184 /* 1185 * Segment table entry not valid, we need a new PT page 1186 */ 1187 if (!pmap_ste_v(pmap, va)) { 1188 int err = pmap_enter_ptpage(pmap, va, can_fail); 1189 if (err) 1190 return err; 1191 } 1192 1193 pa = m68k_trunc_page(pa); 1194 pte = pmap_pte(pmap, va); 1195 opa = pmap_pte_pa(pte); 1196 1197 PMAP_DPRINTF(PDB_ENTER, ("enter: pte %p, *pte %x\n", pte, *pte)); 1198 1199 /* 1200 * Mapping has not changed, must be protection or wiring change. 1201 */ 1202 if (opa == pa) { 1203 /* 1204 * Wiring change, just update stats. 1205 * We don't worry about wiring PT pages as they remain 1206 * resident as long as there are valid mappings in them. 1207 * Hence, if a user page is wired, the PT page will be also. 1208 */ 1209 if (pmap_pte_w_chg(pte, wired ? PG_W : 0)) { 1210 PMAP_DPRINTF(PDB_ENTER, 1211 ("enter: wiring change -> %x\n", wired)); 1212 if (wired) 1213 pmap->pm_stats.wired_count++; 1214 else 1215 pmap->pm_stats.wired_count--; 1216 } 1217 /* 1218 * Retain cache inhibition status 1219 */ 1220 checkpv = false; 1221 if (pmap_pte_ci(pte)) 1222 cacheable = false; 1223 goto validate; 1224 } 1225 1226 /* 1227 * Mapping has changed, invalidate old range and fall through to 1228 * handle validating new mapping. 1229 */ 1230 if (opa) { 1231 PMAP_DPRINTF(PDB_ENTER, 1232 ("enter: removing old mapping %lx\n", va)); 1233 pmap_remove_mapping(pmap, va, pte, 1234 PRM_TFLUSH|PRM_CFLUSH|PRM_KEEPPTPAGE, &opv); 1235 } 1236 1237 /* 1238 * If this is a new user mapping, increment the wiring count 1239 * on this PT page. PT pages are wired down as long as there 1240 * is a valid mapping in the page. 1241 */ 1242 if (pmap != pmap_kernel()) 1243 pmap_ptpage_addref(trunc_page((vaddr_t)pte)); 1244 1245 /* 1246 * Enter on the PV list if part of our managed memory 1247 * Note that we raise IPL while manipulating pv_table 1248 * since pmap_enter can be called at interrupt time. 1249 */ 1250 if (PAGE_IS_MANAGED(pa)) { 1251 struct pv_header *pvh; 1252 struct pv_entry *pv, *npv; 1253 int s; 1254 1255 pvh = pa_to_pvh(pa); 1256 pv = &pvh->pvh_first; 1257 s = splvm(); 1258 1259 PMAP_DPRINTF(PDB_ENTER, 1260 ("enter: pv at %p: %lx/%p/%p\n", 1261 pv, pv->pv_va, pv->pv_pmap, pv->pv_next)); 1262 /* 1263 * No entries yet, use header as the first entry 1264 */ 1265 if (pv->pv_pmap == NULL) { 1266 pv->pv_va = va; 1267 pv->pv_pmap = pmap; 1268 pv->pv_next = NULL; 1269 pv->pv_ptste = NULL; 1270 pv->pv_ptpmap = NULL; 1271 pvh->pvh_attrs = 0; 1272 } 1273 /* 1274 * There is at least one other VA mapping this page. 1275 * Place this entry after the header. 1276 */ 1277 else { 1278 #ifdef DEBUG 1279 for (npv = pv; npv; npv = npv->pv_next) 1280 if (pmap == npv->pv_pmap && va == npv->pv_va) 1281 panic("pmap_enter: already in pv_tab"); 1282 #endif 1283 if (opv != NULL) { 1284 npv = opv; 1285 opv = NULL; 1286 } else { 1287 npv = pmap_alloc_pv(); 1288 } 1289 KASSERT(npv != NULL); 1290 npv->pv_va = va; 1291 npv->pv_pmap = pmap; 1292 npv->pv_next = pv->pv_next; 1293 npv->pv_ptste = NULL; 1294 npv->pv_ptpmap = NULL; 1295 pv->pv_next = npv; 1296 1297 #ifdef M68K_EC_VAC 1298 1299 /* 1300 * Since there is another logical mapping for the 1301 * same page we may need to cache-inhibit the 1302 * descriptors on those CPUs with external VACs. 1303 * We don't need to CI if: 1304 * 1305 * - No two mappings belong to the same user pmaps. 1306 * Since the cache is flushed on context switches 1307 * there is no problem between user processes. 1308 * 1309 * - Mappings within a single pmap are a certain 1310 * magic distance apart. VAs at these appropriate 1311 * boundaries map to the same cache entries or 1312 * otherwise don't conflict. 1313 * 1314 * To keep it simple, we only check for these special 1315 * cases if there are only two mappings, otherwise we 1316 * punt and always CI. 1317 * 1318 * Note that there are no aliasing problems with the 1319 * on-chip data-cache when the WA bit is set. 1320 */ 1321 1322 if (pmap_aliasmask) { 1323 if (pvh->pvh_attrs & PVH_CI) { 1324 PMAP_DPRINTF(PDB_CACHE, 1325 ("enter: pa %lx already CI'ed\n", 1326 pa)); 1327 checkpv = cacheable = false; 1328 } else if (npv->pv_next || 1329 ((pmap == pv->pv_pmap || 1330 pmap == pmap_kernel() || 1331 pv->pv_pmap == pmap_kernel()) && 1332 ((pv->pv_va & pmap_aliasmask) != 1333 (va & pmap_aliasmask)))) { 1334 PMAP_DPRINTF(PDB_CACHE, 1335 ("enter: pa %lx CI'ing all\n", 1336 pa)); 1337 cacheable = false; 1338 pvh->pvh_attrs |= PVH_CI; 1339 } 1340 } 1341 #endif 1342 } 1343 1344 /* 1345 * Speed pmap_is_referenced() or pmap_is_modified() based 1346 * on the hint provided in access_type. 1347 */ 1348 #ifdef DIAGNOSTIC 1349 if ((flags & VM_PROT_ALL) & ~prot) 1350 panic("pmap_enter: access_type exceeds prot"); 1351 #endif 1352 if (flags & VM_PROT_WRITE) 1353 pvh->pvh_attrs |= (PG_U|PG_M); 1354 else if (flags & VM_PROT_ALL) 1355 pvh->pvh_attrs |= PG_U; 1356 1357 splx(s); 1358 } 1359 /* 1360 * Assumption: if it is not part of our managed memory 1361 * then it must be device memory which may be volatile. 1362 */ 1363 else if (pmap_initialized) { 1364 checkpv = cacheable = false; 1365 } 1366 1367 /* 1368 * Increment counters 1369 */ 1370 pmap->pm_stats.resident_count++; 1371 if (wired) 1372 pmap->pm_stats.wired_count++; 1373 1374 validate: 1375 #ifdef M68K_EC_VAC 1376 /* 1377 * Purge kernel side of VAC to ensure we get correct state 1378 * of HW bits so we don't clobber them. 1379 */ 1380 if (pmap_aliasmask) 1381 DCIS(); 1382 #endif 1383 1384 /* 1385 * Build the new PTE. 1386 */ 1387 1388 npte = pa | pte_prot(pmap, prot) | (*pte & (PG_M|PG_U)) | PG_V; 1389 if (wired) 1390 npte |= PG_W; 1391 if (!checkpv && !cacheable) 1392 #if defined(M68040) || defined(M68060) 1393 #if defined(M68020) || defined(M68030) 1394 npte |= (mmutype == MMU_68040 ? PG_CIN : PG_CI); 1395 #else 1396 npte |= PG_CIN; 1397 #endif 1398 #else 1399 npte |= PG_CI; 1400 #endif 1401 #if defined(M68040) || defined(M68060) 1402 #if defined(M68020) || defined(M68030) 1403 else if (mmutype == MMU_68040 && (npte & (PG_PROT|PG_CI)) == PG_RW) 1404 #else 1405 else if ((npte & (PG_PROT|PG_CI)) == PG_RW) 1406 #endif 1407 npte |= PG_CCB; 1408 #endif 1409 1410 PMAP_DPRINTF(PDB_ENTER, ("enter: new pte value %x\n", npte)); 1411 1412 /* 1413 * Remember if this was a wiring-only change. 1414 * If so, we need not flush the TLB and caches. 1415 */ 1416 1417 wired = ((*pte ^ npte) == PG_W); 1418 #if defined(M68040) || defined(M68060) 1419 #if defined(M68020) || defined(M68030) 1420 if (mmutype == MMU_68040 && !wired) 1421 #else 1422 if (!wired) 1423 #endif 1424 { 1425 DCFP(pa); 1426 ICPP(pa); 1427 } 1428 #endif 1429 *pte = npte; 1430 if (!wired && active_pmap(pmap)) 1431 TBIS(va); 1432 #ifdef M68K_EC_VAC 1433 /* 1434 * The following is executed if we are entering a second 1435 * (or greater) mapping for a physical page and the mappings 1436 * may create an aliasing problem. In this case we must 1437 * cache inhibit the descriptors involved and flush any 1438 * external VAC. 1439 */ 1440 if (checkpv && !cacheable) { 1441 pmap_changebit(pa, PG_CI, ~0); 1442 DCIA(); 1443 #ifdef DEBUG 1444 if ((pmapdebug & (PDB_CACHE|PDB_PVDUMP)) == 1445 (PDB_CACHE|PDB_PVDUMP)) 1446 pmap_pvdump(pa); 1447 #endif 1448 } 1449 #endif 1450 #ifdef DEBUG 1451 if ((pmapdebug & PDB_WIRING) && pmap != pmap_kernel()) 1452 pmap_check_wiring("enter", trunc_page((vaddr_t)pte)); 1453 #endif 1454 1455 if (opv != NULL) 1456 pmap_free_pv(opv); 1457 1458 return 0; 1459 } 1460 1461 void 1462 pmap_kenter_pa(vaddr_t va, paddr_t pa, vm_prot_t prot, u_int flags) 1463 { 1464 pmap_t pmap = pmap_kernel(); 1465 pt_entry_t *pte; 1466 int s, npte; 1467 1468 PMAP_DPRINTF(PDB_FOLLOW|PDB_ENTER, 1469 ("pmap_kenter_pa(%lx, %lx, %x)\n", va, pa, prot)); 1470 1471 /* 1472 * Segment table entry not valid, we need a new PT page 1473 */ 1474 1475 if (!pmap_ste_v(pmap, va)) { 1476 s = splvm(); 1477 pmap_enter_ptpage(pmap, va, false); 1478 splx(s); 1479 } 1480 1481 pa = m68k_trunc_page(pa); 1482 pte = pmap_pte(pmap, va); 1483 1484 PMAP_DPRINTF(PDB_ENTER, ("enter: pte %p, *pte %x\n", pte, *pte)); 1485 KASSERT(!pmap_pte_v(pte)); 1486 1487 /* 1488 * Increment counters 1489 */ 1490 1491 pmap->pm_stats.resident_count++; 1492 pmap->pm_stats.wired_count++; 1493 1494 /* 1495 * Build the new PTE. 1496 */ 1497 1498 npte = pa | pte_prot(pmap, prot) | PG_V | PG_W; 1499 if (flags & PMAP_NOCACHE) { 1500 npte |= PG_CI; 1501 } 1502 #if defined(M68040) || defined(M68060) 1503 #if defined(M68020) || defined(M68030) 1504 if (mmutype == MMU_68040 && (npte & (PG_PROT|PG_CI)) == PG_RW) 1505 #else 1506 if ((npte & (PG_PROT|PG_CI)) == PG_RW) 1507 #endif 1508 npte |= PG_CCB; 1509 1510 if (mmutype == MMU_68040) { 1511 DCFP(pa); 1512 ICPP(pa); 1513 } 1514 #endif 1515 1516 *pte = npte; 1517 TBIS(va); 1518 } 1519 1520 void 1521 pmap_kremove(vaddr_t va, vsize_t size) 1522 { 1523 pmap_t pmap = pmap_kernel(); 1524 pt_entry_t *pte; 1525 vaddr_t nssva; 1526 vaddr_t eva = va + size; 1527 #ifdef M68K_EC_VAC 1528 bool firstpage, needcflush; 1529 #endif 1530 1531 PMAP_DPRINTF(PDB_FOLLOW|PDB_REMOVE|PDB_PROTECT, 1532 ("pmap_kremove(%lx, %lx)\n", va, size)); 1533 1534 #ifdef M68K_EC_VAC 1535 firstpage = true; 1536 needcflush = false; 1537 #endif 1538 while (va < eva) { 1539 nssva = m68k_trunc_seg(va) + NBSEG; 1540 if (nssva == 0 || nssva > eva) 1541 nssva = eva; 1542 1543 /* 1544 * If VA belongs to an unallocated segment, 1545 * skip to the next segment boundary. 1546 */ 1547 1548 if (!pmap_ste_v(pmap, va)) { 1549 va = nssva; 1550 continue; 1551 } 1552 1553 /* 1554 * Invalidate every valid mapping within this segment. 1555 */ 1556 1557 pte = pmap_pte(pmap, va); 1558 while (va < nssva) { 1559 if (!pmap_pte_v(pte)) { 1560 pte++; 1561 va += PAGE_SIZE; 1562 continue; 1563 } 1564 #ifdef M68K_EC_VAC 1565 if (pmap_aliasmask) { 1566 1567 /* 1568 * Purge kernel side of VAC to ensure 1569 * we get the correct state of any 1570 * hardware maintained bits. 1571 */ 1572 1573 if (firstpage) { 1574 DCIS(); 1575 firstpage = false; 1576 } 1577 1578 /* 1579 * Remember if we may need to 1580 * flush the VAC. 1581 */ 1582 1583 needcflush = true; 1584 } 1585 #endif 1586 pmap->pm_stats.wired_count--; 1587 pmap->pm_stats.resident_count--; 1588 *pte = PG_NV; 1589 TBIS(va); 1590 pte++; 1591 va += PAGE_SIZE; 1592 } 1593 } 1594 1595 #ifdef M68K_EC_VAC 1596 1597 /* 1598 * In a couple of cases, we don't need to worry about flushing 1599 * the VAC: 1600 * 1. if this is a kernel mapping, 1601 * we have already done it 1602 * 2. if it is a user mapping not for the current process, 1603 * it won't be there 1604 */ 1605 1606 if (pmap_aliasmask && !active_user_pmap(pmap)) 1607 needcflush = false; 1608 if (needcflush) { 1609 if (pmap == pmap_kernel()) { 1610 DCIS(); 1611 } else { 1612 DCIU(); 1613 } 1614 } 1615 #endif 1616 } 1617 1618 /* 1619 * pmap_unwire: [ INTERFACE ] 1620 * 1621 * Clear the wired attribute for a map/virtual-address pair. 1622 * 1623 * The mapping must already exist in the pmap. 1624 */ 1625 void 1626 pmap_unwire(pmap_t pmap, vaddr_t va) 1627 { 1628 pt_entry_t *pte; 1629 1630 PMAP_DPRINTF(PDB_FOLLOW, 1631 ("pmap_unwire(%p, %lx)\n", pmap, va)); 1632 1633 pte = pmap_pte(pmap, va); 1634 1635 /* 1636 * If wiring actually changed (always?) clear the wire bit and 1637 * update the wire count. Note that wiring is not a hardware 1638 * characteristic so there is no need to invalidate the TLB. 1639 */ 1640 1641 if (pmap_pte_w_chg(pte, 0)) { 1642 pmap_pte_set_w(pte, false); 1643 pmap->pm_stats.wired_count--; 1644 } 1645 } 1646 1647 /* 1648 * pmap_extract: [ INTERFACE ] 1649 * 1650 * Extract the physical address associated with the given 1651 * pmap/virtual address pair. 1652 */ 1653 bool 1654 pmap_extract(pmap_t pmap, vaddr_t va, paddr_t *pap) 1655 { 1656 paddr_t pa; 1657 u_int pte; 1658 1659 PMAP_DPRINTF(PDB_FOLLOW, 1660 ("pmap_extract(%p, %lx) -> ", pmap, va)); 1661 1662 if (pmap_ste_v(pmap, va)) { 1663 pte = *(u_int *)pmap_pte(pmap, va); 1664 if (pte) { 1665 pa = (pte & PG_FRAME) | (va & ~PG_FRAME); 1666 if (pap != NULL) 1667 *pap = pa; 1668 #ifdef DEBUG 1669 if (pmapdebug & PDB_FOLLOW) 1670 printf("%lx\n", pa); 1671 #endif 1672 return true; 1673 } 1674 } 1675 #ifdef DEBUG 1676 if (pmapdebug & PDB_FOLLOW) 1677 printf("failed\n"); 1678 #endif 1679 return false; 1680 } 1681 1682 /* 1683 * vtophys: [ INTERFACE-ish ] 1684 * 1685 * Kernel virtual to physical. Use with caution. 1686 */ 1687 paddr_t 1688 vtophys(vaddr_t va) 1689 { 1690 paddr_t pa; 1691 1692 if (pmap_extract(pmap_kernel(), va, &pa)) 1693 return pa; 1694 KASSERT(0); 1695 return (paddr_t) -1; 1696 } 1697 1698 /* 1699 * pmap_copy: [ INTERFACE ] 1700 * 1701 * Copy the mapping range specified by src_addr/len 1702 * from the source map to the range dst_addr/len 1703 * in the destination map. 1704 * 1705 * This routine is only advisory and need not do anything. 1706 */ 1707 void 1708 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vaddr_t dst_addr, vsize_t len, 1709 vaddr_t src_addr) 1710 { 1711 1712 PMAP_DPRINTF(PDB_FOLLOW, 1713 ("pmap_copy(%p, %p, %lx, %lx, %lx)\n", 1714 dst_pmap, src_pmap, dst_addr, len, src_addr)); 1715 } 1716 1717 /* 1718 * pmap_collect1(): 1719 * 1720 * Garbage-collect KPT pages. Helper for the above (bogus) 1721 * pmap_collect(). 1722 * 1723 * Note: THIS SHOULD GO AWAY, AND BE REPLACED WITH A BETTER 1724 * WAY OF HANDLING PT PAGES! 1725 */ 1726 static inline void 1727 pmap_collect1(pmap_t pmap, paddr_t startpa, paddr_t endpa) 1728 { 1729 paddr_t pa; 1730 struct pv_header *pvh; 1731 struct pv_entry *pv; 1732 pt_entry_t *pte; 1733 paddr_t kpa; 1734 #ifdef DEBUG 1735 st_entry_t *ste; 1736 int opmapdebug = 0; 1737 #endif 1738 1739 for (pa = startpa; pa < endpa; pa += PAGE_SIZE) { 1740 struct kpt_page *kpt, **pkpt; 1741 1742 /* 1743 * Locate physical pages which are being used as kernel 1744 * page table pages. 1745 */ 1746 1747 pvh = pa_to_pvh(pa); 1748 pv = &pvh->pvh_first; 1749 if (pv->pv_pmap != pmap_kernel() || 1750 !(pvh->pvh_attrs & PVH_PTPAGE)) 1751 continue; 1752 do { 1753 if (pv->pv_ptste && pv->pv_ptpmap == pmap_kernel()) 1754 break; 1755 } while ((pv = pv->pv_next)); 1756 if (pv == NULL) 1757 continue; 1758 #ifdef DEBUG 1759 if (pv->pv_va < (vaddr_t)Sysmap || 1760 pv->pv_va >= (vaddr_t)Sysmap + M68K_MAX_PTSIZE) { 1761 printf("collect: kernel PT VA out of range\n"); 1762 pmap_pvdump(pa); 1763 continue; 1764 } 1765 #endif 1766 pte = (pt_entry_t *)(pv->pv_va + PAGE_SIZE); 1767 while (--pte >= (pt_entry_t *)pv->pv_va && *pte == PG_NV) 1768 ; 1769 if (pte >= (pt_entry_t *)pv->pv_va) 1770 continue; 1771 1772 #ifdef DEBUG 1773 if (pmapdebug & (PDB_PTPAGE|PDB_COLLECT)) { 1774 printf("collect: freeing KPT page at %lx (ste %x@%p)\n", 1775 pv->pv_va, *pv->pv_ptste, pv->pv_ptste); 1776 opmapdebug = pmapdebug; 1777 pmapdebug |= PDB_PTPAGE; 1778 } 1779 1780 ste = pv->pv_ptste; 1781 #endif 1782 /* 1783 * If all entries were invalid we can remove the page. 1784 * We call pmap_remove_entry to take care of invalidating 1785 * ST and Sysptmap entries. 1786 */ 1787 1788 if (!pmap_extract(pmap, pv->pv_va, &kpa)) { 1789 printf("collect: freeing KPT page at %lx (ste %x@%p)\n", 1790 pv->pv_va, *pv->pv_ptste, pv->pv_ptste); 1791 panic("pmap_collect: mapping not found"); 1792 } 1793 pmap_remove_mapping(pmap, pv->pv_va, NULL, 1794 PRM_TFLUSH|PRM_CFLUSH, NULL); 1795 1796 /* 1797 * Use the physical address to locate the original 1798 * (kmem_alloc assigned) address for the page and put 1799 * that page back on the free list. 1800 */ 1801 1802 for (pkpt = &kpt_used_list, kpt = *pkpt; 1803 kpt != NULL; 1804 pkpt = &kpt->kpt_next, kpt = *pkpt) 1805 if (kpt->kpt_pa == kpa) 1806 break; 1807 #ifdef DEBUG 1808 if (kpt == NULL) 1809 panic("pmap_collect: lost a KPT page"); 1810 if (pmapdebug & (PDB_PTPAGE|PDB_COLLECT)) 1811 printf("collect: %lx (%lx) to free list\n", 1812 kpt->kpt_va, kpa); 1813 #endif 1814 *pkpt = kpt->kpt_next; 1815 kpt->kpt_next = kpt_free_list; 1816 kpt_free_list = kpt; 1817 #ifdef DEBUG 1818 if (pmapdebug & (PDB_PTPAGE|PDB_COLLECT)) 1819 pmapdebug = opmapdebug; 1820 1821 if (*ste != SG_NV) 1822 printf("collect: kernel STE at %p still valid (%x)\n", 1823 ste, *ste); 1824 ste = &Sysptmap[ste - pmap_ste(pmap_kernel(), 0)]; 1825 if (*ste != SG_NV) 1826 printf("collect: kernel PTmap at %p still valid (%x)\n", 1827 ste, *ste); 1828 #endif 1829 } 1830 } 1831 1832 /* 1833 * pmap_collect: 1834 * 1835 * Helper for pmap_enter_ptpage(). 1836 * 1837 * Garbage collects the physical map system for pages which are no 1838 * longer used. Success need not be guaranteed -- that is, there 1839 * may well be pages which are not referenced, but others may be 1840 * collected. 1841 */ 1842 static void 1843 pmap_collect(void) 1844 { 1845 int s; 1846 uvm_physseg_t bank; 1847 1848 /* 1849 * XXX This is very bogus. We should handle kernel PT 1850 * XXX pages much differently. 1851 */ 1852 1853 s = splvm(); 1854 for (bank = uvm_physseg_get_first(); 1855 uvm_physseg_valid_p(bank); 1856 bank = uvm_physseg_get_next(bank)) { 1857 pmap_collect1(pmap_kernel(), ptoa(uvm_physseg_get_start(bank)), 1858 ptoa(uvm_physseg_get_end(bank))); 1859 } 1860 splx(s); 1861 } 1862 1863 /* 1864 * pmap_zero_page: [ INTERFACE ] 1865 * 1866 * Zero the specified (machine independent) page by mapping the page 1867 * into virtual memory and using memset to clear its contents, one 1868 * machine dependent page at a time. 1869 * 1870 * Note: WE DO NOT CURRENTLY LOCK THE TEMPORARY ADDRESSES! 1871 * (Actually, we go to splvm(), and since we don't 1872 * support multiple processors, this is sufficient.) 1873 */ 1874 void 1875 pmap_zero_page(paddr_t phys) 1876 { 1877 int npte; 1878 1879 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_zero_page(%lx)\n", phys)); 1880 1881 npte = phys | PG_V; 1882 #ifdef M68K_EC_VAC 1883 if (pmap_aliasmask) { 1884 1885 /* 1886 * Cache-inhibit the mapping on VAC machines, as we would 1887 * be wasting the cache load. 1888 */ 1889 1890 npte |= PG_CI; 1891 } 1892 #endif 1893 1894 #if defined(M68040) || defined(M68060) 1895 #if defined(M68020) || defined(M68030) 1896 if (mmutype == MMU_68040) 1897 #endif 1898 { 1899 /* 1900 * Set copyback caching on the page; this is required 1901 * for cache consistency (since regular mappings are 1902 * copyback as well). 1903 */ 1904 1905 npte |= PG_CCB; 1906 } 1907 #endif 1908 1909 *caddr1_pte = npte; 1910 TBIS((vaddr_t)CADDR1); 1911 1912 zeropage(CADDR1); 1913 1914 #ifdef DEBUG 1915 *caddr1_pte = PG_NV; 1916 TBIS((vaddr_t)CADDR1); 1917 #endif 1918 } 1919 1920 /* 1921 * pmap_copy_page: [ INTERFACE ] 1922 * 1923 * Copy the specified (machine independent) page by mapping the page 1924 * into virtual memory and using memcpy to copy the page, one machine 1925 * dependent page at a time. 1926 * 1927 * Note: WE DO NOT CURRENTLY LOCK THE TEMPORARY ADDRESSES! 1928 * (Actually, we go to splvm(), and since we don't 1929 * support multiple processors, this is sufficient.) 1930 */ 1931 void 1932 pmap_copy_page(paddr_t src, paddr_t dst) 1933 { 1934 pt_entry_t npte1, npte2; 1935 1936 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_copy_page(%lx, %lx)\n", src, dst)); 1937 1938 npte1 = src | PG_RO | PG_V; 1939 npte2 = dst | PG_V; 1940 #ifdef M68K_EC_VAC 1941 if (pmap_aliasmask) { 1942 1943 /* 1944 * Cache-inhibit the mapping on VAC machines, as we would 1945 * be wasting the cache load. 1946 */ 1947 1948 npte1 |= PG_CI; 1949 npte2 |= PG_CI; 1950 } 1951 #endif 1952 1953 #if defined(M68040) || defined(M68060) 1954 #if defined(M68020) || defined(M68030) 1955 if (mmutype == MMU_68040) 1956 #endif 1957 { 1958 /* 1959 * Set copyback caching on the pages; this is required 1960 * for cache consistency (since regular mappings are 1961 * copyback as well). 1962 */ 1963 1964 npte1 |= PG_CCB; 1965 npte2 |= PG_CCB; 1966 } 1967 #endif 1968 1969 *caddr1_pte = npte1; 1970 TBIS((vaddr_t)CADDR1); 1971 1972 *caddr2_pte = npte2; 1973 TBIS((vaddr_t)CADDR2); 1974 1975 copypage(CADDR1, CADDR2); 1976 1977 #ifdef DEBUG 1978 *caddr1_pte = PG_NV; 1979 TBIS((vaddr_t)CADDR1); 1980 1981 *caddr2_pte = PG_NV; 1982 TBIS((vaddr_t)CADDR2); 1983 #endif 1984 } 1985 1986 /* 1987 * pmap_clear_modify: [ INTERFACE ] 1988 * 1989 * Clear the modify bits on the specified physical page. 1990 */ 1991 bool 1992 pmap_clear_modify(struct vm_page *pg) 1993 { 1994 paddr_t pa = VM_PAGE_TO_PHYS(pg); 1995 1996 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_clear_modify(%p)\n", pg)); 1997 1998 return pmap_changebit(pa, 0, (pt_entry_t)~PG_M); 1999 } 2000 2001 /* 2002 * pmap_clear_reference: [ INTERFACE ] 2003 * 2004 * Clear the reference bit on the specified physical page. 2005 */ 2006 bool 2007 pmap_clear_reference(struct vm_page *pg) 2008 { 2009 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2010 2011 PMAP_DPRINTF(PDB_FOLLOW, ("pmap_clear_reference(%p)\n", pg)); 2012 2013 return pmap_changebit(pa, 0, (pt_entry_t)~PG_U); 2014 } 2015 2016 /* 2017 * pmap_is_referenced: [ INTERFACE ] 2018 * 2019 * Return whether or not the specified physical page is referenced 2020 * by any physical maps. 2021 */ 2022 bool 2023 pmap_is_referenced(struct vm_page *pg) 2024 { 2025 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2026 2027 return pmap_testbit(pa, PG_U); 2028 } 2029 2030 /* 2031 * pmap_is_modified: [ INTERFACE ] 2032 * 2033 * Return whether or not the specified physical page is modified 2034 * by any physical maps. 2035 */ 2036 bool 2037 pmap_is_modified(struct vm_page *pg) 2038 { 2039 paddr_t pa = VM_PAGE_TO_PHYS(pg); 2040 2041 return pmap_testbit(pa, PG_M); 2042 } 2043 2044 /* 2045 * pmap_phys_address: [ INTERFACE ] 2046 * 2047 * Return the physical address corresponding to the specified 2048 * cookie. Used by the device pager to decode a device driver's 2049 * mmap entry point return value. 2050 * 2051 * Note: no locking is necessary in this function. 2052 */ 2053 paddr_t 2054 pmap_phys_address(paddr_t ppn) 2055 { 2056 return m68k_ptob(ppn); 2057 } 2058 2059 #ifdef M68K_EC_VAC 2060 /* 2061 * pmap_prefer: [ INTERFACE ] 2062 * 2063 * Find the first virtual address >= *vap that does not 2064 * cause a virtually-addressed cache alias problem. 2065 */ 2066 void 2067 pmap_prefer(vaddr_t foff, vaddr_t *vap) 2068 { 2069 vaddr_t va; 2070 vsize_t d; 2071 2072 #ifdef M68K_MMU_MOTOROLA 2073 if (pmap_aliasmask) 2074 #endif 2075 { 2076 va = *vap; 2077 d = foff - va; 2078 d &= pmap_aliasmask; 2079 *vap = va + d; 2080 } 2081 } 2082 #endif /* M68K_EC_VAC */ 2083 2084 /* 2085 * Miscellaneous support routines follow 2086 */ 2087 2088 /* 2089 * pmap_remove_mapping: 2090 * 2091 * Invalidate a single page denoted by pmap/va. 2092 * 2093 * If (pte != NULL), it is the already computed PTE for the page. 2094 * 2095 * If (flags & PRM_TFLUSH), we must invalidate any TLB information. 2096 * 2097 * If (flags & PRM_CFLUSH), we must flush/invalidate any cache 2098 * information. 2099 * 2100 * If (flags & PRM_KEEPPTPAGE), we don't free the page table page 2101 * if the reference drops to zero. 2102 */ 2103 /* static */ 2104 void 2105 pmap_remove_mapping(pmap_t pmap, vaddr_t va, pt_entry_t *pte, int flags, 2106 struct pv_entry **opvp) 2107 { 2108 paddr_t pa; 2109 struct pv_header *pvh; 2110 struct pv_entry *pv, *npv, *opv = NULL; 2111 struct pmap *ptpmap; 2112 st_entry_t *ste; 2113 int s, bits; 2114 #ifdef DEBUG 2115 pt_entry_t opte; 2116 #endif 2117 2118 PMAP_DPRINTF(PDB_FOLLOW|PDB_REMOVE|PDB_PROTECT, 2119 ("pmap_remove_mapping(%p, %lx, %p, %x, %p)\n", 2120 pmap, va, pte, flags, opvp)); 2121 2122 /* 2123 * PTE not provided, compute it from pmap and va. 2124 */ 2125 2126 if (pte == NULL) { 2127 pte = pmap_pte(pmap, va); 2128 if (*pte == PG_NV) 2129 return; 2130 } 2131 2132 #ifdef M68K_EC_VAC 2133 if (pmap_aliasmask && (flags & PRM_CFLUSH)) { 2134 2135 /* 2136 * Purge kernel side of VAC to ensure we get the correct 2137 * state of any hardware maintained bits. 2138 */ 2139 2140 DCIS(); 2141 2142 /* 2143 * If this is a non-CI user mapping for the current process, 2144 * flush the VAC. Note that the kernel side was flushed 2145 * above so we don't worry about non-CI kernel mappings. 2146 */ 2147 2148 if (active_user_pmap(pmap) && !pmap_pte_ci(pte)) { 2149 DCIU(); 2150 } 2151 } 2152 #endif 2153 2154 pa = pmap_pte_pa(pte); 2155 #ifdef DEBUG 2156 opte = *pte; 2157 #endif 2158 2159 /* 2160 * Update statistics 2161 */ 2162 2163 if (pmap_pte_w(pte)) 2164 pmap->pm_stats.wired_count--; 2165 pmap->pm_stats.resident_count--; 2166 2167 #if defined(M68040) || defined(M68060) 2168 #if defined(M68020) || defined(M68030) 2169 if (mmutype == MMU_68040) 2170 #endif 2171 if ((flags & PRM_CFLUSH)) { 2172 DCFP(pa); 2173 ICPP(pa); 2174 } 2175 #endif 2176 2177 /* 2178 * Invalidate the PTE after saving the reference modify info. 2179 */ 2180 2181 PMAP_DPRINTF(PDB_REMOVE, ("remove: invalidating pte at %p\n", pte)); 2182 bits = *pte & (PG_U|PG_M); 2183 *pte = PG_NV; 2184 if ((flags & PRM_TFLUSH) && active_pmap(pmap)) 2185 TBIS(va); 2186 2187 /* 2188 * For user mappings decrement the wiring count on 2189 * the PT page. 2190 */ 2191 2192 if (pmap != pmap_kernel()) { 2193 vaddr_t ptpva = trunc_page((vaddr_t)pte); 2194 int refs = pmap_ptpage_delref(ptpva); 2195 #ifdef DEBUG 2196 if (pmapdebug & PDB_WIRING) 2197 pmap_check_wiring("remove", ptpva); 2198 #endif 2199 2200 /* 2201 * If reference count drops to 0, and we're not instructed 2202 * to keep it around, free the PT page. 2203 */ 2204 2205 if (refs == 0 && (flags & PRM_KEEPPTPAGE) == 0) { 2206 #ifdef DIAGNOSTIC 2207 struct pv_header *ptppvh; 2208 struct pv_entry *ptppv; 2209 #endif 2210 paddr_t ptppa; 2211 2212 ptppa = pmap_pte_pa(pmap_pte(pmap_kernel(), ptpva)); 2213 #ifdef DIAGNOSTIC 2214 if (PAGE_IS_MANAGED(ptppa) == 0) 2215 panic("pmap_remove_mapping: unmanaged PT page"); 2216 ptppvh = pa_to_pvh(ptppa); 2217 ptppv = &ptppvh->pvh_first; 2218 if (ptppv->pv_ptste == NULL) 2219 panic("pmap_remove_mapping: ptste == NULL"); 2220 if (ptppv->pv_pmap != pmap_kernel() || 2221 ptppv->pv_va != ptpva || 2222 ptppv->pv_next != NULL) 2223 panic("pmap_remove_mapping: " 2224 "bad PT page pmap %p, va 0x%lx, next %p", 2225 ptppv->pv_pmap, ptppv->pv_va, 2226 ptppv->pv_next); 2227 #endif 2228 pmap_remove_mapping(pmap_kernel(), ptpva, 2229 NULL, PRM_TFLUSH|PRM_CFLUSH, NULL); 2230 rw_enter(uvm_kernel_object->vmobjlock, RW_WRITER); 2231 uvm_pagefree(PHYS_TO_VM_PAGE(ptppa)); 2232 rw_exit(uvm_kernel_object->vmobjlock); 2233 PMAP_DPRINTF(PDB_REMOVE|PDB_PTPAGE, 2234 ("remove: PT page 0x%lx (0x%lx) freed\n", 2235 ptpva, ptppa)); 2236 } 2237 } 2238 2239 /* 2240 * If this isn't a managed page, we are all done. 2241 */ 2242 2243 if (PAGE_IS_MANAGED(pa) == 0) 2244 return; 2245 2246 /* 2247 * Otherwise remove it from the PV table 2248 * (raise IPL since we may be called at interrupt time). 2249 */ 2250 2251 pvh = pa_to_pvh(pa); 2252 pv = &pvh->pvh_first; 2253 ste = NULL; 2254 s = splvm(); 2255 2256 /* 2257 * If it is the first entry on the list, it is actually 2258 * in the header and we must copy the following entry up 2259 * to the header. Otherwise we must search the list for 2260 * the entry. In either case we free the now unused entry. 2261 */ 2262 2263 if (pmap == pv->pv_pmap && va == pv->pv_va) { 2264 ste = pv->pv_ptste; 2265 ptpmap = pv->pv_ptpmap; 2266 npv = pv->pv_next; 2267 if (npv) { 2268 *pv = *npv; 2269 opv = npv; 2270 } else 2271 pv->pv_pmap = NULL; 2272 } else { 2273 for (npv = pv->pv_next; npv; npv = npv->pv_next) { 2274 if (pmap == npv->pv_pmap && va == npv->pv_va) 2275 break; 2276 pv = npv; 2277 } 2278 #ifdef DEBUG 2279 if (npv == NULL) 2280 panic("pmap_remove: PA not in pv_tab"); 2281 #endif 2282 ste = npv->pv_ptste; 2283 ptpmap = npv->pv_ptpmap; 2284 pv->pv_next = npv->pv_next; 2285 opv = npv; 2286 pvh = pa_to_pvh(pa); 2287 pv = &pvh->pvh_first; 2288 } 2289 2290 #ifdef M68K_EC_VAC 2291 2292 /* 2293 * If only one mapping left we no longer need to cache inhibit 2294 */ 2295 2296 if (pmap_aliasmask && 2297 pv->pv_pmap && pv->pv_next == NULL && (pvh->pvh_attrs & PVH_CI)) { 2298 PMAP_DPRINTF(PDB_CACHE, 2299 ("remove: clearing CI for pa %lx\n", pa)); 2300 pvh->pvh_attrs &= ~PVH_CI; 2301 pmap_changebit(pa, 0, (pt_entry_t)~PG_CI); 2302 #ifdef DEBUG 2303 if ((pmapdebug & (PDB_CACHE|PDB_PVDUMP)) == 2304 (PDB_CACHE|PDB_PVDUMP)) 2305 pmap_pvdump(pa); 2306 #endif 2307 } 2308 #endif 2309 2310 /* 2311 * If this was a PT page we must also remove the 2312 * mapping from the associated segment table. 2313 */ 2314 2315 if (ste) { 2316 PMAP_DPRINTF(PDB_REMOVE|PDB_PTPAGE, 2317 ("remove: ste was %x@%p pte was %x@%p\n", 2318 *ste, ste, opte, pmap_pte(pmap, va))); 2319 #if defined(M68040) || defined(M68060) 2320 #if defined(M68020) || defined(M68030) 2321 if (mmutype == MMU_68040) 2322 #endif 2323 { 2324 st_entry_t *este = &ste[NPTEPG/SG4_LEV3SIZE]; 2325 2326 while (ste < este) 2327 *ste++ = SG_NV; 2328 #ifdef DEBUG 2329 ste -= NPTEPG/SG4_LEV3SIZE; 2330 #endif 2331 } 2332 #if defined(M68020) || defined(M68030) 2333 else 2334 #endif 2335 #endif 2336 #if defined(M68020) || defined(M68030) 2337 *ste = SG_NV; 2338 #endif 2339 2340 /* 2341 * If it was a user PT page, we decrement the 2342 * reference count on the segment table as well, 2343 * freeing it if it is now empty. 2344 */ 2345 2346 if (ptpmap != pmap_kernel()) { 2347 PMAP_DPRINTF(PDB_REMOVE|PDB_SEGTAB, 2348 ("remove: stab %p, refcnt %d\n", 2349 ptpmap->pm_stab, ptpmap->pm_sref - 1)); 2350 #ifdef DEBUG 2351 if ((pmapdebug & PDB_PARANOIA) && 2352 ptpmap->pm_stab != 2353 (st_entry_t *)trunc_page((vaddr_t)ste)) 2354 panic("remove: bogus ste"); 2355 #endif 2356 if (--(ptpmap->pm_sref) == 0) { 2357 PMAP_DPRINTF(PDB_REMOVE|PDB_SEGTAB, 2358 ("remove: free stab %p\n", 2359 ptpmap->pm_stab)); 2360 uvm_km_free(st_map, (vaddr_t)ptpmap->pm_stab, 2361 M68K_STSIZE, UVM_KMF_WIRED); 2362 ptpmap->pm_stab = Segtabzero; 2363 ptpmap->pm_stpa = Segtabzeropa; 2364 #if defined(M68040) || defined(M68060) 2365 #if defined(M68020) || defined(M68030) 2366 if (mmutype == MMU_68040) 2367 #endif 2368 ptpmap->pm_stfree = protostfree; 2369 #endif 2370 /* 2371 * Segment table has changed; reload the 2372 * MMU if it's the active user pmap. 2373 */ 2374 if (active_user_pmap(ptpmap)) { 2375 pmap_load_urp((paddr_t)ptpmap->pm_stpa); 2376 } 2377 } 2378 } 2379 pvh->pvh_attrs &= ~PVH_PTPAGE; 2380 ptpmap->pm_ptpages--; 2381 } 2382 2383 /* 2384 * Update saved attributes for managed page 2385 */ 2386 2387 pvh->pvh_attrs |= bits; 2388 splx(s); 2389 2390 if (opvp != NULL) 2391 *opvp = opv; 2392 else if (opv != NULL) 2393 pmap_free_pv(opv); 2394 } 2395 2396 /* 2397 * pmap_testbit: 2398 * 2399 * Test the modified/referenced bits of a physical page. 2400 */ 2401 /* static */ 2402 bool 2403 pmap_testbit(paddr_t pa, int bit) 2404 { 2405 struct pv_header *pvh; 2406 struct pv_entry *pv; 2407 pt_entry_t *pte; 2408 int s; 2409 2410 pvh = pa_to_pvh(pa); 2411 pv = &pvh->pvh_first; 2412 s = splvm(); 2413 2414 /* 2415 * Check saved info first 2416 */ 2417 2418 if (pvh->pvh_attrs & bit) { 2419 splx(s); 2420 return true; 2421 } 2422 2423 #ifdef M68K_EC_VAC 2424 2425 /* 2426 * Flush VAC to get correct state of any hardware maintained bits. 2427 */ 2428 2429 if (pmap_aliasmask && (bit & (PG_U|PG_M))) 2430 DCIS(); 2431 #endif 2432 2433 /* 2434 * Not found. Check current mappings, returning immediately if 2435 * found. Cache a hit to speed future lookups. 2436 */ 2437 2438 if (pv->pv_pmap != NULL) { 2439 for (; pv; pv = pv->pv_next) { 2440 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2441 if (*pte & bit) { 2442 pvh->pvh_attrs |= bit; 2443 splx(s); 2444 return true; 2445 } 2446 } 2447 } 2448 splx(s); 2449 return false; 2450 } 2451 2452 /* 2453 * pmap_changebit: 2454 * 2455 * Change the modified/referenced bits, or other PTE bits, 2456 * for a physical page. 2457 */ 2458 /* static */ 2459 bool 2460 pmap_changebit(paddr_t pa, pt_entry_t set, pt_entry_t mask) 2461 { 2462 struct pv_header *pvh; 2463 struct pv_entry *pv; 2464 pt_entry_t *pte, npte; 2465 vaddr_t va; 2466 int s; 2467 #if defined(M68K_EC_VAC) || defined(M68040) || defined(M68060) 2468 bool firstpage = true; 2469 #endif 2470 bool r; 2471 2472 PMAP_DPRINTF(PDB_BITS, 2473 ("pmap_changebit(%lx, %x, %x)\n", pa, set, mask)); 2474 2475 pvh = pa_to_pvh(pa); 2476 pv = &pvh->pvh_first; 2477 s = splvm(); 2478 2479 /* 2480 * Clear saved attributes (modify, reference) 2481 */ 2482 2483 r = (pvh->pvh_attrs & ~mask) != 0; 2484 pvh->pvh_attrs &= mask; 2485 2486 /* 2487 * Loop over all current mappings setting/clearing as appropriate 2488 * If setting RO do we need to clear the VAC? 2489 */ 2490 2491 if (pv->pv_pmap != NULL) { 2492 #ifdef DEBUG 2493 int toflush = 0; 2494 #endif 2495 for (; pv; pv = pv->pv_next) { 2496 #ifdef DEBUG 2497 toflush |= (pv->pv_pmap == pmap_kernel()) ? 2 : 1; 2498 #endif 2499 va = pv->pv_va; 2500 pte = pmap_pte(pv->pv_pmap, va); 2501 #ifdef M68K_EC_VAC 2502 2503 /* 2504 * Flush VAC to ensure we get correct state of HW bits 2505 * so we don't clobber them. 2506 */ 2507 2508 if (firstpage && pmap_aliasmask) { 2509 firstpage = false; 2510 DCIS(); 2511 } 2512 #endif 2513 npte = (*pte | set) & mask; 2514 if (*pte != npte) { 2515 r = true; 2516 #if defined(M68040) || defined(M68060) 2517 /* 2518 * If we are changing caching status or 2519 * protection make sure the caches are 2520 * flushed (but only once). 2521 */ 2522 if (firstpage && 2523 #if defined(M68020) || defined(M68030) 2524 (mmutype == MMU_68040) && 2525 #endif 2526 ((set == PG_RO) || 2527 (set & PG_CMASK) || 2528 (mask & PG_CMASK) == 0)) { 2529 firstpage = false; 2530 DCFP(pa); 2531 ICPP(pa); 2532 } 2533 #endif 2534 *pte = npte; 2535 if (active_pmap(pv->pv_pmap)) 2536 TBIS(va); 2537 } 2538 } 2539 } 2540 splx(s); 2541 return r; 2542 } 2543 2544 /* 2545 * pmap_enter_ptpage: 2546 * 2547 * Allocate and map a PT page for the specified pmap/va pair. 2548 */ 2549 /* static */ 2550 int 2551 pmap_enter_ptpage(pmap_t pmap, vaddr_t va, bool can_fail) 2552 { 2553 paddr_t ptpa; 2554 uint64_t ticket; 2555 struct vm_page *pg; 2556 struct pv_header *pvh; 2557 struct pv_entry *pv; 2558 st_entry_t *ste; 2559 int s; 2560 2561 PMAP_DPRINTF(PDB_FOLLOW|PDB_ENTER|PDB_PTPAGE, 2562 ("pmap_enter_ptpage: pmap %p, va %lx\n", pmap, va)); 2563 2564 /* 2565 * Allocate a segment table if necessary. Note that it is allocated 2566 * from a private map and not pt_map. This keeps user page tables 2567 * aligned on segment boundaries in the kernel address space. 2568 * The segment table is wired down. It will be freed whenever the 2569 * reference count drops to zero. 2570 */ 2571 if (pmap->pm_stab == Segtabzero) { 2572 pmap->pm_stab = (st_entry_t *) 2573 uvm_km_alloc(st_map, M68K_STSIZE, 0, 2574 UVM_KMF_WIRED | UVM_KMF_ZERO | 2575 (can_fail ? UVM_KMF_NOWAIT : 0)); 2576 if (pmap->pm_stab == NULL) { 2577 pmap->pm_stab = Segtabzero; 2578 return ENOMEM; 2579 } 2580 (void) pmap_extract(pmap_kernel(), (vaddr_t)pmap->pm_stab, 2581 (paddr_t *)&pmap->pm_stpa); 2582 #if defined(M68040) || defined(M68060) 2583 #if defined(M68020) || defined(M68030) 2584 if (mmutype == MMU_68040) 2585 #endif 2586 { 2587 pt_entry_t *pte; 2588 2589 pte = pmap_pte(pmap_kernel(), pmap->pm_stab); 2590 *pte = (*pte & ~PG_CMASK) | PG_CI; 2591 pmap->pm_stfree = protostfree; 2592 } 2593 #endif 2594 /* 2595 * Segment table has changed; reload the 2596 * MMU if it's the active user pmap. 2597 */ 2598 if (active_user_pmap(pmap)) { 2599 pmap_load_urp((paddr_t)pmap->pm_stpa); 2600 } 2601 2602 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2603 ("enter: pmap %p stab %p(%p)\n", 2604 pmap, pmap->pm_stab, pmap->pm_stpa)); 2605 } 2606 2607 ste = pmap_ste(pmap, va); 2608 #if defined(M68040) || defined(M68060) 2609 /* 2610 * Allocate level 2 descriptor block if necessary 2611 */ 2612 #if defined(M68020) || defined(M68030) 2613 if (mmutype == MMU_68040) 2614 #endif 2615 { 2616 if (*ste == SG_NV) { 2617 int ix; 2618 void *addr; 2619 2620 ix = bmtol2(pmap->pm_stfree); 2621 if (ix == -1) 2622 panic("enter: out of address space"); /* XXX */ 2623 pmap->pm_stfree &= ~l2tobm(ix); 2624 addr = (void *)&pmap->pm_stab[ix*SG4_LEV2SIZE]; 2625 memset(addr, 0, SG4_LEV2SIZE*sizeof(st_entry_t)); 2626 addr = (void *)&pmap->pm_stpa[ix*SG4_LEV2SIZE]; 2627 *ste = (u_int)addr | SG_RW | SG_U | SG_V; 2628 2629 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2630 ("enter: alloc ste2 %d(%p)\n", ix, addr)); 2631 } 2632 ste = pmap_ste2(pmap, va); 2633 /* 2634 * Since a level 2 descriptor maps a block of SG4_LEV3SIZE 2635 * level 3 descriptors, we need a chunk of NPTEPG/SG4_LEV3SIZE 2636 * (16) such descriptors (PAGE_SIZE/SG4_LEV3SIZE bytes) to map a 2637 * PT page--the unit of allocation. We set `ste' to point 2638 * to the first entry of that chunk which is validated in its 2639 * entirety below. 2640 */ 2641 ste = (st_entry_t *)((int)ste & ~(PAGE_SIZE/SG4_LEV3SIZE-1)); 2642 2643 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2644 ("enter: ste2 %p (%p)\n", pmap_ste2(pmap, va), ste)); 2645 } 2646 #endif 2647 va = trunc_page((vaddr_t)pmap_pte(pmap, va)); 2648 2649 /* 2650 * In the kernel we allocate a page from the kernel PT page 2651 * free list and map it into the kernel page table map (via 2652 * pmap_enter). 2653 */ 2654 if (pmap == pmap_kernel()) { 2655 struct kpt_page *kpt; 2656 2657 s = splvm(); 2658 if ((kpt = kpt_free_list) == NULL) { 2659 /* 2660 * No PT pages available. 2661 * Try once to free up unused ones. 2662 */ 2663 PMAP_DPRINTF(PDB_COLLECT, 2664 ("enter: no KPT pages, collecting...\n")); 2665 pmap_collect(); 2666 if ((kpt = kpt_free_list) == NULL) 2667 panic("pmap_enter_ptpage: can't get KPT page"); 2668 } 2669 kpt_free_list = kpt->kpt_next; 2670 kpt->kpt_next = kpt_used_list; 2671 kpt_used_list = kpt; 2672 ptpa = kpt->kpt_pa; 2673 memset((void *)kpt->kpt_va, 0, PAGE_SIZE); 2674 pmap_enter(pmap, va, ptpa, VM_PROT_READ | VM_PROT_WRITE, 2675 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 2676 pmap_update(pmap); 2677 #ifdef DEBUG 2678 if (pmapdebug & (PDB_ENTER|PDB_PTPAGE)) { 2679 int ix = pmap_ste(pmap, va) - pmap_ste(pmap, 0); 2680 2681 printf("enter: add &Sysptmap[%d]: %x (KPT page %lx)\n", 2682 ix, Sysptmap[ix], kpt->kpt_va); 2683 } 2684 #endif 2685 splx(s); 2686 } else { 2687 /* 2688 * For user processes we just allocate a page from the 2689 * VM system. Note that we set the page "wired" count to 1, 2690 * which is what we use to check if the page can be freed. 2691 * See pmap_remove_mapping(). 2692 * 2693 * Count the segment table reference first so that we won't 2694 * lose the segment table when low on memory. 2695 */ 2696 2697 pmap->pm_sref++; 2698 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE, 2699 ("enter: about to alloc UPT pg at %lx\n", va)); 2700 rw_enter(uvm_kernel_object->vmobjlock, RW_WRITER); 2701 while (ticket = uvm_wait_prepare(), 2702 (pg = uvm_pagealloc(uvm_kernel_object, 2703 va - vm_map_min(kernel_map), 2704 NULL, UVM_PGA_ZERO)) == NULL) { 2705 rw_exit(uvm_kernel_object->vmobjlock); 2706 if (can_fail) { 2707 pmap->pm_sref--; 2708 return ENOMEM; 2709 } 2710 uvm_wait("ptpage", ticket); 2711 rw_enter(uvm_kernel_object->vmobjlock, RW_WRITER); 2712 } 2713 rw_exit(uvm_kernel_object->vmobjlock); 2714 pg->flags &= ~(PG_BUSY|PG_FAKE); 2715 UVM_PAGE_OWN(pg, NULL); 2716 ptpa = VM_PAGE_TO_PHYS(pg); 2717 pmap_enter(pmap_kernel(), va, ptpa, 2718 VM_PROT_READ | VM_PROT_WRITE, 2719 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 2720 pmap_update(pmap_kernel()); 2721 } 2722 #if defined(M68040) || defined(M68060) 2723 /* 2724 * Turn off copyback caching of page table pages, 2725 * could get ugly otherwise. 2726 */ 2727 #if defined(M68020) || defined(M68030) 2728 if (mmutype == MMU_68040) 2729 #endif 2730 { 2731 #ifdef DEBUG 2732 pt_entry_t *pte = pmap_pte(pmap_kernel(), va); 2733 if ((pmapdebug & PDB_PARANOIA) && (*pte & PG_CCB) == 0) 2734 printf("%s PT no CCB: kva=%lx ptpa=%lx pte@%p=%x\n", 2735 pmap == pmap_kernel() ? "Kernel" : "User", 2736 va, ptpa, pte, *pte); 2737 #endif 2738 if (pmap_changebit(ptpa, PG_CI, (pt_entry_t)~PG_CCB)) 2739 DCIS(); 2740 } 2741 #endif 2742 /* 2743 * Locate the PV entry in the kernel for this PT page and 2744 * record the STE address. This is so that we can invalidate 2745 * the STE when we remove the mapping for the page. 2746 */ 2747 pvh = pa_to_pvh(ptpa); 2748 s = splvm(); 2749 if (pvh) { 2750 pv = &pvh->pvh_first; 2751 pvh->pvh_attrs |= PVH_PTPAGE; 2752 do { 2753 if (pv->pv_pmap == pmap_kernel() && pv->pv_va == va) 2754 break; 2755 } while ((pv = pv->pv_next)); 2756 } else { 2757 pv = NULL; 2758 } 2759 #ifdef DEBUG 2760 if (pv == NULL) 2761 panic("pmap_enter_ptpage: PT page not entered"); 2762 #endif 2763 pv->pv_ptste = ste; 2764 pv->pv_ptpmap = pmap; 2765 2766 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE, 2767 ("enter: new PT page at PA %lx, ste at %p\n", ptpa, ste)); 2768 2769 /* 2770 * Map the new PT page into the segment table. 2771 * Also increment the reference count on the segment table if this 2772 * was a user page table page. Note that we don't use vm_map_pageable 2773 * to keep the count like we do for PT pages, this is mostly because 2774 * it would be difficult to identify ST pages in pmap_pageable to 2775 * release them. We also avoid the overhead of vm_map_pageable. 2776 */ 2777 #if defined(M68040) || defined(M68060) 2778 #if defined(M68020) || defined(M68030) 2779 if (mmutype == MMU_68040) 2780 #endif 2781 { 2782 st_entry_t *este; 2783 2784 for (este = &ste[NPTEPG/SG4_LEV3SIZE]; ste < este; ste++) { 2785 *ste = ptpa | SG_U | SG_RW | SG_V; 2786 ptpa += SG4_LEV3SIZE * sizeof(st_entry_t); 2787 } 2788 } 2789 #if defined(M68020) || defined(M68030) 2790 else 2791 *ste = (ptpa & SG_FRAME) | SG_RW | SG_V; 2792 #endif 2793 #else 2794 *ste = (ptpa & SG_FRAME) | SG_RW | SG_V; 2795 #endif 2796 if (pmap != pmap_kernel()) { 2797 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2798 ("enter: stab %p refcnt %d\n", 2799 pmap->pm_stab, pmap->pm_sref)); 2800 } 2801 /* 2802 * Flush stale TLB info. 2803 */ 2804 if (pmap == pmap_kernel()) 2805 TBIAS(); 2806 else 2807 TBIAU(); 2808 pmap->pm_ptpages++; 2809 splx(s); 2810 2811 return 0; 2812 } 2813 2814 /* 2815 * pmap_ptpage_addref: 2816 * 2817 * Add a reference to the specified PT page. 2818 */ 2819 void 2820 pmap_ptpage_addref(vaddr_t ptpva) 2821 { 2822 struct vm_page *pg; 2823 2824 rw_enter(uvm_kernel_object->vmobjlock, RW_WRITER); 2825 pg = uvm_pagelookup(uvm_kernel_object, ptpva - vm_map_min(kernel_map)); 2826 pg->wire_count++; 2827 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2828 ("ptpage addref: pg %p now %d\n", 2829 pg, pg->wire_count)); 2830 rw_exit(uvm_kernel_object->vmobjlock); 2831 } 2832 2833 /* 2834 * pmap_ptpage_delref: 2835 * 2836 * Delete a reference to the specified PT page. 2837 */ 2838 int 2839 pmap_ptpage_delref(vaddr_t ptpva) 2840 { 2841 struct vm_page *pg; 2842 int rv; 2843 2844 rw_enter(uvm_kernel_object->vmobjlock, RW_WRITER); 2845 pg = uvm_pagelookup(uvm_kernel_object, ptpva - vm_map_min(kernel_map)); 2846 rv = --pg->wire_count; 2847 PMAP_DPRINTF(PDB_ENTER|PDB_PTPAGE|PDB_SEGTAB, 2848 ("ptpage delref: pg %p now %d\n", 2849 pg, pg->wire_count)); 2850 rw_exit(uvm_kernel_object->vmobjlock); 2851 return rv; 2852 } 2853 2854 /* 2855 * Routine: pmap_procwr 2856 * 2857 * Function: 2858 * Synchronize caches corresponding to [addr, addr + len) in p. 2859 */ 2860 void 2861 pmap_procwr(struct proc *p, vaddr_t va, size_t len) 2862 { 2863 2864 (void)cachectl1(0x80000004, va, len, p); 2865 } 2866 2867 #if defined(DDB) || defined(KGDB) 2868 /* 2869 * Routine: pmap_db_write_text_enter 2870 * 2871 * Function: 2872 * Temporarily map a page of kernel text read-write for the 2873 * kernel debugger. 2874 */ 2875 bool 2876 pmap_db_write_text_enter(vaddr_t pgva, struct pmap_db_write_text_context *ctx) 2877 { 2878 volatile pt_entry_t *pte; 2879 pt_entry_t oldpte, tmppte; 2880 2881 #ifdef M68K_MMU_HP 2882 /* 2883 * Flush the supervisor side of the VAC to 2884 * prevent a cache hit on the old, read-only PTE. 2885 */ 2886 if (ectype == EC_VIRT) 2887 DCIS(); 2888 #endif 2889 2890 /* 2891 * N.B. we use the 68851 PTE bit names here, but in 2892 * the case of the kernel text, it all works out vis 2893 * a vis the 68040 PTE bits. 2894 * 2895 * Note the mapping is cache-inhibited to save hair. 2896 */ 2897 pte = kvtopte(pgva); 2898 oldpte = *pte; 2899 if ((oldpte & DT51_PAGE) == 0) { 2900 return false; 2901 } 2902 2903 tmppte = (oldpte & ~PTE51_WP) | PTE51_CI; 2904 *pte = tmppte; 2905 TBIS(pgva); 2906 2907 ctx->pgva = pgva; 2908 ctx->ptep = pte; 2909 ctx->opte = oldpte; 2910 2911 return true; 2912 } 2913 2914 /* 2915 * Routine: pmap_db_write_text_exit 2916 * 2917 * Function: 2918 * Undo the effects of pmap_db_write_text_enter(). 2919 */ 2920 void 2921 pmap_db_write_text_exit(struct pmap_db_write_text_context *ctx) 2922 { 2923 *ctx->ptep = ctx->opte; 2924 TBIS(ctx->pgva); 2925 } 2926 #endif /* DDB || KGDB */ 2927 2928 void 2929 _pmap_set_page_cacheable(pmap_t pmap, vaddr_t va) 2930 { 2931 2932 if (!pmap_ste_v(pmap, va)) 2933 return; 2934 2935 #if defined(M68040) || defined(M68060) 2936 #if defined(M68020) || defined(M68030) 2937 if (mmutype == MMU_68040) { 2938 #endif 2939 if (pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), PG_CCB, 2940 (pt_entry_t)~PG_CI)) 2941 DCIS(); 2942 2943 #if defined(M68020) || defined(M68030) 2944 } else 2945 pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), 0, 2946 (pt_entry_t)~PG_CI); 2947 #endif 2948 #else 2949 pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), 0, 2950 (pt_entry_t)~PG_CI); 2951 #endif 2952 } 2953 2954 void 2955 _pmap_set_page_cacheinhibit(pmap_t pmap, vaddr_t va) 2956 { 2957 2958 if (!pmap_ste_v(pmap, va)) 2959 return; 2960 2961 #if defined(M68040) || defined(M68060) 2962 #if defined(M68020) || defined(M68030) 2963 if (mmutype == MMU_68040) { 2964 #endif 2965 if (pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), PG_CI, 2966 (pt_entry_t)~PG_CCB)) 2967 DCIS(); 2968 #if defined(M68020) || defined(M68030) 2969 } else 2970 pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), PG_CI, ~0); 2971 #endif 2972 #else 2973 pmap_changebit(pmap_pte_pa(pmap_pte(pmap, va)), PG_CI, ~0); 2974 #endif 2975 } 2976 2977 int 2978 _pmap_page_is_cacheable(pmap_t pmap, vaddr_t va) 2979 { 2980 2981 if (!pmap_ste_v(pmap, va)) 2982 return 0; 2983 2984 return (pmap_pte_ci(pmap_pte(pmap, va)) == 0) ? 1 : 0; 2985 } 2986 2987 vaddr_t kernel_reloc_offset; 2988 2989 /* 2990 * pmap_init_kcore_hdr: 2991 * 2992 * Initialize the m68k kernel crash dump header with information 2993 * necessary to perform KVA -> phys translations. 2994 * 2995 * Returns a pointer to the crash dump RAM segment entries for 2996 * machine-specific code to initialize. 2997 */ 2998 phys_ram_seg_t * 2999 pmap_init_kcore_hdr(cpu_kcore_hdr_t *h) 3000 { 3001 struct m68k_kcore_hdr *m = &h->un._m68k; 3002 extern char end[]; 3003 3004 memset(h, 0, sizeof(*h)); 3005 3006 /* 3007 * Initialize the `dispatcher' portion of the header. 3008 */ 3009 strcpy(h->name, machine); 3010 h->page_size = PAGE_SIZE; 3011 h->kernbase = KERNBASE; 3012 3013 /* 3014 * Fill in information about our MMU configuration. 3015 */ 3016 m->mmutype = mmutype; 3017 m->sg_v = SG_V; 3018 m->sg_frame = SG_FRAME; 3019 m->sg_ishift = SG_ISHIFT; 3020 m->sg_pmask = SG_PMASK; 3021 m->sg40_shift1 = SG4_SHIFT1; 3022 m->sg40_mask2 = SG4_MASK2; 3023 m->sg40_shift2 = SG4_SHIFT2; 3024 m->sg40_mask3 = SG4_MASK3; 3025 m->sg40_shift3 = SG4_SHIFT3; 3026 m->sg40_addr1 = SG4_ADDR1; 3027 m->sg40_addr2 = SG4_ADDR2; 3028 m->pg_v = PG_V; 3029 m->pg_frame = PG_FRAME; 3030 3031 /* 3032 * Initialize pointer to kernel segment table. 3033 */ 3034 m->sysseg_pa = Sysseg_pa; 3035 3036 /* 3037 * Initialize relocation value such that: 3038 * 3039 * pa = (va - KERNBASE) + reloc 3040 */ 3041 m->reloc = kernel_reloc_offset; 3042 3043 /* 3044 * Define the end of the relocatable range. 3045 */ 3046 m->relocend = (uint32_t)end; 3047 3048 return m->ram_segs; 3049 } 3050 3051 #ifdef DEBUG 3052 /* 3053 * pmap_pvdump: 3054 * 3055 * Dump the contents of the PV list for the specified physical page. 3056 */ 3057 void 3058 pmap_pvdump(paddr_t pa) 3059 { 3060 struct pv_header *pvh; 3061 struct pv_entry *pv; 3062 3063 printf("pa %lx", pa); 3064 pvh = pa_to_pvh(pa); 3065 for (pv = &pvh->pvh_first; pv; pv = pv->pv_next) 3066 printf(" -> pmap %p, va %lx, ptste %p, ptpmap %p", 3067 pv->pv_pmap, pv->pv_va, pv->pv_ptste, pv->pv_ptpmap); 3068 printf("\n"); 3069 } 3070 3071 /* 3072 * pmap_check_wiring: 3073 * 3074 * Count the number of valid mappings in the specified PT page, 3075 * and ensure that it is consistent with the number of wirings 3076 * to that page that the VM system has. 3077 */ 3078 void 3079 pmap_check_wiring(const char *str, vaddr_t va) 3080 { 3081 pt_entry_t *pte; 3082 paddr_t pa; 3083 struct vm_page *pg; 3084 int count; 3085 3086 if (!pmap_ste_v(pmap_kernel(), va) || 3087 !pmap_pte_v(pmap_pte(pmap_kernel(), va))) 3088 return; 3089 3090 pa = pmap_pte_pa(pmap_pte(pmap_kernel(), va)); 3091 pg = PHYS_TO_VM_PAGE(pa); 3092 if (pg->wire_count > PAGE_SIZE / sizeof(pt_entry_t)) { 3093 panic("*%s*: 0x%lx: wire count %d", str, va, pg->wire_count); 3094 } 3095 3096 count = 0; 3097 for (pte = (pt_entry_t *)va; pte < (pt_entry_t *)(va + PAGE_SIZE); 3098 pte++) 3099 if (*pte) 3100 count++; 3101 if (pg->wire_count != count) 3102 panic("*%s*: 0x%lx: w%d/a%d", 3103 str, va, pg->wire_count, count); 3104 } 3105 #endif /* DEBUG */ 3106 3107 /* 3108 * XXX XXX XXX These are legacy remants and should go away XXX XXX XXX 3109 * (Cribbed from vm_machdep.c because they're tied to this pmap impl.) 3110 */ 3111 3112 /* 3113 * Map `size' bytes of physical memory starting at `paddr' into 3114 * kernel VA space at `vaddr'. Read/write and cache-inhibit status 3115 * are specified by `prot'. 3116 */ 3117 void 3118 physaccess(void *vaddr, void *paddr, int size, int prot) 3119 { 3120 pt_entry_t *pte; 3121 u_int page; 3122 3123 pte = kvtopte(vaddr); 3124 page = (u_int)paddr & PG_FRAME; 3125 for (size = btoc(size); size; size--) { 3126 *pte++ = PG_V | prot | page; 3127 page += PAGE_SIZE; 3128 } 3129 TBIAS(); 3130 } 3131 3132 void 3133 physunaccess(void *vaddr, int size) 3134 { 3135 pt_entry_t *pte; 3136 3137 pte = kvtopte(vaddr); 3138 for (size = btoc(size); size; size--) 3139 *pte++ = PG_NV; 3140 TBIAS(); 3141 } 3142 3143 /* 3144 * Convert kernel VA to physical address 3145 */ 3146 int 3147 kvtop(void *addr) 3148 { 3149 return (int)vtophys((vaddr_t)addr); 3150 } 3151 3152 /* 3153 * pmap_pa_has_static_mapping: 3154 * 3155 * Returns true if the specified PA (and length) has a static 3156 * mapping, and what that mapping is and its properties. 3157 */ 3158 bool 3159 pmap_pa_has_static_mapping(paddr_t pa, size_t len, vm_prot_t prot, 3160 vaddr_t *vap, int *flagsp) 3161 { 3162 #if defined(M68030) || defined(M68040) || defined(M68060) 3163 /* First, check for Transparent Translation. */ 3164 if (cputype >= CPU_68030 && 3165 mmu_range_is_tt(pa, len, prot, flagsp)) { 3166 *vap = pa; 3167 return true; 3168 } 3169 #endif 3170 3171 const struct pmap_bootmap *pmbm = machine_bootmap; 3172 paddr_t lastpg = m68k_btop(pa + (len - 1)); 3173 paddr_t firstpg = m68k_btop(pa); 3174 paddr_t tfirst, tlast; 3175 vaddr_t tblva; 3176 bool need_write = !!(prot & UVM_PROT_WRITE); 3177 3178 for (; pmbm->pmbm_vaddr != (vaddr_t)-1; pmbm++) { 3179 if (pmbm->pmbm_flags & (PMBM_F_VAONLY|PMBM_F_KEEPOUT)) { 3180 continue; 3181 } 3182 if (pmbm->pmbm_flags & PMBM_F_FIXEDVA) { 3183 tblva = pmbm->pmbm_vaddr; 3184 } else { 3185 tblva = *pmbm->pmbm_vaddr_ptr; 3186 } 3187 tfirst = m68k_btop(pmbm->pmbm_paddr); 3188 tlast = m68k_btop(pmbm->pmbm_paddr + (pmbm->pmbm_size - 1)); 3189 3190 if (firstpg >= tfirst && lastpg <= tlast) { 3191 if (need_write && 3192 (pmbm->pmbm_flags & PMBM_F_RO) != 0) { 3193 return false; 3194 } 3195 *vap = tblva + (pa - pmbm->pmbm_paddr); 3196 if (pmbm->pmbm_flags & PMBM_F_CI) { 3197 *flagsp = PMAP_NOCACHE; 3198 } else { 3199 *flagsp = 0; 3200 } 3201 return true; 3202 } 3203 } 3204 3205 return false; 3206 } 3207 3208 /* 3209 * pmap_va_is_static_mapping: 3210 * 3211 * Returns true if the specified VA (and length) is a static 3212 * mapping. 3213 */ 3214 bool 3215 pmap_va_is_static_mapping(vaddr_t va, size_t len) 3216 { 3217 #if defined(M68030) || defined(M68040) || defined(M68060) 3218 int map_flags; 3219 3220 /* First, check for Transparent Translation. */ 3221 if (cputype >= CPU_68030 && 3222 (mmu_range_is_tt(va, len, UVM_PROT_READ, &map_flags) || 3223 mmu_range_is_tt(va, len, UVM_PROT_WRITE, &map_flags) || 3224 mmu_range_is_tt(va, len, UVM_PROT_EXEC, &map_flags))) { 3225 return true; 3226 } 3227 #endif 3228 3229 const struct pmap_bootmap *pmbm = machine_bootmap; 3230 vaddr_t lastpg = m68k_btop(va + (len - 1)); 3231 vaddr_t firstpg = m68k_btop(va); 3232 vaddr_t tblva, tfirst, tlast; 3233 for (; pmbm->pmbm_vaddr != (vaddr_t)-1; pmbm++) { 3234 if (pmbm->pmbm_flags & (PMBM_F_VAONLY|PMBM_F_KEEPOUT)) { 3235 continue; 3236 } 3237 if (pmbm->pmbm_flags & PMBM_F_FIXEDVA) { 3238 tblva = pmbm->pmbm_vaddr; 3239 } else { 3240 tblva = *pmbm->pmbm_vaddr_ptr; 3241 } 3242 tfirst = m68k_btop(tblva); 3243 tlast = m68k_btop(tblva + (pmbm->pmbm_size - 1)); 3244 3245 if (firstpg >= tfirst && lastpg <= tlast) { 3246 return true; 3247 } 3248 } 3249 3250 return false; 3251 } 3252
Indexes created Sun Oct 25 00:26:45 UTC 2026