1 /* $NetBSD: machdep.c,v 1.50 2026/02/25 11:57:46 jmcneill Exp $ */ 2 /*- 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 9 * 10 * This material is based upon work supported by the Defense Advanced Research 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 12 * Contract No. N66001-09-C-2073. 13 * Approved for Public Release, Distribution Unlimited 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 39 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.50 2026/02/25 11:57:46 jmcneill Exp $"); 40 41 #include "opt_altivec.h" 42 #include "opt_ddb.h" 43 #include "opt_mpc85xx.h" 44 #include "opt_multiprocessor.h" 45 #include "opt_pci.h" 46 #include "gpio.h" 47 #include "pci.h" 48 49 #define DDRC_PRIVATE 50 #define GLOBAL_PRIVATE 51 #define L2CACHE_PRIVATE 52 #define _POWERPC_BUS_DMA_PRIVATE 53 54 #include <sys/param.h> 55 #include <sys/cpu.h> 56 #include <sys/intr.h> 57 #include <sys/msgbuf.h> 58 #include <sys/tty.h> 59 #include <sys/kcore.h> 60 #include <sys/bitops.h> 61 #include <sys/bus.h> 62 #include <sys/extent.h> 63 #include <sys/reboot.h> 64 #include <sys/module.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <prop/proplib.h> 69 70 #include <dev/cons.h> 71 72 #include <dev/ic/comreg.h> 73 #include <dev/ic/comvar.h> 74 75 #include <net/if.h> 76 #include <net/if_media.h> 77 #include <dev/mii/miivar.h> 78 79 #include <machine/powerpc.h> 80 81 #include <powerpc/pcb.h> 82 #include <powerpc/spr.h> 83 #include <powerpc/booke/spr.h> 84 85 #include <powerpc/booke/cpuvar.h> 86 #include <powerpc/booke/e500reg.h> 87 #include <powerpc/booke/e500var.h> 88 #include <powerpc/booke/etsecreg.h> 89 #include <powerpc/booke/openpicreg.h> 90 #ifdef CADMUS 91 #include <evbppc/mpc85xx/cadmusreg.h> 92 #endif 93 #ifdef PIXIS 94 #include <evbppc/mpc85xx/pixisreg.h> 95 #endif 96 97 struct uboot_bdinfo { 98 uint32_t bd_memstart; 99 uint32_t bd_memsize; 100 uint32_t bd_flashstart; 101 uint32_t bd_flashsize; 102 /*10*/ uint32_t bd_flashoffset; 103 uint32_t bd_sramstart; 104 uint32_t bd_sramsize; 105 uint32_t bd_immrbase; 106 /*20*/ uint32_t bd_bootflags; 107 uint32_t bd_ipaddr; 108 uint8_t bd_etheraddr[6]; 109 uint16_t bd_ethspeed; 110 /*30*/ uint32_t bd_intfreq; 111 uint32_t bd_cpufreq; 112 uint32_t bd_baudrate; 113 /*3c*/ uint8_t bd_etheraddr1[6]; 114 /*42*/ uint8_t bd_etheraddr2[6]; 115 /*48*/ uint8_t bd_etheraddr3[6]; 116 /*4e*/ uint16_t bd_pad; 117 }; 118 119 char root_string[16]; 120 121 /* 122 * booke kernels need to set module_machine to this for modules to work. 123 */ 124 char module_machine_booke[] = "powerpc-booke"; 125 126 void initppc(vaddr_t, vaddr_t, void *, void *, char *, char *); 127 128 #define MEMREGIONS 4 129 phys_ram_seg_t physmemr[MEMREGIONS]; /* All memory */ 130 phys_ram_seg_t availmemr[2*MEMREGIONS]; /* Available memory */ 131 static struct mem_region phys_region[MEMREGIONS]; 132 static struct mem_region avail_region[2*MEMREGIONS]; 133 static u_int nmemr; 134 135 #ifndef CONSFREQ 136 # define CONSFREQ -1 /* inherit from firmware */ 137 #endif 138 #ifndef CONSPEED 139 # define CONSPEED 115200 140 #endif 141 #ifndef CONMODE 142 # define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) 143 #endif 144 #ifndef CONSADDR 145 # define CONSADDR DUART2_BASE 146 #endif 147 148 int comcnfreq = CONSFREQ; 149 int comcnspeed = CONSPEED; 150 tcflag_t comcnmode = CONMODE; 151 bus_addr_t comcnaddr = (bus_addr_t)CONSADDR; 152 153 #if NPCI > 0 154 struct extent *pcimem_ex; 155 struct extent *pciio_ex; 156 #endif 157 158 struct powerpc_bus_space gur_bst = { 159 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE, 160 .pbs_offset = GUR_BASE, 161 .pbs_limit = GUR_SIZE, 162 }; 163 164 struct powerpc_bus_space gur_le_bst = { 165 .pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE, 166 .pbs_offset = GUR_BASE, 167 .pbs_limit = GUR_SIZE, 168 }; 169 170 const bus_space_handle_t gur_bsh = (bus_space_handle_t)(uintptr_t)(GUR_BASE); 171 172 #if defined(SYS_CLK) 173 static uint64_t e500_sys_clk = SYS_CLK; 174 #endif 175 #ifdef CADMUS 176 static uint8_t cadmus_pci; 177 static uint8_t cadmus_csr; 178 #ifndef SYS_CLK 179 static uint64_t e500_sys_clk = 33333333; /* 33.333333Mhz */ 180 #endif 181 #elif defined(PIXIS) 182 static const uint32_t pixis_spd_map[8] = { 183 [PX_SPD_33MHZ] = 33333333, 184 [PX_SPD_40MHZ] = 40000000, 185 [PX_SPD_50MHZ] = 50000000, 186 [PX_SPD_66MHZ] = 66666666, 187 [PX_SPD_83MHZ] = 83333333, 188 [PX_SPD_100MHZ] = 100000000, 189 [PX_SPD_133MHZ] = 133333333, 190 [PX_SPD_166MHZ] = 166666667, 191 }; 192 static uint8_t pixis_spd; 193 #ifndef SYS_CLK 194 static uint64_t e500_sys_clk; 195 #endif 196 #elif !defined(SYS_CLK) 197 static uint64_t e500_sys_clk = 66666667; /* 66.666667Mhz */ 198 #endif 199 200 static int e500_cngetc(dev_t); 201 static void e500_cnputc(dev_t, int); 202 203 static struct consdev e500_earlycons = { 204 .cn_getc = e500_cngetc, 205 .cn_putc = e500_cnputc, 206 .cn_pollc = nullcnpollc, 207 }; 208 209 /* 210 * List of port-specific devices to attach to the processor local bus. 211 */ 212 static const struct cpunode_locators mpc8548_cpunode_locs[] = { 213 { "cpu", 0, 0, 0, 0, { 0 }, 0, /* not a real device */ 214 { 0xffff, SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 215 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 216 #if defined(MPC8572) || defined(P2020) || defined(P1025) \ 217 || defined(P1023) 218 { "cpu", 0, 0, 1, 0, { 0 }, 0, /* not a real device */ 219 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 220 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 221 { "cpu", 0, 0, 2, 0, { 0 }, 0, /* not a real device */ 222 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 223 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 224 #endif 225 { "wdog" }, /* not a real device */ 226 { "duart", DUART1_BASE, 2*DUART_SIZE, 0, 227 1, { ISOURCE_DUART }, 228 1 + ilog2(DEVDISR_DUART) }, 229 { "tsec", ETSEC1_BASE, ETSEC_SIZE, 1, 230 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 231 1 + ilog2(DEVDISR_TSEC1), 232 { 0xffff, SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 233 #if defined(P1025) 234 { "mdio", ETSEC1_BASE, ETSEC_SIZE, 1, 235 0, { }, 236 1 + ilog2(DEVDISR_TSEC1), 237 { SVR_P1025v1 >> 16 } }, 238 { "tsec", ETSEC1_G0_BASE, ETSEC_SIZE, 1, 239 3, { ISOURCE_ETSEC1_TX, ISOURCE_ETSEC1_RX, ISOURCE_ETSEC1_ERR }, 240 1 + ilog2(DEVDISR_TSEC1), 241 { SVR_P1025v1 >> 16 } }, 242 #if 0 243 { "tsec", ETSEC1_G1_BASE, ETSEC_SIZE, 1, 244 3, { ISOURCE_ETSEC1_G1_TX, ISOURCE_ETSEC1_G1_RX, 245 ISOURCE_ETSEC1_G1_ERR }, 246 1 + ilog2(DEVDISR_TSEC1), 247 { SVR_P1025v1 >> 16 } }, 248 #endif 249 #endif 250 #if defined(MPC8548) || defined(MPC8555) || defined(MPC8572) \ 251 || defined(P2020) 252 { "tsec", ETSEC2_BASE, ETSEC_SIZE, 2, 253 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 254 1 + ilog2(DEVDISR_TSEC2), 255 { SVR_MPC8548v1 >> 16, SVR_MPC8555v1 >> 16, 256 SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 257 SVR_P1025v1 >> 16 } }, 258 #endif 259 #if defined(P1025) 260 { "mdio", ETSEC2_BASE, ETSEC_SIZE, 2, 261 0, { }, 262 1 + ilog2(DEVDISR_TSEC2), 263 { SVR_P1025v1 >> 16 } }, 264 { "tsec", ETSEC2_G0_BASE, ETSEC_SIZE, 2, 265 3, { ISOURCE_ETSEC2_TX, ISOURCE_ETSEC2_RX, ISOURCE_ETSEC2_ERR }, 266 1 + ilog2(DEVDISR_TSEC2), 267 { SVR_P1025v1 >> 16 } }, 268 #if 0 269 { "tsec", ETSEC2_G1_BASE, ETSEC_SIZE, 5, 270 3, { ISOURCE_ETSEC2_G1_TX, ISOURCE_ETSEC2_G1_RX, 271 ISOURCE_ETSEC2_G1_ERR }, 272 1 + ilog2(DEVDISR_TSEC2), 273 { SVR_P1025v1 >> 16 } }, 274 #endif 275 #endif 276 #if defined(MPC8544) || defined(MPC8536) 277 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 2, 278 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 279 1 + ilog2(DEVDISR_TSEC3), 280 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 281 #endif 282 #if defined(MPC8548) || defined(MPC8572) || defined(P2020) 283 { "tsec", ETSEC3_BASE, ETSEC_SIZE, 3, 284 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 285 1 + ilog2(DEVDISR_TSEC3), 286 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16, 287 SVR_P2020v2 >> 16 } }, 288 #endif 289 #if defined(P1025) 290 { "mdio", ETSEC3_BASE, ETSEC_SIZE, 3, 291 0, { }, 292 1 + ilog2(DEVDISR_TSEC3), 293 { SVR_P1025v1 >> 16 } }, 294 { "tsec", ETSEC3_G0_BASE, ETSEC_SIZE, 3, 295 3, { ISOURCE_ETSEC3_TX, ISOURCE_ETSEC3_RX, ISOURCE_ETSEC3_ERR }, 296 1 + ilog2(DEVDISR_TSEC3), 297 { SVR_P1025v1 >> 16 } }, 298 #if 0 299 { "tsec", ETSEC3_G1_BASE, ETSEC_SIZE, 3, 300 3, { ISOURCE_ETSEC3_G1_TX, ISOURCE_ETSEC3_G1_RX, 301 ISOURCE_ETSEC3_G1_ERR }, 302 1 + ilog2(DEVDISR_TSEC3), 303 { SVR_P1025v1 >> 16 } }, 304 #endif 305 #endif 306 #if defined(MPC8548) || defined(MPC8572) 307 { "tsec", ETSEC4_BASE, ETSEC_SIZE, 4, 308 3, { ISOURCE_ETSEC4_TX, ISOURCE_ETSEC4_RX, ISOURCE_ETSEC4_ERR }, 309 1 + ilog2(DEVDISR_TSEC4), 310 { SVR_MPC8548v1 >> 16, SVR_MPC8572v1 >> 16 } }, 311 #endif 312 { "diic", I2C1_BASE, I2C_SIZE, 0, 313 1, { ISOURCE_I2C }, 314 1 + ilog2(DEVDISR_I2C) }, 315 { "diic", I2C2_BASE, I2C_SIZE, 1, 316 1, { ISOURCE_I2C }, 317 1 + ilog2(DEVDISR_I2C) }, 318 /* MPC8572 doesn't have any GPIO */ 319 { "gpio", GLOBAL_BASE, GLOBAL_SIZE, 0, 320 1, { ISOURCE_GPIO }, 321 0, 322 { 0xffff, SVR_MPC8572v1 >> 16 } }, 323 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 324 1, { ISOURCE_DDR }, 325 1 + ilog2(DEVDISR_DDR_15), 326 { 0xffff, SVR_MPC8572v1 >> 16, SVR_MPC8536v1 >> 16 } }, 327 #if defined(MPC8536) 328 { "ddrc", DDRC1_BASE, DDRC_SIZE, 0, 329 1, { ISOURCE_DDR }, 330 1 + ilog2(DEVDISR_DDR_16), 331 { SVR_MPC8536v1 >> 16 } }, 332 #endif 333 #if defined(MPC8572) 334 { "ddrc", DDRC1_BASE, DDRC_SIZE, 1, 335 1, { ISOURCE_DDR }, 336 1 + ilog2(DEVDISR_DDR_15), 337 { SVR_MPC8572v1 >> 16 } }, 338 { "ddrc", DDRC2_BASE, DDRC_SIZE, 2, 339 1, { ISOURCE_DDR }, 340 1 + ilog2(DEVDISR_DDR2_14), 341 { SVR_MPC8572v1 >> 16 } }, 342 #endif 343 { "lbc", LBC_BASE, LBC_SIZE, 0, 344 1, { ISOURCE_LBC }, 345 1 + ilog2(DEVDISR_LBC) }, 346 #if defined(MPC8544) || defined(MPC8536) 347 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 348 1, { ISOURCE_PCIEX }, 349 1 + ilog2(DEVDISR_PCIE), 350 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 351 { "pcie", PCIE2_MPC8544_BASE, PCI_SIZE, 2, 352 1, { ISOURCE_PCIEX2 }, 353 1 + ilog2(DEVDISR_PCIE2), 354 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 355 { "pcie", PCIE3_MPC8544_BASE, PCI_SIZE, 3, 356 1, { ISOURCE_PCIEX3 }, 357 1 + ilog2(DEVDISR_PCIE3), 358 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 359 { "pci", PCIX1_MPC8544_BASE, PCI_SIZE, 0, 360 1, { ISOURCE_PCI1 }, 361 1 + ilog2(DEVDISR_PCI1), 362 { SVR_MPC8536v1 >> 16, SVR_MPC8544v1 >> 16 } }, 363 #endif 364 #ifdef MPC8548 365 { "pcie", PCIE1_BASE, PCI_SIZE, 0, 366 1, { ISOURCE_PCIEX }, 367 1 + ilog2(DEVDISR_PCIE), 368 { SVR_MPC8548v1 >> 16 }, }, 369 { "pci", PCIX1_MPC8548_BASE, PCI_SIZE, 1, 370 1, { ISOURCE_PCI1 }, 371 1 + ilog2(DEVDISR_PCI1), 372 { SVR_MPC8548v1 >> 16 }, }, 373 { "pci", PCIX2_MPC8548_BASE, PCI_SIZE, 2, 374 1, { ISOURCE_PCI2 }, 375 1 + ilog2(DEVDISR_PCI2), 376 { SVR_MPC8548v1 >> 16 }, }, 377 #endif 378 #if defined(MPC8572) || defined(P1025) || defined(P2020) \ 379 || defined(P1023) 380 { "pcie", PCIE1_BASE, PCI_SIZE, 1, 381 1, { ISOURCE_PCIEX }, 382 1 + ilog2(DEVDISR_PCIE), 383 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 384 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 385 { "pcie", PCIE2_MPC8572_BASE, PCI_SIZE, 2, 386 1, { ISOURCE_PCIEX2 }, 387 1 + ilog2(DEVDISR_PCIE2), 388 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 389 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 390 #endif 391 #if defined(MPC8572) || defined(P2020) || defined(_P1023) 392 { "pcie", PCIE3_MPC8572_BASE, PCI_SIZE, 3, 393 1, { ISOURCE_PCIEX3_MPC8572 }, 394 1 + ilog2(DEVDISR_PCIE3), 395 { SVR_MPC8572v1 >> 16, SVR_P2020v2 >> 16, 396 SVR_P1023v1 >> 16 } }, 397 #endif 398 #if defined(MPC8536) || defined(P1025) || defined(P2020) \ 399 || defined(P1023) 400 { "ehci", USB1_BASE, USB_SIZE, 1, 401 1, { ISOURCE_USB1 }, 402 1 + ilog2(DEVDISR_USB1), 403 { SVR_MPC8536v1 >> 16, SVR_P2020v2 >> 16, 404 SVR_P1025v1 >> 16, SVR_P1023v1 >> 16 } }, 405 #endif 406 #ifdef MPC8536 407 { "ehci", USB2_BASE, USB_SIZE, 2, 408 1, { ISOURCE_USB2 }, 409 1 + ilog2(DEVDISR_USB2), 410 { SVR_MPC8536v1 >> 16 }, }, 411 { "ehci", USB3_BASE, USB_SIZE, 3, 412 1, { ISOURCE_USB3 }, 413 1 + ilog2(DEVDISR_USB3), 414 { SVR_MPC8536v1 >> 16 }, }, 415 { "sata", SATA1_BASE, SATA_SIZE, 1, 416 1, { ISOURCE_SATA1 }, 417 1 + ilog2(DEVDISR_SATA1), 418 { SVR_MPC8536v1 >> 16 }, }, 419 { "sata", SATA2_BASE, SATA_SIZE, 2, 420 1, { ISOURCE_SATA2 }, 421 1 + ilog2(DEVDISR_SATA2), 422 { SVR_MPC8536v1 >> 16 }, }, 423 { "spi", SPI_BASE, SPI_SIZE, 0, 424 1, { ISOURCE_SPI }, 425 1 + ilog2(DEVDISR_SPI_15), 426 { SVR_MPC8536v1 >> 16 }, }, 427 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 428 1, { ISOURCE_ESDHC }, 429 1 + ilog2(DEVDISR_ESDHC_12), 430 { SVR_MPC8536v1 >> 16 }, }, 431 #endif 432 #if defined(P1025) || defined(P2020) || defined(P1023) 433 { "spi", SPI_BASE, SPI_SIZE, 0, 434 1, { ISOURCE_SPI }, 435 1 + ilog2(DEVDISR_SPI_28), 436 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16, 437 SVR_P1023v1 >> 16 }, }, 438 #endif 439 #if defined(P1025) || defined(P2020) 440 { "sdhc", ESDHC_BASE, ESDHC_SIZE, 0, 441 1, { ISOURCE_ESDHC }, 442 1 + ilog2(DEVDISR_ESDHC_10), 443 { SVR_P2020v2 >> 16, SVR_P1025v1 >> 16 }, }, 444 #endif 445 //{ "sec", RNG_BASE, RNG_SIZE, 0, 0, }, 446 { NULL } 447 }; 448 449 static int 450 e500_cngetc(dev_t dv) 451 { 452 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 453 454 if ((com0addr[com_lsr] & LSR_RXRDY) == 0) 455 return -1; 456 457 return com0addr[com_data] & 0xff; 458 } 459 460 static void 461 e500_cnputc(dev_t dv, int c) 462 { 463 volatile uint8_t * const com0addr = (void *)(GUR_BASE+CONSADDR); 464 int timo = 150000; 465 466 while ((com0addr[com_lsr] & LSR_TXRDY) == 0 && --timo > 0) 467 ; 468 469 com0addr[com_data] = c; 470 __asm("mbar"); 471 472 while ((com0addr[com_lsr] & LSR_TSRE) == 0 && --timo > 0) 473 ; 474 } 475 476 static void * 477 gur_tlb_mapiodev(paddr_t pa, psize_t len, bool prefetchable) 478 { 479 if (prefetchable) 480 return NULL; 481 if (pa < gur_bst.pbs_offset) 482 return NULL; 483 if (pa + len > gur_bst.pbs_offset + gur_bst.pbs_limit) 484 return NULL; 485 return (void *)pa; 486 } 487 488 static void *(* const early_tlb_mapiodev)(paddr_t, psize_t, bool) = gur_tlb_mapiodev; 489 490 static void 491 e500_cpu_reset(void) 492 { 493 __asm volatile("sync"); 494 cpu_write_4(GLOBAL_BASE + RSTCR, HRESET_REQ); 495 __asm volatile("msync;isync"); 496 } 497 498 static psize_t 499 memprobe(vaddr_t endkernel) 500 { 501 phys_ram_seg_t *mr; 502 paddr_t boot_page = cpu_read_4(GUR_BPTR); 503 printf(" bptr=%"PRIxPADDR, boot_page); 504 if (boot_page & BPTR_EN) { 505 /* 506 * shift it to an address 507 */ 508 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 509 } else { 510 boot_page = ~(paddr_t)0; 511 } 512 513 /* 514 * First we need to find out how much physical memory we have. 515 * We could let our bootloader tell us, but it's almost as easy 516 * to ask the DDR memory controller. 517 */ 518 mr = physmemr; 519 for (u_int i = 0; i < 4; i++) { 520 uint32_t v = cpu_read_4(DDRC1_BASE + CS_CONFIG(i)); 521 if (v & CS_CONFIG_EN) { 522 v = cpu_read_4(DDRC1_BASE + CS_BNDS(i)); 523 if (v == 0) 524 continue; 525 mr->start = BNDS_SA_GET(v); 526 mr->size = BNDS_SIZE_GET(v); 527 #ifdef MEMSIZE 528 if (mr->start >= MEMSIZE) 529 continue; 530 if (mr->start + mr->size > MEMSIZE) 531 mr->size = MEMSIZE - mr->start; 532 #endif 533 #if 0 534 printf(" [%zd]={%#"PRIx64"@%#"PRIx64"}", 535 mr - physmemr, mr->size, mr->start); 536 #endif 537 mr++; 538 } 539 } 540 541 if (mr == physmemr) 542 panic("no memory configured!"); 543 544 /* 545 * Sort memory regions from low to high and coalesce adjacent regions 546 */ 547 u_int cnt = mr - physmemr; 548 if (cnt > 1) { 549 for (u_int i = 0; i < cnt - 1; i++) { 550 for (u_int j = i + 1; j < cnt; j++) { 551 if (physmemr[j].start < physmemr[i].start) { 552 phys_ram_seg_t tmp = physmemr[i]; 553 physmemr[i] = physmemr[j]; 554 physmemr[j] = tmp; 555 } 556 } 557 } 558 mr = physmemr; 559 for (u_int i = 0; i + 1 < cnt; i++, mr++) { 560 if (mr->start + mr->size == mr[1].start) { 561 mr->size += mr[1].size; 562 for (u_int j = 1; i + j + 1 < cnt; j++) 563 mr[j] = mr[j+1]; 564 cnt--; 565 } 566 } 567 } else if (cnt == 0) { 568 panic("%s: no memory found", __func__); 569 } 570 571 /* 572 * Copy physical memory to available memory. 573 */ 574 memcpy(availmemr, physmemr, cnt * sizeof(physmemr[0])); 575 576 /* 577 * Adjust available memory to skip kernel at start of memory. 578 */ 579 availmemr[0].size -= endkernel - availmemr[0].start; 580 availmemr[0].start = endkernel; 581 582 mr = availmemr; 583 for (u_int i = 0; i < cnt; i++, mr++) { 584 /* 585 * U-boot reserves a boot-page on multi-core chips. 586 * We need to make sure that we never disturb it. 587 */ 588 const paddr_t mr_end = mr->start + mr->size; 589 if (mr_end > boot_page && boot_page >= mr->start) { 590 /* 591 * Normally u-boot will put in at the end 592 * of memory. But in case it doesn't, deal 593 * with all possibilities. 594 */ 595 if (boot_page + PAGE_SIZE == mr_end) { 596 mr->size -= PAGE_SIZE; 597 } else if (boot_page == mr->start) { 598 mr->start += PAGE_SIZE; 599 mr->size -= PAGE_SIZE; 600 } else { 601 mr->size = boot_page - mr->start; 602 mr++; 603 for (u_int j = cnt; j > i + 1; j--) { 604 availmemr[j] = availmemr[j-1]; 605 } 606 cnt++; 607 mr->start = boot_page + PAGE_SIZE; 608 mr->size = mr_end - mr->start; 609 } 610 break; 611 } 612 } 613 614 /* 615 * Steal pages at the end of memory for the kernel message buffer. 616 */ 617 mr = availmemr + cnt - 1; 618 KASSERT(mr->size >= round_page(MSGBUFSIZE)); 619 mr->size -= round_page(MSGBUFSIZE); 620 msgbuf_paddr = (uintptr_t)(mr->start + mr->size); 621 622 /* 623 * Calculate physmem. 624 */ 625 for (u_int i = 0; i < cnt; i++) 626 physmem += atop(physmemr[i].size); 627 628 /* Populate powerpc mem regions. */ 629 for (u_int i = 0; i < __arraycount(physmemr); i++) { 630 phys_region[i].start = (paddr_t)physmemr[i].start; 631 phys_region[i].size = (psize_t)physmemr[i].size; 632 if (phys_region[i].size == 0) { 633 break; 634 } 635 } 636 for (u_int i = 0; i < __arraycount(availmemr); i++) { 637 avail_region[i].start = (paddr_t)availmemr[i].start; 638 avail_region[i].size = (psize_t)availmemr[i].size; 639 if (avail_region[i].size == 0) { 640 break; 641 } 642 } 643 644 nmemr = cnt; 645 return physmemr[cnt-1].start + physmemr[cnt-1].size; 646 } 647 648 void 649 consinit(void) 650 { 651 static bool attached = false; 652 653 if (attached) 654 return; 655 attached = true; 656 657 if (comcnfreq == -1) { 658 const uint32_t porpplsr = cpu_read_4(GLOBAL_BASE + PORPLLSR); 659 const uint32_t plat_ratio = PLAT_RATIO_GET(porpplsr); 660 comcnfreq = e500_sys_clk * plat_ratio; 661 printf(" comcnfreq=%u", comcnfreq); 662 } 663 664 comcnattach(&gur_bst, comcnaddr, comcnspeed, comcnfreq, 665 COM_TYPE_NORMAL, comcnmode); 666 } 667 668 void 669 cpu_probe_cache(void) 670 { 671 struct cpu_info * const ci = curcpu(); 672 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 673 const int dcache_assoc = L1CFG_CNWAY_GET(l1cfg0); 674 675 ci->ci_ci.dcache_size = L1CFG_CSIZE_GET(l1cfg0); 676 ci->ci_ci.dcache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg0); 677 678 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 679 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 680 681 ci->ci_ci.icache_size = L1CFG_CSIZE_GET(l1cfg1); 682 ci->ci_ci.icache_line_size = 32 << L1CFG_CBSIZE_GET(l1cfg1); 683 } else { 684 ci->ci_ci.icache_size = ci->ci_ci.dcache_size; 685 ci->ci_ci.icache_line_size = ci->ci_ci.dcache_line_size; 686 } 687 688 /* 689 * Possibly recolor. 690 */ 691 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / dcache_assoc)); 692 693 #ifdef DEBUG 694 uint32_t l1csr0 = mfspr(SPR_L1CSR0); 695 if ((L1CSR_CE & l1csr0) == 0) 696 printf(" DC=off"); 697 698 uint32_t l1csr1 = mfspr(SPR_L1CSR1); 699 if ((L1CSR_CE & l1csr1) == 0) 700 printf(" IC=off"); 701 #endif 702 } 703 704 static uint16_t 705 getsvr(void) 706 { 707 uint16_t svr = mfspr(SPR_SVR) >> 16; 708 709 svr &= ~0x8; /* clear security bit */ 710 switch (svr) { 711 case SVR_MPC8543v1 >> 16: return SVR_MPC8548v1 >> 16; 712 case SVR_MPC8541v1 >> 16: return SVR_MPC8555v1 >> 16; 713 case SVR_P2010v2 >> 16: return SVR_P2020v2 >> 16; 714 case SVR_P1016v1 >> 16: return SVR_P1025v1 >> 16; 715 case SVR_P1017v1 >> 16: return SVR_P1023v1 >> 16; 716 default: return svr; 717 } 718 } 719 720 static const char * 721 socname(uint32_t svr) 722 { 723 svr &= ~0x80000; /* clear security bit */ 724 switch (svr >> 8) { 725 case SVR_MPC8533 >> 8: return "MPC8533"; 726 case SVR_MPC8536v1 >> 8: return "MPC8536"; 727 case SVR_MPC8541v1 >> 8: return "MPC8541"; 728 case SVR_MPC8543v2 >> 8: return "MPC8543"; 729 case SVR_MPC8544v1 >> 8: return "MPC8544"; 730 case SVR_MPC8545v2 >> 8: return "MPC8545"; 731 case SVR_MPC8547v2 >> 8: return "MPC8547"; 732 case SVR_MPC8548v2 >> 8: return "MPC8548"; 733 case SVR_MPC8555v1 >> 8: return "MPC8555"; 734 case SVR_MPC8568v1 >> 8: return "MPC8568"; 735 case SVR_MPC8567v1 >> 8: return "MPC8567"; 736 case SVR_MPC8572v1 >> 8: return "MPC8572"; 737 case SVR_P2020v2 >> 8: return "P2020"; 738 case SVR_P2010v2 >> 8: return "P2010"; 739 case SVR_P1016v1 >> 8: return "P1016"; 740 case SVR_P1017v1 >> 8: return "P1017"; 741 case SVR_P1023v1 >> 8: return "P1023"; 742 case SVR_P1025v1 >> 8: return "P1025"; 743 default: 744 panic("%s: unknown SVR %#x", __func__, svr); 745 } 746 } 747 748 static void 749 e500_tlb_print(device_t self, const char *name, uint32_t tlbcfg) 750 { 751 static const char units[16] = "KKKKKMMMMMGGGGGT"; 752 753 const uint32_t minsize = 1U << (2 * TLBCFG_MINSIZE(tlbcfg)); 754 const uint32_t assoc = TLBCFG_ASSOC(tlbcfg); 755 const u_int maxsize_log4k = TLBCFG_MAXSIZE(tlbcfg); 756 const uint64_t maxsize = 1ULL << (2 * maxsize_log4k % 10); 757 const uint32_t nentries = TLBCFG_NENTRY(tlbcfg); 758 759 aprint_normal_dev(self, "%s:", name); 760 761 aprint_normal(" %u", nentries); 762 if (TLBCFG_AVAIL_P(tlbcfg)) { 763 aprint_normal(" variable-size (%uKB..%"PRIu64"%cB)", 764 minsize, maxsize, units[maxsize_log4k]); 765 } else { 766 aprint_normal(" fixed-size (%uKB)", minsize); 767 } 768 if (assoc == 0 || assoc == nentries) 769 aprint_normal(" fully"); 770 else 771 aprint_normal(" %u-way set", assoc); 772 aprint_normal(" associative entries\n"); 773 } 774 775 static void 776 cpu_print_info(struct cpu_info *ci) 777 { 778 uint64_t freq = board_info_get_number("processor-frequency"); 779 device_t self = ci->ci_dev; 780 781 char freqbuf[10]; 782 if (freq >= 999500000) { 783 const uint32_t freq32 = (freq + 500000) / 10000000; 784 snprintf(freqbuf, sizeof(freqbuf), "%u.%02u GHz", 785 freq32 / 100, freq32 % 100); 786 } else { 787 const uint32_t freq32 = (freq + 500000) / 1000000; 788 snprintf(freqbuf, sizeof(freqbuf), "%u MHz", freq32); 789 } 790 791 const uint32_t pvr = mfpvr(); 792 const uint32_t svr = mfspr(SPR_SVR); 793 const uint32_t pir = mfspr(SPR_PIR); 794 795 aprint_normal_dev(self, "%s %s%s %u.%u with an e500%s %u.%u core, " 796 "ID %u%s\n", 797 freqbuf, socname(svr), (SVR_SECURITY_P(svr) ? "E" : ""), 798 (svr >> 4) & 15, svr & 15, 799 (pvr >> 16) == PVR_MPCe500v2 ? "v2" : "", 800 (pvr >> 4) & 15, pvr & 15, 801 pir, (pir == 0 ? " (Primary)" : "")); 802 803 const uint32_t l1cfg0 = mfspr(SPR_L1CFG0); 804 aprint_normal_dev(self, 805 "%uKB/%uB %u-way L1 %s cache\n", 806 L1CFG_CSIZE_GET(l1cfg0) >> 10, 807 32 << L1CFG_CBSIZE_GET(l1cfg0), 808 L1CFG_CNWAY_GET(l1cfg0), 809 L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD 810 ? "data" : "unified"); 811 812 if (L1CFG_CARCH_GET(l1cfg0) == L1CFG_CARCH_HARVARD) { 813 const uint32_t l1cfg1 = mfspr(SPR_L1CFG1); 814 aprint_normal_dev(self, 815 "%uKB/%uB %u-way L1 %s cache\n", 816 L1CFG_CSIZE_GET(l1cfg1) >> 10, 817 32 << L1CFG_CBSIZE_GET(l1cfg1), 818 L1CFG_CNWAY_GET(l1cfg1), 819 "instruction"); 820 } 821 822 const uint32_t mmucfg = mfspr(SPR_MMUCFG); 823 aprint_normal_dev(self, 824 "%u TLBs, %u concurrent %u-bit PIDs (%u total)\n", 825 MMUCFG_NTLBS_GET(mmucfg) + 1, 826 MMUCFG_NPIDS_GET(mmucfg), 827 MMUCFG_PIDSIZE_GET(mmucfg) + 1, 828 1 << (MMUCFG_PIDSIZE_GET(mmucfg) + 1)); 829 830 e500_tlb_print(self, "tlb0", mfspr(SPR_TLB0CFG)); 831 e500_tlb_print(self, "tlb1", mfspr(SPR_TLB1CFG)); 832 } 833 834 #ifdef MULTIPROCESSOR 835 static void 836 e500_cpu_spinup(device_t self, struct cpu_info *ci) 837 { 838 uintptr_t spinup_table_addr = board_info_get_number("mp-spin-up-table"); 839 struct pglist splist; 840 841 if (spinup_table_addr == 0) { 842 aprint_error_dev(self, "hatch failed (no spin-up table)"); 843 return; 844 } 845 846 struct uboot_spinup_entry * const e = (void *)spinup_table_addr; 847 volatile struct cpu_hatch_data * const h = &cpu_hatch_data; 848 const size_t id = cpu_index(ci); 849 kcpuset_t * const hatchlings = cpuset_info.cpus_hatched; 850 851 if (h->hatch_sp == 0) { 852 int error = uvm_pglistalloc(PAGE_SIZE, PAGE_SIZE, 853 64*1024*1024, PAGE_SIZE, 0, &splist, 1, 1); 854 if (error) { 855 aprint_error_dev(self, 856 "unable to allocate hatch stack\n"); 857 return; 858 } 859 h->hatch_sp = VM_PAGE_TO_PHYS(TAILQ_FIRST(&splist)) 860 + PAGE_SIZE - CALLFRAMELEN; 861 } 862 863 864 for (size_t i = 1; e[i].entry_pir != 0; i++) { 865 printf("%s: cpu%u: entry#%zu(%p): pir=%u\n", 866 __func__, ci->ci_cpuid, i, &e[i], e[i].entry_pir); 867 if (e[i].entry_pir == ci->ci_cpuid) { 868 869 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 870 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 871 ci->ci_curpm = pmap_kernel(); 872 ci->ci_lasttb = cpu_info[0].ci_lasttb; 873 ci->ci_data.cpu_cc_freq = 874 cpu_info[0].ci_data.cpu_cc_freq; 875 876 h->hatch_self = self; 877 h->hatch_ci = ci; 878 h->hatch_running = -1; 879 h->hatch_pir = e[i].entry_pir; 880 h->hatch_hid0 = mfspr(SPR_HID0); 881 u_int tlbidx; 882 e500_tlb_lookup_xtlb(0, &tlbidx); 883 h->hatch_tlbidx = tlbidx; 884 KASSERT(h->hatch_sp != 0); 885 /* 886 * Get new timebase. We don't want to deal with 887 * timebase crossing a 32-bit boundary so make sure 888 * that we have enough headroom to do the timebase 889 * synchronization. 890 */ 891 #define TBSYNC_SLOP 2000 892 uint32_t tbl; 893 uint32_t tbu; 894 do { 895 tbu = mfspr(SPR_RTBU); 896 tbl = mfspr(SPR_RTBL) + TBSYNC_SLOP; 897 } while (tbl < TBSYNC_SLOP); 898 899 h->hatch_tbu = tbu; 900 h->hatch_tbl = tbl; 901 __asm("sync;isync"); 902 dcache_wbinv((vaddr_t)h, sizeof(*h)); 903 904 /* 905 * And here we go... 906 */ 907 e[i].entry_addr_lower = 908 (uint32_t)e500_spinup_trampoline; 909 dcache_wbinv((vaddr_t)&e[i], sizeof(e[i])); 910 __asm __volatile("sync;isync"); 911 __insn_barrier(); 912 913 for (u_int timo = 0; timo++ < 10000; ) { 914 dcache_inv((vaddr_t)&e[i], sizeof(e[i])); 915 if (e[i].entry_addr_lower == 3) { 916 #if 0 917 printf( 918 "%s: cpu%u started in %u spins\n", 919 __func__, cpu_index(ci), timo); 920 #endif 921 break; 922 } 923 } 924 for (u_int timo = 0; timo++ < 10000; ) { 925 dcache_inv((vaddr_t)h, sizeof(*h)); 926 if (h->hatch_running == 0) { 927 #if 0 928 printf( 929 "%s: cpu%u cracked in %u spins: (running=%d)\n", 930 __func__, cpu_index(ci), 931 timo, h->hatch_running); 932 #endif 933 break; 934 } 935 } 936 if (h->hatch_running == -1) { 937 aprint_error_dev(self, 938 "hatch failed (timeout): running=%d" 939 ", entry=%#x\n", 940 h->hatch_running, e[i].entry_addr_lower); 941 goto out; 942 } 943 944 /* 945 * First then we do is to synchronize timebases. 946 * TBSYNC_SLOP*16 should be more than enough 947 * instructions. 948 */ 949 while (tbl != mftbl()) 950 continue; 951 h->hatch_running = 1; 952 dcache_wbinv((vaddr_t)h, sizeof(*h)); 953 __asm("sync;isync"); 954 __insn_barrier(); 955 printf("%s: cpu%u set to running\n", 956 __func__, cpu_index(ci)); 957 958 for (u_int timo = 10000; timo-- > 0; ) { 959 dcache_inv((vaddr_t)h, sizeof(*h)); 960 if (h->hatch_running > 1) 961 break; 962 } 963 if (h->hatch_running == 1) { 964 printf( 965 "%s: tb sync failed: offset from %"PRId64"=%"PRId64" (running=%d)\n", 966 __func__, 967 ((int64_t)tbu << 32) + tbl, 968 (int64_t) 969 (((uint64_t)h->hatch_tbu << 32) 970 + (uint64_t)h->hatch_tbl), 971 h->hatch_running); 972 goto out; 973 } 974 printf( 975 "%s: tb synced: offset=%"PRId64" (running=%d)\n", 976 __func__, 977 (int64_t) 978 (((uint64_t)h->hatch_tbu << 32) 979 + (uint64_t)h->hatch_tbl), 980 h->hatch_running); 981 /* 982 * Now we wait for the hatching to complete. 30ms 983 * should be long enough. 984 */ 985 for (u_int timo = 30000; timo-- > 0; ) { 986 if (kcpuset_isset(hatchlings, id)) { 987 aprint_normal_dev(self, 988 "hatch successful (%u spins, " 989 "timebase adjusted by %"PRId64")\n", 990 30000 - timo, 991 (int64_t) 992 (((uint64_t)h->hatch_tbu << 32) 993 + (uint64_t)h->hatch_tbl)); 994 goto out; 995 } 996 DELAY(1); 997 } 998 999 aprint_error_dev(self, 1000 "hatch failed (timeout): running=%u\n", 1001 h->hatch_running); 1002 goto out; 1003 } 1004 } 1005 1006 aprint_error_dev(self, "hatch failed (no spin-up entry for PIR %u)", 1007 ci->ci_cpuid); 1008 out: 1009 if (h->hatch_sp == 0) 1010 uvm_pglistfree(&splist); 1011 } 1012 #endif 1013 1014 void 1015 e500_cpu_hatch(struct cpu_info *ci) 1016 { 1017 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1018 1019 /* 1020 * Make sure interrupts are blocked. 1021 */ 1022 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1023 1024 /* Set the MAS4 defaults */ 1025 mtspr(SPR_MAS4, MAS4_TSIZED_4KB | MAS4_MD); 1026 tlb_invalidate_all(); 1027 1028 intr_cpu_hatch(ci); 1029 1030 cpu_probe_cache(); 1031 cpu_print_info(ci); 1032 1033 /* 1034 */ 1035 } 1036 1037 static void 1038 e500_cpu_attach(device_t self, u_int instance) 1039 { 1040 struct cpu_info * const ci = &cpu_info[instance - (instance > 0)]; 1041 1042 if (instance > 1) { 1043 #if defined(MULTIPROCESSOR) 1044 ci->ci_idepth = -1; 1045 device_set_private(self, ci); 1046 1047 ci->ci_cpuid = instance - (instance > 0); 1048 ci->ci_dev = self; 1049 ci->ci_tlb_info = cpu_info[0].ci_tlb_info; 1050 1051 mi_cpu_attach(ci); 1052 1053 intr_cpu_attach(ci); 1054 cpu_evcnt_attach(ci); 1055 1056 e500_cpu_spinup(self, ci); 1057 return; 1058 #else 1059 aprint_error_dev(self, "disabled (uniprocessor kernel)\n"); 1060 return; 1061 #endif 1062 } 1063 1064 device_set_private(self, ci); 1065 1066 ci->ci_cpuid = instance - (instance > 0); 1067 ci->ci_dev = self; 1068 1069 intr_cpu_attach(ci); 1070 cpu_evcnt_attach(ci); 1071 1072 KASSERT(ci == curcpu()); 1073 intr_cpu_hatch(ci); 1074 1075 cpu_print_info(ci); 1076 } 1077 1078 void 1079 e500_ipi_halt(void) 1080 { 1081 #ifdef MULTIPROCESSOR 1082 struct cpuset_info * const csi = &cpuset_info; 1083 const cpuid_t index = cpu_index(curcpu()); 1084 1085 printf("cpu%lu: shutting down\n", index); 1086 kcpuset_set(csi->cpus_halted, index); 1087 #endif 1088 register_t msr, hid0; 1089 1090 msr = wrtee(0); 1091 1092 hid0 = mfspr(SPR_HID0); 1093 hid0 = (hid0 & ~(HID0_TBEN|HID0_NAP|HID0_SLEEP)) | HID0_DOZE; 1094 mtspr(SPR_HID0, hid0); 1095 1096 msr = (msr & ~(PSL_EE|PSL_CE|PSL_ME)) | PSL_WE; 1097 mtmsr(msr); 1098 for (;;); /* loop forever */ 1099 } 1100 1101 1102 static void 1103 calltozero(void) 1104 { 1105 panic("call to 0 from %p", __builtin_return_address(0)); 1106 } 1107 1108 #if !defined(ROUTERBOOT) 1109 static void 1110 parse_cmdline(char *cp) 1111 { 1112 int ourhowto = 0; 1113 char c; 1114 bool opt = false; 1115 for (; (c = *cp) != '\0'; cp++) { 1116 if (c == '-') { 1117 opt = true; 1118 continue; 1119 } 1120 if (c == ' ') { 1121 opt = false; 1122 continue; 1123 } 1124 if (opt) { 1125 switch (c) { 1126 case 'a': ourhowto |= RB_ASKNAME; break; 1127 case 'd': ourhowto |= AB_DEBUG; break; 1128 case 'q': ourhowto |= AB_QUIET; break; 1129 case 's': ourhowto |= RB_SINGLE; break; 1130 case 'v': ourhowto |= AB_VERBOSE; break; 1131 } 1132 continue; 1133 } 1134 strlcpy(root_string, cp, sizeof(root_string)); 1135 break; 1136 } 1137 if (ourhowto) { 1138 boothowto |= ourhowto; 1139 printf(" boothowto=%#x(%#x)", boothowto, ourhowto); 1140 } 1141 if (root_string[0]) 1142 printf(" root=%s", root_string); 1143 } 1144 #endif /* !ROUTERBOOT */ 1145 1146 void 1147 initppc(vaddr_t startkernel, vaddr_t endkernel, 1148 void *a0, void *a1, char *a2, char *a3) 1149 { 1150 struct cpu_info * const ci = curcpu(); 1151 struct cpu_softc * const cpu = ci->ci_softc; 1152 1153 cn_tab = &e500_earlycons; 1154 printf(" initppc(%#"PRIxVADDR", %#"PRIxVADDR", %p, %p, %p, %p)<enter>", 1155 startkernel, endkernel, a0, a1, a2, a3); 1156 1157 #if !defined(ROUTERBOOT) 1158 if (a2[0] != '\0') 1159 printf(" consdev=<%s>", a2); 1160 if (a3[0] != '\0') { 1161 printf(" cmdline=<%s>", a3); 1162 parse_cmdline(a3); 1163 } 1164 #endif /* !ROUTERBOOT */ 1165 1166 /* 1167 * Make sure we don't enter NAP or SLEEP if PSL_POW (MSR[WE]) is set. 1168 * DOZE is ok. 1169 */ 1170 const register_t hid0 = mfspr(SPR_HID0); 1171 mtspr(SPR_HID0, 1172 (hid0 & ~(HID0_NAP | HID0_SLEEP)) | HID0_TBEN | HID0_EMCP | HID0_DOZE); 1173 #ifdef CADMUS 1174 /* 1175 * Need to cache this from cadmus since we need to unmap cadmus since 1176 * it falls in the middle of kernel address space. 1177 */ 1178 cadmus_pci = ((uint8_t *)0xf8004000)[CM_PCI]; 1179 cadmus_csr = ((uint8_t *)0xf8004000)[CM_CSR]; 1180 ((uint8_t *)0xf8004000)[CM_CSR] |= CM_RST_PHYRST; 1181 printf(" cadmus_pci=%#x", cadmus_pci); 1182 printf(" cadmus_csr=%#x", cadmus_csr); 1183 ((uint8_t *)0xf8004000)[CM_CSR] = 0; 1184 if ((cadmus_pci & CM_PCI_PSPEED) == CM_PCI_PSPEED_66) { 1185 e500_sys_clk *= 2; 1186 } 1187 #endif 1188 #ifdef PIXIS 1189 pixis_spd = ((uint8_t *)PX_BASE)[PX_SPD]; 1190 printf(" pixis_spd=%#x sysclk=%"PRIuMAX, 1191 pixis_spd, PX_SPD_SYSCLK_GET(pixis_spd)); 1192 #ifndef SYS_CLK 1193 e500_sys_clk = pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]; 1194 #else 1195 printf(" pixis_sysclk=%u", pixis_spd_map[PX_SPD_SYSCLK_GET(pixis_spd)]); 1196 #endif 1197 #endif 1198 printf(" porpllsr=0x%08x", 1199 *(uint32_t *)(GUR_BASE + GLOBAL_BASE + PORPLLSR)); 1200 printf(" sys_clk=%"PRIu64, e500_sys_clk); 1201 1202 /* 1203 * Make sure arguments are page aligned. 1204 */ 1205 startkernel = trunc_page(startkernel); 1206 endkernel = round_page(endkernel); 1207 1208 /* 1209 * Initialize the bus space tag used to access the 85xx general 1210 * utility registers. It doesn't need to be extent protected. 1211 * We know the GUR is mapped via a TLB1 entry so we add a limited 1212 * mapiodev which allows mappings in GUR space. 1213 */ 1214 CTASSERT(offsetof(struct tlb_md_io_ops, md_tlb_mapiodev) == 0); 1215 cpu_md_ops.md_tlb_io_ops = (const void *)&early_tlb_mapiodev; 1216 bus_space_init(&gur_bst, NULL, NULL, 0); 1217 bus_space_init(&gur_le_bst, NULL, NULL, 0); 1218 cpu->cpu_bst = &gur_bst; 1219 cpu->cpu_le_bst = &gur_le_bst; 1220 cpu->cpu_bsh = gur_bsh; 1221 1222 /* 1223 * Attach the console early, really early. 1224 */ 1225 consinit(); 1226 1227 /* 1228 * Reset the PIC to a known state. 1229 */ 1230 cpu_write_4(OPENPIC_BASE + OPENPIC_GCR, GCR_RST); 1231 while (cpu_read_4(OPENPIC_BASE + OPENPIC_GCR) & GCR_RST) 1232 ; 1233 #if 0 1234 cpu_write_4(OPENPIC_BASE + OPENPIC_CTPR, 15); /* IPL_HIGH */ 1235 #endif 1236 printf(" openpic-reset(ctpr=%u)", 1237 cpu_read_4(OPENPIC_BASE + OPENPIC_CTPR)); 1238 1239 /* 1240 * fill in with an absolute branch to a routine that will panic. 1241 */ 1242 *(volatile int *)0 = 0x48000002 | (int) calltozero; 1243 1244 /* 1245 * Get the cache sizes. 1246 */ 1247 cpu_probe_cache(); 1248 printf(" cache(DC=%uKB/%u,IC=%uKB/%u)", 1249 ci->ci_ci.dcache_size >> 10, 1250 ci->ci_ci.dcache_line_size, 1251 ci->ci_ci.icache_size >> 10, 1252 ci->ci_ci.icache_line_size); 1253 1254 /* 1255 * Now find out how much memory is attached 1256 */ 1257 pmemsize = memprobe(endkernel); 1258 cpu->cpu_highmem = pmemsize; 1259 printf(" memprobe=%zuMB", (size_t) (pmemsize >> 20)); 1260 1261 /* 1262 * Now we need cleanout the TLB of stuff that we don't need. 1263 */ 1264 e500_tlb_init(endkernel, pmemsize); 1265 printf(" e500_tlbinit(%#lx,%zuMB)", 1266 endkernel, (size_t) (pmemsize >> 20)); 1267 1268 /* 1269 * 1270 */ 1271 printf(" hid0=%#lx/%#jx", hid0, (uintmax_t)mfspr(SPR_HID0)); 1272 printf(" hid1=%#jx", (uintmax_t)mfspr(SPR_HID1)); 1273 printf(" pordevsr=%#x", cpu_read_4(GLOBAL_BASE + PORDEVSR)); 1274 printf(" devdisr=%#x", cpu_read_4(GLOBAL_BASE + DEVDISR)); 1275 1276 mtmsr(mfmsr() | PSL_CE | PSL_ME | PSL_DE); 1277 1278 /* 1279 * Initialize the message buffer. 1280 */ 1281 initmsgbuf((void *)msgbuf_paddr, round_page(MSGBUFSIZE)); 1282 printf(" msgbuf=%p", (void *)msgbuf_paddr); 1283 1284 /* 1285 * Initialize exception vectors and interrupts 1286 */ 1287 exception_init(&e500_intrsw); 1288 1289 printf(" exception_init=%p", &e500_intrsw); 1290 1291 mtspr(SPR_TCR, TCR_WIE | mfspr(SPR_TCR)); 1292 1293 uvm_md_init(); 1294 1295 /* 1296 * Initialize the pmap. 1297 */ 1298 endkernel = pmap_bootstrap(startkernel, endkernel, availmemr, nmemr); 1299 1300 /* 1301 * Let's take all the indirect calls via our stubs and patch 1302 * them to be direct calls. 1303 */ 1304 cpu_fixup_stubs(); 1305 1306 /* 1307 * As a debug measure we can change the TLB entry that maps all of 1308 * memory to one that encompasses the 64KB with the kernel vectors. 1309 * All other pages will be soft faulted into the TLB as needed. 1310 */ 1311 e500_tlb_minimize(endkernel); 1312 1313 /* 1314 * Set some more MD helpers 1315 */ 1316 cpu_md_ops.md_cpunode_locs = mpc8548_cpunode_locs; 1317 cpu_md_ops.md_device_register = e500_device_register; 1318 cpu_md_ops.md_cpu_attach = e500_cpu_attach; 1319 cpu_md_ops.md_cpu_reset = e500_cpu_reset; 1320 #if NGPIO > 0 1321 cpu_md_ops.md_cpunode_attach = pq3gpio_attach; 1322 #endif 1323 1324 printf(" initppc done!\n"); 1325 1326 /* 1327 * Look for the Book-E modules in the right place. 1328 */ 1329 module_machine = module_machine_booke; 1330 } 1331 1332 #ifdef MPC8548 1333 static const char * const mpc8548cds_extirq_names[] = { 1334 [0] = "pci inta", 1335 [1] = "pci intb", 1336 [2] = "pci intc", 1337 [3] = "pci intd", 1338 [4] = "irq4", 1339 [5] = "gige phy", 1340 [6] = "atm phy", 1341 [7] = "cpld", 1342 [8] = "irq8", 1343 [9] = "nvram", 1344 [10] = "debug", 1345 [11] = "pci2 inta", 1346 }; 1347 #endif 1348 1349 #ifndef MPC8548 1350 static const char * const mpc85xx_extirq_names[] = { 1351 [0] = "extirq 0", 1352 [1] = "extirq 1", 1353 [2] = "extirq 2", 1354 [3] = "extirq 3", 1355 [4] = "extirq 4", 1356 [5] = "extirq 5", 1357 [6] = "extirq 6", 1358 [7] = "extirq 7", 1359 [8] = "extirq 8", 1360 [9] = "extirq 9", 1361 [10] = "extirq 10", 1362 [11] = "extirq 11", 1363 }; 1364 #endif 1365 1366 static void 1367 mpc85xx_extirq_setup(void) 1368 { 1369 #ifdef MPC8548 1370 const char * const * names = mpc8548cds_extirq_names; 1371 const size_t n = __arraycount(mpc8548cds_extirq_names); 1372 #else 1373 const char * const * names = mpc85xx_extirq_names; 1374 const size_t n = __arraycount(mpc85xx_extirq_names); 1375 #endif 1376 prop_array_t extirqs = prop_array_create_with_capacity(n); 1377 for (u_int i = 0; i < n; i++) { 1378 prop_string_t ps = prop_string_create_nocopy(names[i]); 1379 prop_array_set(extirqs, i, ps); 1380 prop_object_release(ps); 1381 } 1382 board_info_add_object("external-irqs", extirqs); 1383 prop_object_release(extirqs); 1384 } 1385 1386 static void 1387 mpc85xx_pci_setup(const char *name, uint32_t intmask, int ist, int inta, ...) 1388 { 1389 prop_dictionary_t pci_intmap = prop_dictionary_create(); 1390 KASSERT(pci_intmap != NULL); 1391 prop_number_t mask = prop_number_create_unsigned(intmask); 1392 KASSERT(mask != NULL); 1393 prop_dictionary_set(pci_intmap, "interrupt-mask", mask); 1394 prop_object_release(mask); 1395 prop_number_t pn_ist = prop_number_create_unsigned(ist); 1396 KASSERT(pn_ist != NULL); 1397 prop_number_t pn_intr = prop_number_create_unsigned(inta); 1398 KASSERT(pn_intr != NULL); 1399 prop_dictionary_t entry = prop_dictionary_create(); 1400 KASSERT(entry != NULL); 1401 prop_dictionary_set(entry, "interrupt", pn_intr); 1402 prop_dictionary_set(entry, "type", pn_ist); 1403 prop_dictionary_set(pci_intmap, "000000", entry); 1404 prop_object_release(pn_intr); 1405 prop_object_release(entry); 1406 va_list ap; 1407 va_start(ap, inta); 1408 u_int intrinc = __LOWEST_SET_BIT(intmask); 1409 for (u_int i = 0; i < intmask; i += intrinc) { 1410 char prop_name[12]; 1411 snprintf(prop_name, sizeof(prop_name), "%06x", i + intrinc); 1412 entry = prop_dictionary_create(); 1413 KASSERT(entry != NULL); 1414 pn_intr = prop_number_create_unsigned(va_arg(ap, u_int)); 1415 KASSERT(pn_intr != NULL); 1416 prop_dictionary_set(entry, "interrupt", pn_intr); 1417 prop_dictionary_set(entry, "type", pn_ist); 1418 prop_dictionary_set(pci_intmap, prop_name, entry); 1419 prop_object_release(pn_intr); 1420 prop_object_release(entry); 1421 } 1422 va_end(ap); 1423 prop_object_release(pn_ist); 1424 board_info_add_object(name, pci_intmap); 1425 prop_object_release(pci_intmap); 1426 } 1427 1428 void 1429 cpu_startup(void) 1430 { 1431 struct cpu_info * const ci = curcpu(); 1432 const uint16_t svr = getsvr(); 1433 1434 powersave = 0; /* we can do it but turn it on by default */ 1435 1436 booke_cpu_startup(socname(mfspr(SPR_SVR))); 1437 1438 uint32_t v = cpu_read_4(GLOBAL_BASE + PORPLLSR); 1439 uint32_t plat_ratio = PLAT_RATIO_GET(v); 1440 uint32_t e500_ratio = E500_RATIO_GET(v); 1441 1442 uint64_t ccb_freq = e500_sys_clk * plat_ratio; 1443 uint64_t cpu_freq = ccb_freq * e500_ratio / 2; 1444 1445 ci->ci_khz = (cpu_freq + 500) / 1000; 1446 cpu_timebase = ci->ci_data.cpu_cc_freq = ccb_freq / 8; 1447 1448 board_info_add_number("my-id", svr); 1449 board_info_add_bool("pq3"); 1450 board_info_add_number("mem-size", pmemsize); 1451 const uint32_t l2ctl = cpu_read_4(L2CACHE_BASE + L2CTL); 1452 uint32_t l2siz = L2CTL_L2SIZ_GET(l2ctl); 1453 uint32_t l2banks = l2siz >> 16; 1454 #ifdef MPC85555 1455 if (svr == (MPC8555v1 >> 16)) { 1456 l2siz >>= 1; 1457 l2banks >>= 1; 1458 } 1459 #endif 1460 paddr_t boot_page = cpu_read_4(GUR_BPTR); 1461 if (boot_page & BPTR_EN) { 1462 bool found = false; 1463 boot_page = (boot_page & BPTR_BOOT_PAGE) << PAGE_SHIFT; 1464 for (const uint32_t *dp = (void *)(boot_page + PAGE_SIZE - 4), 1465 * const bp = (void *)boot_page; 1466 bp <= dp; dp--) { 1467 if (*dp == boot_page) { 1468 uintptr_t spinup_table_addr = (uintptr_t)++dp; 1469 spinup_table_addr = 1470 roundup2(spinup_table_addr, 32); 1471 board_info_add_number("mp-boot-page", 1472 boot_page); 1473 board_info_add_number("mp-spin-up-table", 1474 spinup_table_addr); 1475 printf("Found MP boot page @ %#"PRIxPADDR". " 1476 "Spin-up table @ %#"PRIxPTR"\n", 1477 boot_page, spinup_table_addr); 1478 found = true; 1479 break; 1480 } 1481 } 1482 if (!found) { 1483 printf("Found MP boot page @ %#"PRIxPADDR 1484 " with missing U-boot signature!\n", boot_page); 1485 board_info_add_number("mp-spin-up-table", 0); 1486 } 1487 } 1488 board_info_add_number("l2-cache-size", l2siz); 1489 board_info_add_number("l2-cache-line-size", 32); 1490 board_info_add_number("l2-cache-banks", l2banks); 1491 board_info_add_number("l2-cache-ways", 8); 1492 1493 board_info_add_number("processor-frequency", cpu_freq); 1494 board_info_add_number("bus-frequency", ccb_freq); 1495 board_info_add_number("pci-frequency", e500_sys_clk); 1496 board_info_add_number("timebase-frequency", ccb_freq / 8); 1497 1498 #ifdef CADMUS 1499 const uint8_t phy_base = CM_CSR_EPHY_GET(cadmus_csr) << 2; 1500 board_info_add_number("tsec1-phy-addr", phy_base + 0); 1501 board_info_add_number("tsec2-phy-addr", phy_base + 1); 1502 board_info_add_number("tsec3-phy-addr", phy_base + 2); 1503 board_info_add_number("tsec4-phy-addr", phy_base + 3); 1504 #else 1505 board_info_add_number("tsec1-phy-addr", MII_PHY_ANY); 1506 board_info_add_number("tsec2-phy-addr", MII_PHY_ANY); 1507 board_info_add_number("tsec3-phy-addr", MII_PHY_ANY); 1508 board_info_add_number("tsec4-phy-addr", MII_PHY_ANY); 1509 #endif 1510 1511 uint64_t macstnaddr = 1512 ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR1)) << 16) 1513 | ((uint64_t)le32toh(cpu_read_4(ETSEC1_BASE + MACSTNADDR2)) << 48); 1514 board_info_add_data("tsec-mac-addr-base", &macstnaddr, 6); 1515 1516 #if NPCI > 0 && defined(PCI_MEMBASE) 1517 pcimem_ex = extent_create("pcimem", 1518 PCI_MEMBASE, PCI_MEMBASE + 4*PCI_MEMSIZE, 1519 NULL, 0, EX_WAITOK); 1520 #endif 1521 #if NPCI > 0 && defined(PCI_IOBASE) 1522 pciio_ex = extent_create("pciio", 1523 PCI_IOBASE, PCI_IOBASE + 4*PCI_IOSIZE, 1524 NULL, 0, EX_WAITOK); 1525 #endif 1526 mpc85xx_extirq_setup(); 1527 /* 1528 * PCI-Express virtual wire interrupts on combined with 1529 * External IRQ0/1/2/3. 1530 */ 1531 switch (svr) { 1532 #if defined(MPC8548) 1533 case SVR_MPC8548v1 >> 16: 1534 mpc85xx_pci_setup("pcie0-interrupt-map", 0x001800, 1535 IST_LEVEL, 0, 1, 2, 3); 1536 break; 1537 #endif 1538 #if defined(MPC8544) || defined(MPC8572) || defined(MPC8536) \ 1539 || defined(P1025) || defined(P2020) || defined(P1023) 1540 case SVR_MPC8536v1 >> 16: 1541 case SVR_MPC8544v1 >> 16: 1542 case SVR_MPC8572v1 >> 16: 1543 case SVR_P1016v1 >> 16: 1544 case SVR_P1017v1 >> 16: 1545 case SVR_P1023v1 >> 16: 1546 case SVR_P2010v2 >> 16: 1547 case SVR_P2020v2 >> 16: 1548 mpc85xx_pci_setup("pcie3-interrupt-map", 0x001800, IST_LEVEL, 1549 8, 9, 10, 11); 1550 /* FALLTHROUGH */ 1551 case SVR_P1025v1 >> 16: 1552 mpc85xx_pci_setup("pcie2-interrupt-map", 0x001800, IST_LEVEL, 1553 4, 5, 6, 7); 1554 mpc85xx_pci_setup("pcie1-interrupt-map", 0x001800, IST_LEVEL, 1555 0, 1, 2, 3); 1556 break; 1557 #endif 1558 } 1559 switch (svr) { 1560 #if defined(MPC8536) 1561 case SVR_MPC8536v1 >> 16: 1562 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1563 1, 2, 3, 4); 1564 break; 1565 #endif 1566 #if defined(MPC8544) 1567 case SVR_MPC8544v1 >> 16: 1568 mpc85xx_pci_setup("pci0-interrupt-map", 0x001800, IST_LEVEL, 1569 0, 1, 2, 3); 1570 break; 1571 #endif 1572 #if defined(MPC8548) 1573 case SVR_MPC8548v1 >> 16: 1574 mpc85xx_pci_setup("pci1-interrupt-map", 0x001800, IST_LEVEL, 1575 0, 1, 2, 3); 1576 mpc85xx_pci_setup("pci2-interrupt-map", 0x001800, IST_LEVEL, 1577 11, 1, 2, 3); 1578 break; 1579 #endif 1580 } 1581 } 1582 1583 void 1584 mem_regions(struct mem_region **mem, struct mem_region **avail) 1585 { 1586 *mem = phys_region; 1587 *avail = avail_region; 1588 } 1589
Indexes created Sun Oct 25 00:26:45 UTC 2026