1 /* $NetBSD: imx23_pinctrl.c,v 1.10 2026/02/02 09:51:40 yurix Exp $ */ 2 3 /* 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/types.h> 34 #include <sys/bus.h> 35 #include <sys/cdefs.h> 36 #include <sys/device.h> 37 #include <sys/errno.h> 38 #include <sys/gpio.h> 39 #include <sys/kmem.h> 40 41 #include <dev/fdt/fdtvar.h> 42 #include <dev/gpio/gpiovar.h> 43 44 #include <arm/imx/imx23_pinctrlreg.h> 45 #include <arm/imx/imx23var.h> 46 47 #define IMX23_NUM_GPIO_PINS 96 48 #define NUM_GPIO_BANKS 3 49 50 struct imx23_pinctrl_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_iot; 53 bus_space_handle_t sc_hdl; 54 struct gpio_chipset_tag gc; 55 gpio_pin_t pins[IMX23_NUM_GPIO_PINS]; 56 int bank_phandles[NUM_GPIO_BANKS]; 57 }; 58 59 struct imx23_pinctrl_fdt_pin { 60 int pin_nr; 61 bool pin_actlo; 62 }; 63 64 static int imx23_pinctrl_match(device_t, cfdata_t, void *); 65 static void imx23_pinctrl_attach(device_t, device_t, void *); 66 67 static void imx23_pinctrl_init(struct imx23_pinctrl_softc *); 68 69 static int imx23_pinctrl_gp_gc_open(void *, device_t); 70 static void imx23_pinctrl_gp_gc_close(void *, device_t); 71 static int imx23_pinctrl_gp_pin_read(void *, int); 72 static void imx23_pinctrl_gp_pin_write(void *, int, int); 73 static void imx23_pinctrl_gp_pin_ctl(void *, int, int); 74 75 static void *imx23_gpio_acquire(device_t, const void *, size_t, int); 76 static void imx23_gpio_release(device_t, void *); 77 static int imx23_gpio_read(device_t, void *, bool); 78 static void imx23_gpio_write(device_t, void *, int, bool); 79 80 static struct imx23_pinctrl_softc *_sc = NULL; 81 82 CFATTACH_DECL_NEW(imx23pctl, sizeof(struct imx23_pinctrl_softc), 83 imx23_pinctrl_match, imx23_pinctrl_attach, NULL, NULL); 84 85 #define GPIO_PIN_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_INOUT | \ 86 GPIO_PIN_PULLUP | GPIO_PIN_SET) 87 88 /* 89 * Supported capabilities for each GPIO pin. 90 */ 91 const static int pin_caps[IMX23_NUM_GPIO_PINS] = { 92 /* 93 * HW_PINCTRL_MUXSEL0 94 */ 95 /* PIN 0 */ 96 GPIO_PIN_CAP, 97 /* PIN 1 */ 98 GPIO_PIN_CAP, 99 /* PIN 2 */ 100 GPIO_PIN_CAP, 101 /* PIN 3 */ 102 GPIO_PIN_CAP, 103 /* PIN 4 */ 104 GPIO_PIN_CAP, 105 /* PIN 5 */ 106 GPIO_PIN_CAP, 107 /* PIN 6 */ 108 GPIO_PIN_CAP, 109 /* PIN 7 */ 110 GPIO_PIN_CAP, 111 /* PIN 8 */ 112 GPIO_PIN_CAP, 113 /* PIN 9 */ 114 GPIO_PIN_CAP, 115 /* PIN 10 */ 116 GPIO_PIN_CAP, 117 /* PIN 11 */ 118 GPIO_PIN_CAP, 119 /* PIN 12 */ 120 GPIO_PIN_CAP, 121 /* PIN 13 */ 122 GPIO_PIN_CAP, 123 /* PIN 14 */ 124 GPIO_PIN_CAP, 125 /* PIN 15 */ 126 GPIO_PIN_CAP, 127 /* 128 * HW_PINCTRL_MUXSEL1 129 */ 130 /* PIN 16 */ 131 GPIO_PIN_CAP, 132 /* PIN 17 */ 133 0, /* Reserved for powering OLinuXino MAXI/MINI USB hub. */ 134 /* PIN 18 */ 135 GPIO_PIN_CAP, 136 /* PIN 19 */ 137 GPIO_PIN_CAP, 138 /* PIN 20 */ 139 GPIO_PIN_CAP, 140 /* PIN 21 */ 141 GPIO_PIN_CAP, 142 /* PIN 22 */ 143 GPIO_PIN_CAP, 144 /* PIN 23 */ 145 GPIO_PIN_CAP, 146 /* PIN 24 */ 147 GPIO_PIN_CAP, 148 /* PIN 25 */ 149 GPIO_PIN_CAP, 150 /* PIN 26 */ 151 GPIO_PIN_CAP, 152 /* PIN 27 */ 153 GPIO_PIN_CAP, 154 /* PIN 28 */ 155 GPIO_PIN_CAP, 156 /* PIN 29 */ 157 GPIO_PIN_CAP, 158 /* PIN 30 */ 159 GPIO_PIN_CAP, 160 /* PIN 31 */ 161 GPIO_PIN_CAP, 162 /* 163 * HW_PINCTRL_MUXSEL2 164 */ 165 /* PIN 32 */ 166 GPIO_PIN_CAP, 167 /* PIN 33 */ 168 GPIO_PIN_CAP, 169 /* PIN 34 */ 170 GPIO_PIN_CAP, 171 /* PIN 35 */ 172 GPIO_PIN_CAP, 173 /* PIN 36 */ 174 GPIO_PIN_CAP, 175 /* PIN 37 */ 176 GPIO_PIN_CAP, 177 /* PIN 38 */ 178 GPIO_PIN_CAP, 179 /* PIN 39 */ 180 GPIO_PIN_CAP, 181 /* PIN 40 */ 182 GPIO_PIN_CAP, 183 /* PIN 41 */ 184 GPIO_PIN_CAP, 185 /* PIN 42 */ 186 GPIO_PIN_CAP, 187 /* PIN 43 */ 188 GPIO_PIN_CAP, 189 /* PIN 44 */ 190 GPIO_PIN_CAP, 191 /* PIN 45 */ 192 GPIO_PIN_CAP, 193 /* PIN 46 */ 194 GPIO_PIN_CAP, 195 /* PIN 47 */ 196 GPIO_PIN_CAP, 197 /* 198 * HW_PINCTRL_MUXSEL3 199 */ 200 /* PIN 48 */ 201 GPIO_PIN_CAP, 202 /* PIN 49 */ 203 GPIO_PIN_CAP, 204 /* PIN 50 */ 205 GPIO_PIN_CAP, 206 /* PIN 51 */ 207 GPIO_PIN_CAP, 208 /* PIN 52 */ 209 GPIO_PIN_CAP, 210 /* PIN 53 */ 211 GPIO_PIN_CAP, 212 /* PIN 54 */ 213 GPIO_PIN_CAP, 214 /* PIN 55 */ 215 GPIO_PIN_CAP, 216 /* PIN 56 */ 217 GPIO_PIN_CAP, 218 /* PIN 57 */ 219 GPIO_PIN_CAP, 220 /* PIN 58 */ 221 GPIO_PIN_CAP, 222 /* PIN 59 */ 223 GPIO_PIN_CAP, 224 /* PIN 60 */ 225 GPIO_PIN_CAP, 226 /* PIN 61 */ 227 GPIO_PIN_CAP, 228 /* PIN 62 */ 229 GPIO_PIN_CAP, 230 /* PIN 63 */ 231 0, /* Reserved. */ 232 /* 233 * HW_PINCTRL_MUXSEL4 234 */ 235 /* PIN 64 */ 236 GPIO_PIN_CAP, 237 /* PIN 65 */ 238 GPIO_PIN_CAP, 239 /* PIN 66 */ 240 GPIO_PIN_CAP, 241 /* PIN 67 */ 242 GPIO_PIN_CAP, 243 /* PIN 68 */ 244 GPIO_PIN_CAP, 245 /* PIN 69 */ 246 GPIO_PIN_CAP, 247 /* PIN 70 */ 248 GPIO_PIN_CAP, 249 /* PIN 71 */ 250 GPIO_PIN_CAP, 251 /* PIN 72 */ 252 GPIO_PIN_CAP, 253 /* PIN 73 */ 254 0, /* From this on reserved for EMI (DRAM) pins. */ 255 /* PIN 74 */ 256 0, 257 /* PIN 75 */ 258 0, 259 /* PIN 76 */ 260 0, 261 /* PIN 77 */ 262 0, 263 /* PIN 78 */ 264 0, 265 /* PIN 79 */ 266 0, 267 /* 268 * HW_PINCTRL_MUXSEL5 269 */ 270 /* PIN 80 */ 271 0, 272 /* PIN 81 */ 273 0, 274 /* PIN 82 */ 275 0, 276 /* PIN 83 */ 277 0, 278 /* PIN 84 */ 279 0, 280 /* PIN 85 */ 281 0, 282 /* PIN 86 */ 283 0, 284 /* PIN 87 */ 285 0, 286 /* PIN 88 */ 287 0, 288 /* PIN 89 */ 289 0, 290 /* PIN 90 */ 291 0, 292 /* PIN 91 */ 293 0, 294 /* PIN 92 */ 295 0, 296 /* PIN 93 */ 297 0, 298 /* PIN 94 */ 299 0, 300 /* PIN 95 */ 301 0 302 }; 303 304 #define PINCTRL_RD(sc, reg) \ 305 bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg)) 306 #define PINCTRL_WR(sc, reg, val) \ 307 bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val)) 308 309 /* 310 * Macros to map pin numbers to registers and bit fields. 311 */ 312 #define MUXSEL_REG_SIZE 0x10 313 #define PIN2MUXSEL_REG(pin) \ 314 ((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0) 315 #define PIN2MUXSEL_SET_REG(pin) \ 316 ((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0_SET) 317 #define PIN2MUXSEL_CLR_REG(pin) \ 318 ((pin / 16) * MUXSEL_REG_SIZE + HW_PINCTRL_MUXSEL0_CLR) 319 #define PIN2MUXSEL_MASK(pin) (3<<(pin % 16 * 2)) 320 321 #define DRIVE_REG_SIZE 0x10 322 #define PIN2DRIVE_REG(pin) \ 323 ((pin / 8) * DRIVE_REG_SIZE + HW_PINCTRL_DRIVE0) 324 #define PIN2DRIVE_SET_REG(pin) \ 325 ((pin / 8) * DRIVE_REG_SIZE + HW_PINCTRL_DRIVE0_SET) 326 #define PIN2DRIVE_CLR_REG(pin) \ 327 ((pin / 8) * DRIVE_REG_SIZE + HW_PINCTRL_DRIVE0_CLR) 328 #define PIN2DRIVE_MASK(pin) (3<<(pin % 8 * 4)) 329 330 #define PULL_REG_SIZE 0x10 331 #define PIN2PULL_REG(pin) \ 332 ((pin / 32) * PULL_REG_SIZE + HW_PINCTRL_PULL0) 333 #define PIN2PULL_SET_REG(pin) \ 334 ((pin / 32) * PULL_REG_SIZE + HW_PINCTRL_PULL0_SET) 335 #define PIN2PULL_CLR_REG(pin) \ 336 ((pin / 32) * PULL_REG_SIZE + HW_PINCTRL_PULL0_CLR) 337 #define PIN2PULL_MASK(pin) (1<<(pin % 32)) 338 339 #define DOUT_REG_SIZE 0x10 340 #define PIN2DOUT_REG(pin) \ 341 ((pin / 32) * DOUT_REG_SIZE + HW_PINCTRL_DOUT0) 342 #define PIN2DOUT_SET_REG(pin) \ 343 ((pin / 32) * DOUT_REG_SIZE + HW_PINCTRL_DOUT0_SET) 344 #define PIN2DOUT_CLR_REG(pin) \ 345 ((pin / 32) * DOUT_REG_SIZE + HW_PINCTRL_DOUT0_CLR) 346 #define PIN2DOUT_MASK(pin) (1<<(pin % 32)) 347 348 #define DIN_REG_SIZE 0x10 349 #define PIN2DIN_REG(pin) ((pin / 32) * DIN_REG_SIZE + HW_PINCTRL_DIN0) 350 #define PIN2DIN_MASK(pin) (1<<(pin % 32)) 351 352 #define DOE_REG_SIZE 0x10 353 #define PIN2DOE_REG(pin) \ 354 ((pin / 32) * DOE_REG_SIZE + HW_PINCTRL_DOE0) 355 #define PIN2DOE_SET_REG(pin) \ 356 ((pin / 32) * DOE_REG_SIZE + HW_PINCTRL_DOE0_SET) 357 #define PIN2DOE_CLR_REG(pin) \ 358 ((pin / 32) * DOE_REG_SIZE + HW_PINCTRL_DOE0_CLR) 359 #define PIN2DOE_MASK(pin) (1<<(pin % 32)) 360 361 #define DRIVE_STRENGTH_4MA 0 362 #define DRIVE_STRENGTH_8MA 1 363 #define DRIVE_STRENGTH_12MA 2 364 365 #define MUXEL_GPIO_MODE 3 366 367 #define PINCTRL_SOFT_RST_LOOP 455 /* At least 1 us ... */ 368 369 static const struct device_compatible_entry compat_data[] = { 370 { .compat = "fsl,imx23-pinctrl" }, 371 DEVICE_COMPAT_EOL 372 }; 373 374 static const struct device_compatible_entry child_compat_data[] = { 375 { .compat = "fsl,imx23-gpio" }, 376 DEVICE_COMPAT_EOL 377 }; 378 379 static struct fdtbus_gpio_controller_func imx23_gpio_funcs = { 380 .acquire = imx23_gpio_acquire, 381 .release = imx23_gpio_release, 382 .read = imx23_gpio_read, 383 .write = imx23_gpio_write 384 }; 385 386 static void * 387 imx23_gpio_acquire(device_t dev, const void *data, size_t len, int flags) { 388 struct imx23_pinctrl_softc * const sc = device_private(dev); 389 struct imx23_pinctrl_fdt_pin *pin; 390 const uint32_t *gpio = data; 391 392 if (len != 12) return NULL; 393 394 const int bank_phandle = 395 fdtbus_get_phandle_from_native(be32toh(gpio[0])); 396 int pin_nr_offset = 0; 397 for (int i=0;i<NUM_GPIO_BANKS;i++) { 398 if (sc->bank_phandles[i] == bank_phandle) { 399 pin_nr_offset = 32*i; 400 break; 401 } 402 } 403 404 const int pin_nr = pin_nr_offset + be32toh(gpio[1]); 405 const bool actlo = be32toh(gpio[2]) & 1; 406 407 pin = kmem_zalloc(sizeof(struct imx23_pinctrl_fdt_pin), KM_SLEEP); 408 pin->pin_nr = pin_nr; 409 pin->pin_actlo = actlo; 410 411 gpiobus_pin_ctl(&sc->gc, pin->pin_nr, flags); 412 413 return pin; 414 } 415 416 static void 417 imx23_gpio_release(device_t dev, void *priv) 418 { 419 struct imx23_pinctrl_softc * const sc = device_private(dev); 420 struct imx23_pinctrl_fdt_pin *pin = priv; 421 422 gpiobus_pin_ctl(&sc->gc, pin->pin_nr, GPIO_PIN_INPUT); 423 424 kmem_free(pin, sizeof(*pin)); 425 } 426 427 static int 428 imx23_gpio_read(device_t dev, void *priv, bool raw) 429 { 430 struct imx23_pinctrl_softc * const sc = device_private(dev); 431 struct imx23_pinctrl_fdt_pin *pin = priv; 432 int val; 433 434 val = gpiobus_pin_read(&sc->gc, pin->pin_nr); 435 436 if (!raw && pin->pin_actlo) 437 val = !val; 438 439 return val; 440 } 441 442 static void 443 imx23_gpio_write(device_t dev, void *priv, int val, bool raw) 444 { 445 struct imx23_pinctrl_softc * const sc = device_private(dev); 446 struct imx23_pinctrl_fdt_pin *pin = priv; 447 448 if (!raw && pin->pin_actlo) 449 val = !val; 450 451 gpiobus_pin_write(&sc->gc, pin->pin_nr, val); 452 } 453 454 static int 455 imx23_pinctrl_match(device_t parent, cfdata_t match, void *aux) 456 { 457 struct fdt_attach_args * const faa = aux; 458 459 return of_compatible_match(faa->faa_phandle, compat_data); 460 } 461 462 static void 463 imx23_pinctrl_attach(device_t parent, device_t self, void *aux) 464 { 465 struct imx23_pinctrl_softc *const sc = device_private(self); 466 struct fdt_attach_args *const faa = aux; 467 const int phandle = faa->faa_phandle; 468 469 sc->sc_dev = self; 470 sc->sc_iot = faa->faa_bst; 471 472 bus_addr_t addr; 473 bus_size_t size; 474 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 475 aprint_error(": couldn't get register address\n"); 476 return; 477 } 478 if (bus_space_map(faa->faa_bst, addr, size, 0, &sc->sc_hdl)) { 479 aprint_error(": couldn't map registers\n"); 480 return; 481 } 482 483 imx23_pinctrl_init(sc); 484 485 aprint_normal(": PIN MUX & GPIO\n"); 486 487 /* Set pin capabilities. */ 488 for (int i = 0; i < IMX23_NUM_GPIO_PINS; i++) { 489 sc->pins[i].pin_caps = pin_caps[i]; 490 } 491 492 sc->gc.gp_cookie = sc; 493 sc->gc.gp_gc_open = imx23_pinctrl_gp_gc_open; 494 sc->gc.gp_gc_close = imx23_pinctrl_gp_gc_close; 495 sc->gc.gp_pin_read = imx23_pinctrl_gp_pin_read; 496 sc->gc.gp_pin_write = imx23_pinctrl_gp_pin_write; 497 sc->gc.gp_pin_ctl = imx23_pinctrl_gp_pin_ctl; 498 499 struct gpiobus_attach_args gpiobus_aa; 500 gpiobus_aa.gba_gc = &sc->gc; 501 gpiobus_aa.gba_npins = IMX23_NUM_GPIO_PINS; 502 gpiobus_aa.gba_pins = sc->pins; 503 504 config_found(sc->sc_dev, &gpiobus_aa, gpiobus_print, CFARGS_NONE); 505 506 /* configure fdt gpio system */ 507 for (int i=0;i<NUM_GPIO_BANKS;i++) { 508 sc->bank_phandles[i] = 0; 509 } 510 /* add gpio banks */ 511 for (int child = OF_child(phandle); child; child = OF_peer(child)) { 512 if (!of_compatible_match(child, child_compat_data)) 513 continue; 514 515 bus_addr_t gpio_instance; 516 if (fdtbus_get_reg(child, 0, &gpio_instance, NULL) != 0) { 517 aprint_error(": couldn't get register address\n"); 518 return; 519 } 520 521 if (gpio_instance >= NUM_GPIO_BANKS){ 522 aprint_error(": bank %ld out of range", gpio_instance); 523 continue; 524 } 525 sc->bank_phandles[gpio_instance] = child; 526 527 fdtbus_register_gpio_controller(self, child, &imx23_gpio_funcs); 528 } 529 } 530 531 static void 532 imx23_pinctrl_init(struct imx23_pinctrl_softc *sc) 533 { 534 _sc = sc; 535 } 536 537 static int 538 imx23_pinctrl_gp_gc_open(void *cookie, device_t dev) 539 { 540 return 0; 541 } 542 543 static void 544 imx23_pinctrl_gp_gc_close(void *cookie, device_t dev) 545 { 546 /* do nothing */ 547 } 548 549 static int 550 imx23_pinctrl_gp_pin_read(void *cookie, int pin) 551 { 552 int value; 553 struct imx23_pinctrl_softc *sc = (struct imx23_pinctrl_softc *) cookie; 554 555 if (PINCTRL_RD(sc, PIN2DIN_REG(pin)) & PIN2DIN_MASK(pin)) 556 value = 1; 557 else 558 value = 0; 559 560 return value; 561 } 562 563 static void 564 imx23_pinctrl_gp_pin_write(void *cookie, int pin, int value) 565 { 566 struct imx23_pinctrl_softc *sc = (struct imx23_pinctrl_softc *) cookie; 567 568 if (value) 569 PINCTRL_WR(sc, PIN2DOUT_SET_REG(pin), PIN2DOUT_MASK(pin)); 570 else 571 PINCTRL_WR(sc, PIN2DOUT_CLR_REG(pin), PIN2DOUT_MASK(pin)); 572 } 573 574 /* 575 * Configure pin as requested in flags. 576 */ 577 static void 578 imx23_pinctrl_gp_pin_ctl(void *cookie, int pin, int flags) 579 { 580 struct imx23_pinctrl_softc *sc = (struct imx23_pinctrl_softc *) cookie; 581 uint32_t tmpr; 582 583 /* Enable GPIO pin. */ 584 tmpr = PINCTRL_RD(sc, PIN2MUXSEL_REG(pin)); 585 tmpr &= ~PIN2MUXSEL_MASK(pin); 586 tmpr |= __SHIFTIN(MUXEL_GPIO_MODE, PIN2MUXSEL_MASK(pin)); 587 PINCTRL_WR(sc, PIN2MUXSEL_REG(pin), tmpr); 588 589 /* Configure pin drive strength. */ 590 tmpr = PINCTRL_RD(sc, PIN2DRIVE_REG(pin)); 591 tmpr &= ~PIN2DRIVE_MASK(pin); 592 tmpr |= __SHIFTIN(DRIVE_STRENGTH_4MA, PIN2DRIVE_MASK(pin)); 593 PINCTRL_WR(sc, PIN2DRIVE_REG(pin), tmpr); 594 595 if ((flags & (GPIO_PIN_OUTPUT | GPIO_PIN_INOUT))) { 596 /* Configure pullup resistor or gate keeper. */ 597 if (flags & GPIO_PIN_PULLUP) 598 PINCTRL_WR(sc, PIN2PULL_SET_REG(pin), 599 PIN2PULL_MASK(pin)); 600 else 601 PINCTRL_WR(sc, PIN2PULL_CLR_REG(pin), 602 PIN2PULL_MASK(pin)); 603 604 /* Set initial pin value to logic zero. */ 605 PINCTRL_WR(sc, PIN2DOUT_CLR_REG(pin), PIN2DOUT_MASK(pin)); 606 607 /* Enable pin output. */ 608 PINCTRL_WR(sc, PIN2DOE_SET_REG(pin), PIN2DOE_MASK(pin)); 609 } 610 611 if (flags & GPIO_PIN_INPUT) { 612 /* Disable pin output. */ 613 PINCTRL_WR(sc, PIN2DOE_CLR_REG(pin), PIN2DOE_MASK(pin)); 614 615 /* Configure pullup resistor or gate keeper. */ 616 if (flags & GPIO_PIN_PULLUP) 617 PINCTRL_WR(sc, PIN2PULL_SET_REG(pin), 618 PIN2PULL_MASK(pin)); 619 else 620 PINCTRL_WR(sc, PIN2PULL_CLR_REG(pin), 621 PIN2PULL_MASK(pin)); 622 } 623 } 624
Indexes created Sun Oct 25 00:26:45 UTC 2026