1 /* $NetBSD: ki2c.c,v 1.45 2026/03/24 07:30:19 macallan Exp $ */ 2 /* Id: ki2c.c,v 1.7 2002/10/05 09:56:05 tsubai Exp */ 3 4 /*- 5 * Copyright (c) 2001 Tsubai Masanari. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/device.h> 32 #include <sys/systm.h> 33 #include <sys/mutex.h> 34 35 #include <dev/ofw/openfirm.h> 36 #include <machine/autoconf.h> 37 #include <powerpc/pic/picvar.h> 38 39 #include "opt_ki2c.h" 40 #include <macppc/dev/ki2cvar.h> 41 42 #ifdef KI2C_DEBUG 43 #define DPRINTF printf 44 #else 45 #define DPRINTF while (0) printf 46 #endif 47 48 #define KI2C_EXEC_MAX_CMDLEN 32 49 #define KI2C_EXEC_MAX_BUFLEN 32 50 51 int ki2c_match(device_t, cfdata_t, void *); 52 void ki2c_attach(device_t, device_t, void *); 53 inline uint8_t ki2c_readreg(struct ki2c_softc *, int); 54 inline void ki2c_writereg(struct ki2c_softc *, int, uint8_t); 55 u_int ki2c_getmode(struct ki2c_softc *); 56 void ki2c_setmode(struct ki2c_softc *, u_int); 57 u_int ki2c_getspeed(struct ki2c_softc *); 58 void ki2c_setspeed(struct ki2c_softc *, u_int); 59 int ki2c_intr(void *); 60 int ki2c_poll(struct ki2c_softc *, int); 61 int ki2c_start(struct ki2c_softc *, int, int, void *, int); 62 int ki2c_read(struct ki2c_softc *, int, int, void *, int); 63 int ki2c_write(struct ki2c_softc *, int, int, void *, int); 64 65 /* I2C glue */ 66 static int ki2c_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 67 void *, size_t, int); 68 69 static void 70 ki2c_select_channel(struct ki2c_softc *sc, int channel) 71 { 72 uint8_t val = channel ? 0x10 : 0x00; 73 74 /* We handle the subaddress stuff ourselves. */ 75 ki2c_setmode(sc, val | I2C_STDMODE); 76 } 77 78 static int 79 ki2c_acquire_bus(void *v, int flags) 80 { 81 struct ki2c_channel *ch = v; 82 struct ki2c_softc *sc = ch->ch_sc; 83 84 int error = iic_acquire_bus_lock(&sc->sc_mux_lock, flags); 85 if (error) { 86 return error; 87 } 88 89 ki2c_select_channel(sc, ch->ch_channel); 90 return 0; 91 } 92 93 static void 94 ki2c_release_bus(void *v, int flags) 95 { 96 struct ki2c_channel *ch = v; 97 struct ki2c_softc *sc = ch->ch_sc; 98 99 iic_release_bus_lock(&sc->sc_mux_lock); 100 } 101 102 static void 103 ki2c_init_channel(struct ki2c_softc *sc, int channel, int node) 104 { 105 struct ki2c_channel *ch = &sc->sc_channels[channel]; 106 107 /* 108 * XXX PowerMac G5 11,2 has two channel-0 nodes for ki2c1. 109 * 110 * The first one has 2 audio codecs, the second one has 111 * only 1 (which is a duplicate of the pcm3052 under the 112 * first node). This //appears// to be an error in the 113 * OpenFirmware device tree. 114 * 115 * See port-macppc/59673. 116 */ 117 if (ch->ch_sc != NULL) { 118 aprint_debug_dev(sc->sc_dev, 119 "skipping duplicate channel %d (device tree error?)\n", 120 channel); 121 return; 122 } 123 124 iic_tag_init(&ch->ch_i2c); 125 ch->ch_i2c.ic_channel = channel; 126 ch->ch_i2c.ic_cookie = ch; 127 ch->ch_i2c.ic_exec = ki2c_i2c_exec; 128 ch->ch_i2c.ic_acquire_bus = ki2c_acquire_bus; 129 ch->ch_i2c.ic_release_bus = ki2c_release_bus; 130 131 ch->ch_sc = sc; 132 ch->ch_node = node; 133 ch->ch_channel = channel; 134 } 135 136 CFATTACH_DECL_NEW(ki2c, sizeof(struct ki2c_softc), ki2c_match, ki2c_attach, 137 NULL, NULL); 138 139 int 140 ki2c_match(device_t parent, cfdata_t match, void *aux) 141 { 142 struct confargs *ca = aux; 143 144 if (strcmp(ca->ca_name, "i2c") == 0) 145 return 1; 146 147 return 0; 148 } 149 150 void 151 ki2c_attach(device_t parent, device_t self, void *aux) 152 { 153 struct ki2c_softc *sc = device_private(self); 154 struct confargs *ca = aux; 155 int node = ca->ca_node; 156 uint32_t addr, channel; 157 int rate, child, irq, type; 158 char name[32], intr_xname[32]; 159 160 sc->sc_dev = self; 161 sc->sc_tag = ca->ca_tag; 162 ca->ca_reg[0] += ca->ca_baseaddr; 163 164 if (OF_getprop(node, "AAPL,i2c-rate", &rate, 4) != 4) { 165 aprint_error(": cannot get i2c-rate\n"); 166 return; 167 } 168 if (OF_getprop(node, "AAPL,address", &addr, 4) != 4) { 169 aprint_error(": unable to find i2c address\n"); 170 return; 171 } 172 if (bus_space_map(sc->sc_tag, addr, PAGE_SIZE, 0, &sc->sc_bh) != 0) { 173 aprint_error_dev(sc->sc_dev, "failed to map registers\n"); 174 return; 175 } 176 177 if (OF_getprop(node, "AAPL,address-step", &sc->sc_regstep, 4) != 4) { 178 aprint_error(": unable to find i2c address step\n"); 179 return; 180 } 181 182 irq = OF_get_intr(node, intr_xname, 32, &type); 183 sc->sc_poll = (irq == -1); 184 185 if (sc->sc_poll) { 186 aprint_normal(" polling"); 187 } else aprint_normal(" %s", intr_xname); 188 189 printf("\n"); 190 191 ki2c_writereg(sc, STATUS, 0); 192 ki2c_writereg(sc, ISR, 0); 193 ki2c_writereg(sc, IER, 0); 194 195 ki2c_setmode(sc, I2C_STDSUBMODE); 196 ki2c_setspeed(sc, I2C_100kHz); /* XXX rate */ 197 198 ki2c_writereg(sc, IER,I2C_INT_DATA|I2C_INT_ADDR|I2C_INT_STOP); 199 200 /* 201 * Newer OpenFirmware will have "i2c-bus" nodes below the controller 202 * node. If we don't find any, then the devices are direct children 203 * of the controller node, and the channel number is encoded in 204 * bit 8 of the i2c address cell (see ofw_i2c_machdep.c). 205 */ 206 bool found_busnode = false; 207 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 208 OF_getprop(child, "name", name, sizeof(name)); 209 if (strcmp(name, "i2c-bus") == 0) { 210 OF_getprop(child, "reg", &channel, sizeof(channel)); 211 DPRINTF("found channel %x\n", channel); 212 if (channel >= KI2C_MAX_CHANNELS) { 213 aprint_error_dev(self, 214 "ignoring invalid I2C channel %u\n", 215 channel); 216 continue; 217 } 218 ki2c_init_channel(sc, channel, child); 219 found_busnode = true; 220 } 221 } 222 if (!found_busnode) { 223 for (channel = 0; channel < KI2C_MAX_CHANNELS; channel++) { 224 ki2c_init_channel(sc, channel, node); 225 } 226 } 227 228 /* 229 * The Keywest I2C controller has a built-in I2C mux, but it's not 230 * really a distinct device in the device tree, so we handle it here. 231 * 232 * The locking order is: 233 * 234 * iic bus mutex -> mux_lock 235 * 236 * mux_lock is taken in ki2c_acquire_bus(). 237 */ 238 mutex_init(&sc->sc_mux_lock, MUTEX_DEFAULT, IPL_NONE); 239 240 cv_init(&sc->sc_todev, device_xname(self)); 241 mutex_init(&sc->sc_todevmtx, MUTEX_DEFAULT, IPL_NONE); 242 243 if(sc->sc_poll == 0) { 244 snprintf(intr_xname, sizeof(intr_xname), "%s intr", device_xname(self)); 245 intr_establish_xname(irq, type, IPL_BIO, ki2c_intr, sc, 246 intr_xname); 247 248 ki2c_writereg(sc, IER, I2C_INT_DATA | I2C_INT_ADDR| I2C_INT_STOP); 249 } 250 251 for (channel = 0; channel < KI2C_MAX_CHANNELS; channel++) { 252 if (sc->sc_channels[channel].ch_node == 0) { 253 continue; 254 } 255 iicbus_attach_with_devhandle(sc->sc_dev, 256 &sc->sc_channels[channel].ch_i2c, 257 devhandle_from_of(device_handle(sc->sc_dev), 258 sc->sc_channels[channel].ch_node)); 259 } 260 } 261 262 uint8_t 263 ki2c_readreg(struct ki2c_softc *sc, int reg) 264 { 265 266 return bus_space_read_1(sc->sc_tag, sc->sc_bh, sc->sc_regstep * reg); 267 } 268 269 void 270 ki2c_writereg(struct ki2c_softc *sc, int reg, uint8_t val) 271 { 272 273 bus_space_write_1(sc->sc_tag, sc->sc_bh, reg * sc->sc_regstep, val); 274 delay(10); 275 } 276 277 u_int 278 ki2c_getmode(struct ki2c_softc *sc) 279 { 280 return ki2c_readreg(sc, MODE) & I2C_MODE; 281 } 282 283 void 284 ki2c_setmode(struct ki2c_softc *sc, u_int mode) 285 { 286 ki2c_writereg(sc, MODE, mode); 287 } 288 289 u_int 290 ki2c_getspeed(struct ki2c_softc *sc) 291 { 292 return ki2c_readreg(sc, MODE) & I2C_SPEED; 293 } 294 295 void 296 ki2c_setspeed(struct ki2c_softc *sc, u_int speed) 297 { 298 u_int x; 299 300 KASSERT((speed & ~I2C_SPEED) == 0); 301 x = ki2c_readreg(sc, MODE); 302 x &= ~I2C_SPEED; 303 x |= speed; 304 ki2c_writereg(sc, MODE, x); 305 } 306 307 int 308 ki2c_intr(void *cookie) 309 { 310 struct ki2c_softc *sc = cookie; 311 u_int isr, x; 312 isr = ki2c_readreg(sc, ISR); 313 if (isr & I2C_INT_ADDR) { 314 #if 0 315 if ((ki2c_readreg(sc, STATUS) & I2C_ST_LASTAAK) == 0) { 316 /* No slave responded. */ 317 sc->sc_flags |= I2C_ERROR; 318 goto out; 319 } 320 #endif 321 322 if (sc->sc_flags & I2C_READING) { 323 if (sc->sc_resid > 1) { 324 x = ki2c_readreg(sc, CONTROL); 325 x |= I2C_CT_AAK; 326 ki2c_writereg(sc, CONTROL, x); 327 } 328 } else { 329 ki2c_writereg(sc, DATA, *sc->sc_data++); 330 sc->sc_resid--; 331 } 332 } 333 334 if (isr & I2C_INT_DATA) { 335 if (sc->sc_flags & I2C_READING) { 336 *sc->sc_data++ = ki2c_readreg(sc, DATA); 337 sc->sc_resid--; 338 339 if (sc->sc_resid == 0) { /* Completed */ 340 ki2c_writereg(sc, CONTROL, 0); 341 goto out; 342 } 343 } else { 344 #if 0 345 if ((ki2c_readreg(sc, STATUS) & I2C_ST_LASTAAK) == 0) { 346 /* No slave responded. */ 347 sc->sc_flags |= I2C_ERROR; 348 goto out; 349 } 350 #endif 351 352 if (sc->sc_resid == 0) { 353 x = ki2c_readreg(sc, CONTROL) | I2C_CT_STOP; 354 ki2c_writereg(sc, CONTROL, x); 355 } else { 356 ki2c_writereg(sc, DATA, *sc->sc_data++); 357 sc->sc_resid--; 358 } 359 } 360 } 361 362 out: 363 if (isr & I2C_INT_STOP) { 364 ki2c_writereg(sc, CONTROL, 0); 365 sc->sc_flags &= ~I2C_BUSY; 366 cv_signal(&sc->sc_todev); 367 } 368 369 ki2c_writereg(sc, ISR, isr); 370 371 return 1; 372 } 373 374 int 375 ki2c_poll(struct ki2c_softc *sc, int timo) 376 { 377 int bail = 0; 378 while (sc->sc_flags & I2C_BUSY) { 379 if ((cold) || (bail > 10) || (sc->sc_poll)) { 380 if (ki2c_readreg(sc, ISR)) 381 ki2c_intr(sc); 382 timo -= 10; 383 if (timo < 0) { 384 DPRINTF("i2c_poll: timeout\n"); 385 return -1; 386 } 387 delay(10); 388 } else { 389 mutex_enter(&sc->sc_todevmtx); 390 cv_timedwait_sig(&sc->sc_todev, &sc->sc_todevmtx, hz/10); 391 mutex_exit(&sc->sc_todevmtx); 392 bail++; 393 } 394 } 395 return 0; 396 } 397 398 int 399 ki2c_start(struct ki2c_softc *sc, int addr, int subaddr, void *data, int len) 400 { 401 int rw = (sc->sc_flags & I2C_READING) ? 1 : 0; 402 int timo, x; 403 404 KASSERT((addr & 1) == 0); 405 406 sc->sc_data = data; 407 sc->sc_resid = len; 408 sc->sc_flags |= I2C_BUSY; 409 410 timo = 1000 + len * 200; 411 412 /* XXX TAS3001 sometimes takes 50ms to finish writing registers. */ 413 /* if (addr == 0x68) */ 414 timo += 100000; 415 416 ki2c_writereg(sc, ADDR, addr | rw); 417 ki2c_writereg(sc, SUBADDR, subaddr); 418 419 x = ki2c_readreg(sc, CONTROL) | I2C_CT_ADDR; 420 ki2c_writereg(sc, CONTROL, x); 421 422 if (ki2c_poll(sc, timo)) 423 return -1; 424 if (sc->sc_flags & I2C_ERROR) { 425 DPRINTF("I2C_ERROR\n"); 426 return -1; 427 } 428 return 0; 429 } 430 431 int 432 ki2c_read(struct ki2c_softc *sc, int addr, int subaddr, void *data, int len) 433 { 434 sc->sc_flags = I2C_READING; 435 DPRINTF("ki2c_read: %02x %d\n", addr, len); 436 return ki2c_start(sc, addr, subaddr, data, len); 437 } 438 439 int 440 ki2c_write(struct ki2c_softc *sc, int addr, int subaddr, void *data, int len) 441 { 442 sc->sc_flags = 0; 443 DPRINTF("ki2c_write: %02x %d\n",addr,len); 444 return ki2c_start(sc, addr, subaddr, data, len); 445 } 446 447 int 448 ki2c_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd, 449 size_t cmdlen, void *vbuf, size_t buflen, int flags) 450 { 451 struct ki2c_channel *ch = cookie; 452 struct ki2c_softc *sc = ch->ch_sc; 453 int i; 454 size_t w_len; 455 uint8_t *wp; 456 uint8_t wrbuf[KI2C_EXEC_MAX_CMDLEN + KI2C_EXEC_MAX_CMDLEN]; 457 458 /* 459 * We don't have any idea if the ki2c controller can execute 460 * i2c quick_{read,write} operations, so if someone tries one, 461 * return an error. 462 */ 463 if (cmdlen == 0 && buflen == 0) 464 return -1; 465 466 /* 467 * Transaction could be much larger now. Bail if it exceeds our 468 * small combining buffer, we don't expect such devices. 469 */ 470 if (cmdlen + buflen > sizeof(wrbuf)) 471 return -1; 472 473 addr &= 0x7f; /* KASSERT((addr & ~0x7f) == 0); ??? */ 474 475 ki2c_setspeed(sc, I2C_50kHz); 476 477 /* Write-buffer defaults to vcmd */ 478 wp = (uint8_t *)(__UNCONST(vcmd)); 479 w_len = cmdlen; 480 481 /* 482 * Concatenate vcmd and vbuf for write operations 483 * 484 * Drivers written specifically for ki2c might already do this, 485 * but "generic" i2c drivers still provide separate arguments 486 * for the cmd and buf parts of iic_smbus_write_{byte,word}. 487 */ 488 if (I2C_OP_WRITE_P(op) && buflen != 0) { 489 if (cmdlen == 0) { 490 wp = (uint8_t *)vbuf; 491 w_len = buflen; 492 } else { 493 KASSERT((cmdlen + buflen) <= sizeof(wrbuf)); 494 wp = (uint8_t *)(__UNCONST(vcmd)); 495 w_len = 0; 496 for (i = 0; i < cmdlen; i++) 497 wrbuf[w_len++] = *wp++; 498 wp = (uint8_t *)vbuf; 499 for (i = 0; i < buflen; i++) 500 wrbuf[w_len++] = *wp++; 501 wp = wrbuf; 502 } 503 } 504 505 if (w_len > 0) 506 if (ki2c_write(sc, addr << 1, 0, wp, w_len) !=0 ) 507 return -1; 508 509 if (I2C_OP_READ_P(op)) { 510 if (ki2c_read(sc, addr << 1, 0, vbuf, buflen) !=0 ) 511 return -1; 512 } 513 return 0; 514 } 515
Indexes created Sun Oct 25 00:26:45 UTC 2026