1 /* $NetBSD: nvme_pci.c,v 1.38 2026/11/13 14:25:16 skrll Exp $ */ 2 /* $OpenBSD: nvme_pci.c,v 1.3 2016/04/14 11:18:32 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2014 David Gwynne <dlg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Copyright (C) 2016 NONAKA Kimihiro <nonaka (at) netbsd.org> 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 38 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 40 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 42 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.38 2026/11/13 14:25:16 skrll Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/device.h> 52 #include <sys/bitops.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/interrupt.h> 56 #include <sys/kmem.h> 57 #include <sys/pmf.h> 58 #include <sys/module.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/ic/nvmereg.h> 65 #include <dev/ic/nvmevar.h> 66 67 int nvme_pci_force_intx = 0; 68 int nvme_pci_mpsafe = 1; 69 int nvme_pci_mq = 1; /* INTx: ioq=1, MSI/MSI-X: ioq=ncpu */ 70 71 #define NVME_PCI_BAR 0x10 72 73 struct nvme_pci_softc { 74 struct nvme_softc psc_nvme; 75 76 pci_chipset_tag_t psc_pc; 77 pcitag_t psc_tag; 78 pci_intr_handle_t *psc_intrs; 79 int psc_nintrs; 80 }; 81 82 static int nvme_pci_match(device_t, cfdata_t, void *); 83 static void nvme_pci_attach(device_t, device_t, void *); 84 static int nvme_pci_detach(device_t, int); 85 static int nvme_pci_rescan(device_t, const char *, const int *); 86 static bool nvme_pci_suspend(device_t, const pmf_qual_t *); 87 static bool nvme_pci_resume(device_t, const pmf_qual_t *); 88 89 CFATTACH_DECL3_NEW(nvme_pci, sizeof(struct nvme_pci_softc), 90 nvme_pci_match, nvme_pci_attach, nvme_pci_detach, NULL, nvme_pci_rescan, 91 nvme_childdet, DVF_DETACH_SHUTDOWN); 92 93 static int nvme_pci_intr_establish(struct nvme_softc *, 94 uint16_t, struct nvme_queue *); 95 static int nvme_pci_intr_disestablish(struct nvme_softc *, uint16_t); 96 static int nvme_pci_setup_intr(struct pci_attach_args *, 97 struct nvme_pci_softc *); 98 99 static const struct nvme_pci_quirk { 100 pci_vendor_id_t vendor; 101 pci_product_id_t product; 102 uint32_t quirks; 103 } nvme_pci_quirks[] = { 104 { PCI_VENDOR_HGST, PCI_PRODUCT_HGST_SN100, 105 NVME_QUIRK_DELAY_B4_CHK_RDY }, 106 { PCI_VENDOR_HGST, PCI_PRODUCT_HGST_SN200, 107 NVME_QUIRK_DELAY_B4_CHK_RDY }, 108 { PCI_VENDOR_BEIJING_MEMBLAZE, PCI_PRODUCT_BEIJING_MEMBLAZE_PBLAZE4, 109 NVME_QUIRK_DELAY_B4_CHK_RDY }, 110 { PCI_VENDOR_SAMSUNGELEC3, PCI_PRODUCT_SAMSUNGELEC3_172X, 111 NVME_QUIRK_DELAY_B4_CHK_RDY }, 112 { PCI_VENDOR_SAMSUNGELEC3, PCI_PRODUCT_SAMSUNGELEC3_172XAB, 113 NVME_QUIRK_DELAY_B4_CHK_RDY }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DC_P4500_SSD, 115 NVME_QUIRK_NOMSI }, 116 }; 117 118 static const struct nvme_pci_quirk * 119 nvme_pci_lookup_quirk(struct pci_attach_args *pa) 120 { 121 const struct nvme_pci_quirk *q; 122 int i; 123 124 for (i = 0; i < __arraycount(nvme_pci_quirks); i++) { 125 q = &nvme_pci_quirks[i]; 126 127 if (PCI_VENDOR(pa->pa_id) == q->vendor && 128 PCI_PRODUCT(pa->pa_id) == q->product) 129 return q; 130 } 131 return NULL; 132 } 133 134 static int 135 nvme_pci_match(device_t parent, cfdata_t match, void *aux) 136 { 137 struct pci_attach_args *pa = aux; 138 139 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 140 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_NVM && 141 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME_IO) 142 return 1; 143 144 return 0; 145 } 146 147 static void 148 nvme_pci_attach(device_t parent, device_t self, void *aux) 149 { 150 struct nvme_pci_softc *psc = device_private(self); 151 struct nvme_softc *sc = &psc->psc_nvme; 152 struct pci_attach_args *pa = aux; 153 const struct nvme_pci_quirk *quirk; 154 pcireg_t memtype, reg; 155 bus_addr_t memaddr; 156 int flags, error; 157 int msixoff; 158 159 sc->sc_dev = self; 160 psc->psc_pc = pa->pa_pc; 161 psc->psc_tag = pa->pa_tag; 162 if (pci_dma64_available(pa)) 163 sc->sc_dmat = pa->pa_dmat64; 164 else 165 sc->sc_dmat = pa->pa_dmat; 166 167 quirk = nvme_pci_lookup_quirk(pa); 168 if (quirk != NULL) 169 sc->sc_quirks = quirk->quirks; 170 171 pci_aprint_devinfo(pa, NULL); 172 173 /* Map registers */ 174 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, NVME_PCI_BAR); 175 if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) { 176 aprint_error_dev(self, "invalid type (type=0x%x)\n", memtype); 177 return; 178 } 179 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 180 if (((reg & PCI_COMMAND_MASTER_ENABLE) == 0) || 181 ((reg & PCI_COMMAND_MEM_ENABLE) == 0)) { 182 /* 183 * Enable address decoding for memory range in case BIOS or 184 * UEFI didn't set it. 185 */ 186 reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 187 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 188 reg); 189 } 190 191 sc->sc_iot = pa->pa_memt; 192 error = pci_mapreg_info(pa->pa_pc, pa->pa_tag, NVME_PCI_BAR, 193 memtype, &memaddr, &sc->sc_ios, &flags); 194 if (error) { 195 aprint_error_dev(self, "can't get map info\n"); 196 return; 197 } 198 199 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff, 200 NULL)) { 201 pcireg_t msixtbl; 202 uint32_t table_offset; 203 int bir; 204 205 msixtbl = pci_conf_read(pa->pa_pc, pa->pa_tag, 206 msixoff + PCI_MSIX_TBLOFFSET); 207 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK; 208 bir = msixtbl & PCI_MSIX_TBLBIR_MASK; 209 if (bir == PCI_MAPREG_NUM(NVME_PCI_BAR)) { 210 sc->sc_ios = table_offset; 211 } 212 } 213 214 error = bus_space_map(sc->sc_iot, memaddr, sc->sc_ios, flags, 215 &sc->sc_ioh); 216 if (error != 0) { 217 aprint_error_dev(self, "can't map mem space (error=%d)\n", 218 error); 219 return; 220 } 221 222 /* Establish interrupts */ 223 if (nvme_pci_setup_intr(pa, psc) != 0) { 224 aprint_error_dev(self, "unable to allocate interrupt\n"); 225 goto unmap; 226 } 227 sc->sc_intr_establish = nvme_pci_intr_establish; 228 sc->sc_intr_disestablish = nvme_pci_intr_disestablish; 229 230 sc->sc_ih = kmem_zalloc(sizeof(*sc->sc_ih) * psc->psc_nintrs, KM_SLEEP); 231 sc->sc_softih = kmem_zalloc( 232 sizeof(*sc->sc_softih) * psc->psc_nintrs, KM_SLEEP); 233 234 if (nvme_attach(sc) != 0) { 235 /* error printed by nvme_attach() */ 236 goto softintr_free; 237 } 238 239 if (!pmf_device_register(self, nvme_pci_suspend, nvme_pci_resume)) 240 aprint_error_dev(self, "couldn't establish power handler\n"); 241 242 SET(sc->sc_flags, NVME_F_ATTACHED); 243 return; 244 245 softintr_free: 246 kmem_free(sc->sc_softih, sizeof(*sc->sc_softih) * psc->psc_nintrs); 247 kmem_free(sc->sc_ih, sizeof(*sc->sc_ih) * psc->psc_nintrs); 248 sc->sc_nq = 0; 249 pci_intr_release(pa->pa_pc, psc->psc_intrs, psc->psc_nintrs); 250 psc->psc_nintrs = 0; 251 unmap: 252 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 253 sc->sc_ios = 0; 254 } 255 256 static int 257 nvme_pci_rescan(device_t self, const char *attr, const int *flags) 258 { 259 260 return nvme_rescan(self, attr, flags); 261 } 262 263 static bool 264 nvme_pci_suspend(device_t self, const pmf_qual_t *qual) 265 { 266 struct nvme_pci_softc *psc = device_private(self); 267 struct nvme_softc *sc = &psc->psc_nvme; 268 int error; 269 270 error = nvme_suspend(sc); 271 if (error) 272 return false; 273 274 return true; 275 } 276 277 static bool 278 nvme_pci_resume(device_t self, const pmf_qual_t *qual) 279 { 280 struct nvme_pci_softc *psc = device_private(self); 281 struct nvme_softc *sc = &psc->psc_nvme; 282 int error; 283 284 error = nvme_resume(sc); 285 if (error) 286 return false; 287 288 return true; 289 } 290 291 static int 292 nvme_pci_detach(device_t self, int flags) 293 { 294 struct nvme_pci_softc *psc = device_private(self); 295 struct nvme_softc *sc = &psc->psc_nvme; 296 int error; 297 298 if (!ISSET(sc->sc_flags, NVME_F_ATTACHED)) 299 return 0; 300 301 error = nvme_detach(sc, flags); 302 if (error) 303 return error; 304 305 kmem_free(sc->sc_softih, sizeof(*sc->sc_softih) * psc->psc_nintrs); 306 sc->sc_softih = NULL; 307 308 kmem_free(sc->sc_ih, sizeof(*sc->sc_ih) * psc->psc_nintrs); 309 pci_intr_release(psc->psc_pc, psc->psc_intrs, psc->psc_nintrs); 310 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 311 return 0; 312 } 313 314 static void 315 nvme_pci_intx_disable(struct nvme_pci_softc *psc, bool disable) 316 { 317 pcireg_t command; 318 319 /* Write only the Command half to keep W1C Status bits intact. */ 320 command = pci_conf_read(psc->psc_pc, psc->psc_tag, 321 PCI_COMMAND_STATUS_REG) & PCI_COMMAND_MASK; 322 if (disable) 323 command |= PCI_COMMAND_INTERRUPT_DISABLE; 324 else 325 command &= ~PCI_COMMAND_INTERRUPT_DISABLE; 326 pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG, 327 command); 328 (void)pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG); 329 } 330 331 static int 332 nvme_pci_intr_intx(void *arg) 333 { 334 struct nvme_softc *sc = arg; 335 336 /* Some controllers keep INTx asserted after INTMS is set. */ 337 nvme_pci_intx_disable((struct nvme_pci_softc *)sc, true); 338 return nvme_intr(sc); 339 } 340 341 static void 342 nvme_pci_softintr_intx(void *arg) 343 { 344 struct nvme_queue *q = arg; 345 struct nvme_softc *sc = q->q_sc; 346 347 nvme_softintr_intx(q); 348 nvme_pci_intx_disable((struct nvme_pci_softc *)sc, false); 349 350 if (nvme_intx_pending(sc)) 351 softint_schedule(sc->sc_softih[0]); 352 } 353 354 static int 355 nvme_pci_intr_establish(struct nvme_softc *sc, uint16_t qid, 356 struct nvme_queue *q) 357 { 358 struct nvme_pci_softc *psc = (struct nvme_pci_softc *)sc; 359 char intr_xname[INTRDEVNAMEBUF]; 360 char intrbuf[PCI_INTRSTR_LEN]; 361 const char *intrstr = NULL; 362 int (*ih_func)(void *); 363 void (*ih_func_soft)(void *); 364 void *ih_arg; 365 int error; 366 367 KASSERT(sc->sc_use_mq || qid == NVME_ADMIN_Q); 368 KASSERT(sc->sc_ih[qid] == NULL); 369 370 if (nvme_pci_mpsafe) { 371 pci_intr_setattr(psc->psc_pc, &psc->psc_intrs[qid], 372 PCI_INTR_MPSAFE, true); 373 } 374 375 if (!sc->sc_use_mq) { 376 snprintf(intr_xname, sizeof(intr_xname), "%s", 377 device_xname(sc->sc_dev)); 378 ih_arg = sc; 379 ih_func = nvme_intr; 380 ih_func_soft = nvme_softintr_intx; 381 if (pci_intr_type(psc->psc_pc, psc->psc_intrs[0]) == 382 PCI_INTR_TYPE_INTX) { 383 ih_func = nvme_pci_intr_intx; 384 ih_func_soft = nvme_pci_softintr_intx; 385 } 386 } else { 387 if (qid == NVME_ADMIN_Q) { 388 snprintf(intr_xname, sizeof(intr_xname), "%s adminq", 389 device_xname(sc->sc_dev)); 390 } else { 391 snprintf(intr_xname, sizeof(intr_xname), "%s ioq%d", 392 device_xname(sc->sc_dev), qid); 393 } 394 ih_arg = q; 395 ih_func = nvme_intr_msi; 396 ih_func_soft = nvme_softintr_msi; 397 } 398 399 /* establish hardware interrupt */ 400 sc->sc_ih[qid] = pci_intr_establish_xname(psc->psc_pc, 401 psc->psc_intrs[qid], IPL_BIO, ih_func, ih_arg, intr_xname); 402 if (sc->sc_ih[qid] == NULL) { 403 aprint_error_dev(sc->sc_dev, 404 "unable to establish %s interrupt\n", intr_xname); 405 return 1; 406 } 407 408 /* establish also the software interrupt */ 409 sc->sc_softih[qid] = softint_establish( 410 SOFTINT_BIO|(nvme_pci_mpsafe ? SOFTINT_MPSAFE : 0), 411 ih_func_soft, q); 412 if (sc->sc_softih[qid] == NULL) { 413 pci_intr_disestablish(psc->psc_pc, sc->sc_ih[qid]); 414 sc->sc_ih[qid] = NULL; 415 416 aprint_error_dev(sc->sc_dev, 417 "unable to establish %s soft interrupt\n", 418 intr_xname); 419 return 1; 420 } 421 422 intrstr = pci_intr_string(psc->psc_pc, psc->psc_intrs[qid], intrbuf, 423 sizeof(intrbuf)); 424 if (!sc->sc_use_mq) { 425 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 426 } else if (qid == NVME_ADMIN_Q) { 427 aprint_normal_dev(sc->sc_dev, 428 "for admin queue interrupting at %s\n", intrstr); 429 } else if (!nvme_pci_mpsafe) { 430 aprint_normal_dev(sc->sc_dev, 431 "for io queue %d interrupting at %s\n", qid, intrstr); 432 } else { 433 kcpuset_t *affinity; 434 cpuid_t affinity_to; 435 436 kcpuset_create(&affinity, true); 437 affinity_to = (qid - 1) % ncpu; 438 kcpuset_set(affinity, affinity_to); 439 error = interrupt_distribute(sc->sc_ih[qid], affinity, NULL); 440 kcpuset_destroy(affinity); 441 aprint_normal_dev(sc->sc_dev, 442 "for io queue %d interrupting at %s", qid, intrstr); 443 if (error == 0) 444 aprint_normal(" affinity to cpu%lu", affinity_to); 445 aprint_normal("\n"); 446 } 447 return 0; 448 } 449 450 static int 451 nvme_pci_intr_disestablish(struct nvme_softc *sc, uint16_t qid) 452 { 453 struct nvme_pci_softc *psc = (struct nvme_pci_softc *)sc; 454 455 KASSERT(sc->sc_use_mq || qid == NVME_ADMIN_Q); 456 KASSERT(sc->sc_ih[qid] != NULL); 457 458 if (sc->sc_softih) { 459 softint_disestablish(sc->sc_softih[qid]); 460 sc->sc_softih[qid] = NULL; 461 } 462 463 pci_intr_disestablish(psc->psc_pc, sc->sc_ih[qid]); 464 sc->sc_ih[qid] = NULL; 465 466 return 0; 467 } 468 469 static int 470 nvme_pci_setup_intr(struct pci_attach_args *pa, struct nvme_pci_softc *psc) 471 { 472 struct nvme_softc *sc = &psc->psc_nvme; 473 int error; 474 int counts[PCI_INTR_TYPE_SIZE]; 475 pci_intr_handle_t *ihps; 476 int intr_type; 477 478 memset(counts, 0, sizeof(counts)); 479 480 if (nvme_pci_force_intx) 481 goto setup_intx; 482 483 /* MSI-X */ 484 counts[PCI_INTR_TYPE_MSIX] = uimin(pci_msix_count(pa->pa_pc, pa->pa_tag), 485 ncpu + 1); 486 if (counts[PCI_INTR_TYPE_MSIX] < 1) { 487 counts[PCI_INTR_TYPE_MSIX] = 0; 488 } else if (!nvme_pci_mq || !nvme_pci_mpsafe) { 489 if (counts[PCI_INTR_TYPE_MSIX] > 2) 490 counts[PCI_INTR_TYPE_MSIX] = 2; /* adminq + 1 ioq */ 491 } 492 493 /* MSI */ 494 if (sc->sc_quirks & NVME_QUIRK_NOMSI) 495 goto setup_intx; 496 counts[PCI_INTR_TYPE_MSI] = pci_msi_count(pa->pa_pc, pa->pa_tag); 497 if (counts[PCI_INTR_TYPE_MSI] > 0) { 498 while (counts[PCI_INTR_TYPE_MSI] > ncpu + 1) { 499 if (counts[PCI_INTR_TYPE_MSI] / 2 <= ncpu + 1) 500 break; 501 counts[PCI_INTR_TYPE_MSI] /= 2; 502 } 503 } 504 if (counts[PCI_INTR_TYPE_MSI] < 1) { 505 counts[PCI_INTR_TYPE_MSI] = 0; 506 } else if (!nvme_pci_mq || !nvme_pci_mpsafe) { 507 if (counts[PCI_INTR_TYPE_MSI] > 2) 508 counts[PCI_INTR_TYPE_MSI] = 2; /* adminq + 1 ioq */ 509 } 510 511 setup_intx: 512 /* INTx */ 513 counts[PCI_INTR_TYPE_INTX] = 1; 514 515 error = pci_intr_alloc(pa, &ihps, counts, PCI_INTR_TYPE_MSIX); 516 if (error) 517 return error; 518 519 intr_type = pci_intr_type(pa->pa_pc, ihps[0]); 520 521 psc->psc_intrs = ihps; 522 psc->psc_nintrs = counts[intr_type]; 523 if (intr_type == PCI_INTR_TYPE_MSI) { 524 if (counts[intr_type] > ncpu + 1) 525 counts[intr_type] = ncpu + 1; 526 } 527 sc->sc_use_mq = counts[intr_type] > 1; 528 sc->sc_nq = sc->sc_use_mq ? counts[intr_type] - 1 : 1; 529 530 return 0; 531 } 532 533 MODULE(MODULE_CLASS_DRIVER, nvme, "pci,dk_subr"); 534 535 #ifdef _MODULE 536 #include "ioconf.c" 537 #endif 538 539 static int 540 nvme_modcmd(modcmd_t cmd, void *opaque) 541 { 542 #ifdef _MODULE 543 devmajor_t cmajor, bmajor; 544 extern const struct cdevsw nvme_cdevsw; 545 static bool devsw_ok; 546 #endif 547 int error = 0; 548 549 #ifdef _MODULE 550 switch (cmd) { 551 case MODULE_CMD_INIT: 552 bmajor = cmajor = NODEVMAJOR; 553 error = devsw_attach(nvme_cd.cd_name, NULL, &bmajor, 554 &nvme_cdevsw, &cmajor); 555 if (error) { 556 aprint_error("%s: unable to register devsw, err %d\n", 557 nvme_cd.cd_name, error); 558 /* do not abort, just /dev/nvme* will not work */ 559 } 560 else 561 devsw_ok = true; 562 563 error = config_init_component(cfdriver_ioconf_nvme_pci, 564 cfattach_ioconf_nvme_pci, cfdata_ioconf_nvme_pci); 565 if (error) { 566 if (devsw_ok) { 567 devsw_detach(NULL, &nvme_cdevsw); 568 devsw_ok = false; 569 } 570 break; 571 } 572 break; 573 case MODULE_CMD_FINI: 574 error = config_fini_component(cfdriver_ioconf_nvme_pci, 575 cfattach_ioconf_nvme_pci, cfdata_ioconf_nvme_pci); 576 if (devsw_ok) { 577 devsw_detach(NULL, &nvme_cdevsw); 578 devsw_ok = false; 579 } 580 break; 581 default: 582 break; 583 } 584 #endif 585 return error; 586 } 587
Indexes created Sat Nov 14 00:26:57 UTC 2026