1 /* $NetBSD: if_urtw.c,v 1.28 2026/08/29 01:59:51 maya Exp $ */ 2 /* $OpenBSD: if_urtw.c,v 1.39 2011/07/03 15:47:17 matthew Exp $ */ 3 4 /*- 5 * Copyright (c) 2009 Martynas Venckus <martynas (at) openbsd.org> 6 * Copyright (c) 2008 Weongyo Jeong <weongyo (at) FreeBSD.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: if_urtw.c,v 1.28 2026/08/29 01:59:51 maya Exp $"); 23 24 #ifdef _KERNEL_OPT 25 #include "opt_usb.h" 26 #endif 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/proc.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/callout.h> 36 #include <sys/conf.h> 37 #include <sys/device.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 41 #include <machine/endian.h> 42 #include <net/bpf.h> 43 #include <net/if.h> 44 #include <net/if_arp.h> 45 #include <net/if_dl.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 #include <net/if_types.h> 49 50 #include <netinet/in.h> 51 #include <netinet/in_systm.h> 52 #include <netinet/in_var.h> 53 #include <netinet/if_inarp.h> 54 #include <netinet/ip.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_radiotap.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdi_util.h> 62 #include <dev/usb/usbdivar.h> 63 #include <dev/usb/usbdevs.h> 64 65 #include "if_urtwreg.h" 66 67 #ifdef URTW_DEBUG 68 #define DPRINTF(x) do { if (urtw_debug) printf x; } while (0) 69 #define DPRINTFN(n, x) do { if (urtw_debug >= (n)) printf x; } while (0) 70 int urtw_debug = 0; 71 #else 72 #define DPRINTF(x) 73 #define DPRINTFN(n, x) 74 #endif 75 76 /* 77 * Recognized device vendors/products. 78 */ 79 static const struct urtw_type { 80 struct usb_devno dev; 81 uint8_t rev; 82 } urtw_devs[] = { 83 #define URTW_DEV_RTL8187(v, p) \ 84 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 } 85 #define URTW_DEV_RTL8187B(v, p) \ 86 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B } 87 /* Realtek RTL8187 devices. */ 88 URTW_DEV_RTL8187(ASUSTEK, P5B_WIFI), 89 URTW_DEV_RTL8187(DICKSMITH, RTL8187), 90 URTW_DEV_RTL8187(LINKSYS4, WUSB54GC_2), 91 URTW_DEV_RTL8187(LOGITEC, RTL8187), 92 URTW_DEV_RTL8187(NETGEAR, WG111V2), 93 URTW_DEV_RTL8187(REALTEK, RTL8187), 94 URTW_DEV_RTL8187(SITECOMEU, WL168V1), 95 URTW_DEV_RTL8187(SPHAIRON, RTL8187), 96 URTW_DEV_RTL8187(SURECOM, EP9001G2A), 97 /* Realtek RTL8187B devices. */ 98 URTW_DEV_RTL8187B(BELKIN, F5D7050E), 99 URTW_DEV_RTL8187B(NETGEAR, WG111V3), 100 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0), 101 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1), 102 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2), 103 URTW_DEV_RTL8187B(SITECOMEU, WL168V4) 104 #undef URTW_DEV_RTL8187 105 #undef URTW_DEV_RTL8187B 106 }; 107 #define urtw_lookup(v, p) \ 108 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 109 110 /* 111 * Helper read/write macros. 112 */ 113 #define urtw_read8_m(sc, val, data) do { \ 114 error = urtw_read8_c(sc, val, data, 0); \ 115 if (error != 0) \ 116 goto fail; \ 117 } while (0) 118 #define urtw_read8_idx_m(sc, val, data, idx) do { \ 119 error = urtw_read8_c(sc, val, data, idx); \ 120 if (error != 0) \ 121 goto fail; \ 122 } while (0) 123 #define urtw_write8_m(sc, val, data) do { \ 124 error = urtw_write8_c(sc, val, data, 0); \ 125 if (error != 0) \ 126 goto fail; \ 127 } while (0) 128 #define urtw_write8_idx_m(sc, val, data, idx) do { \ 129 error = urtw_write8_c(sc, val, data, idx); \ 130 if (error != 0) \ 131 goto fail; \ 132 } while (0) 133 #define urtw_read16_m(sc, val, data) do { \ 134 error = urtw_read16_c(sc, val, data, 0); \ 135 if (error != 0) \ 136 goto fail; \ 137 } while (0) 138 #define urtw_read16_idx_m(sc, val, data, idx) do { \ 139 error = urtw_read16_c(sc, val, data, idx); \ 140 if (error != 0) \ 141 goto fail; \ 142 } while (0) 143 #define urtw_write16_m(sc, val, data) do { \ 144 error = urtw_write16_c(sc, val, data, 0); \ 145 if (error != 0) \ 146 goto fail; \ 147 } while (0) 148 #define urtw_write16_idx_m(sc, val, data, idx) do { \ 149 error = urtw_write16_c(sc, val, data, idx); \ 150 if (error != 0) \ 151 goto fail; \ 152 } while (0) 153 #define urtw_read32_m(sc, val, data) do { \ 154 error = urtw_read32_c(sc, val, data, 0); \ 155 if (error != 0) \ 156 goto fail; \ 157 } while (0) 158 #define urtw_read32_idx_m(sc, val, data, idx) do { \ 159 error = urtw_read32_c(sc, val, data, idx); \ 160 if (error != 0) \ 161 goto fail; \ 162 } while (0) 163 #define urtw_write32_m(sc, val, data) do { \ 164 error = urtw_write32_c(sc, val, data, 0); \ 165 if (error != 0) \ 166 goto fail; \ 167 } while (0) 168 #define urtw_write32_idx_m(sc, val, data, idx) do { \ 169 error = urtw_write32_c(sc, val, data, idx); \ 170 if (error != 0) \ 171 goto fail; \ 172 } while (0) 173 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 174 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 175 if (error != 0) \ 176 goto fail; \ 177 } while (0) 178 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 179 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 180 if (error != 0) \ 181 goto fail; \ 182 } while (0) 183 #define urtw_8225_write(sc, val, data) do { \ 184 error = urtw_8225_write_c(sc, val, data); \ 185 if (error != 0) \ 186 goto fail; \ 187 } while (0) 188 189 struct urtw_pair { 190 uint32_t reg; 191 uint32_t val; 192 }; 193 194 struct urtw_pair_idx { 195 uint8_t reg; 196 uint8_t val; 197 uint8_t idx; 198 }; 199 200 static struct urtw_pair_idx urtw_8187b_regtbl[] = { 201 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 202 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 203 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 204 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 205 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 206 { 0xff, 0x00, 0 }, 207 208 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 }, 209 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 }, 210 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 }, 211 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 }, 212 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 }, 213 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 }, 214 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 }, 215 { 0xf8, 0x08, 1 }, 216 217 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, 218 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, 219 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, 220 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, 221 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, 222 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, 223 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, 224 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, 225 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, 226 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 }, 227 228 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 }, 229 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 }, 230 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 }, 231 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 }, 232 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 }, 233 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 }, 234 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 235 236 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 237 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 238 }; 239 240 static uint8_t urtw_8225_agc[] = { 241 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 242 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 243 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 244 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 245 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 246 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 247 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 248 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 249 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 250 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 251 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 252 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 253 }; 254 255 static uint32_t urtw_8225_channel[] = { 256 0x0000, /* dummy channel 0 */ 257 0x085c, /* 1 */ 258 0x08dc, /* 2 */ 259 0x095c, /* 3 */ 260 0x09dc, /* 4 */ 261 0x0a5c, /* 5 */ 262 0x0adc, /* 6 */ 263 0x0b5c, /* 7 */ 264 0x0bdc, /* 8 */ 265 0x0c5c, /* 9 */ 266 0x0cdc, /* 10 */ 267 0x0d5c, /* 11 */ 268 0x0ddc, /* 12 */ 269 0x0e5c, /* 13 */ 270 0x0f72, /* 14 */ 271 }; 272 273 static uint8_t urtw_8225_gain[] = { 274 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 275 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 276 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 277 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 278 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 279 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 280 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 281 }; 282 283 static struct urtw_pair urtw_8225_rf_part1[] = { 284 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 285 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 286 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 287 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 } 288 }; 289 290 static struct urtw_pair urtw_8225_rf_part2[] = { 291 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 292 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 293 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 294 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 295 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 296 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 297 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 298 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 299 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 300 { 0x27, 0x88 } 301 }; 302 303 static struct urtw_pair urtw_8225_rf_part3[] = { 304 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 305 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 306 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 307 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 308 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 309 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 310 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 311 }; 312 313 static uint16_t urtw_8225_rxgain[] = { 314 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 315 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 316 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 317 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 318 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 319 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 320 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 321 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 322 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 323 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 324 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 325 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 326 }; 327 328 static uint8_t urtw_8225_threshold[] = { 329 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd 330 }; 331 332 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 333 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 334 }; 335 336 static uint8_t urtw_8225_txpwr_cck[] = { 337 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 338 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 339 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 340 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 341 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 342 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 343 }; 344 345 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 346 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 347 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 348 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 349 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 350 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 351 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 352 }; 353 354 static uint8_t urtw_8225_txpwr_ofdm[] = { 355 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 356 }; 357 358 static uint8_t urtw_8225v2_agc[] = { 359 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 360 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47, 361 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37, 362 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 363 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 364 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 365 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 366 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 367 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 368 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 369 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 370 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 371 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 372 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31, 373 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 374 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 375 }; 376 377 static uint8_t urtw_8225v2_ofdm[] = { 378 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60, 379 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 380 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26, 381 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3, 382 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f, 383 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 384 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 385 0x6d, 0x3c, 0xfb, 0x07 386 }; 387 388 static uint8_t urtw_8225v2_gain_bg[] = { 389 0x23, 0x15, 0xa5, /* -82-1dbm */ 390 0x23, 0x15, 0xb5, /* -82-2dbm */ 391 0x23, 0x15, 0xc5, /* -82-3dbm */ 392 0x33, 0x15, 0xc5, /* -78dbm */ 393 0x43, 0x15, 0xc5, /* -74dbm */ 394 0x53, 0x15, 0xc5, /* -70dbm */ 395 0x63, 0x15, 0xc5, /* -66dbm */ 396 }; 397 398 static struct urtw_pair urtw_8225v2_rf_part1[] = { 399 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 400 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 401 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 402 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 403 }; 404 405 static struct urtw_pair urtw_8225v2_rf_part2[] = { 406 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 407 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 408 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 409 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 410 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 411 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 412 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 413 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 414 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 415 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 416 }; 417 418 static struct urtw_pair urtw_8225v2_rf_part3[] = { 419 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 420 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 421 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 422 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 423 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 424 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 425 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 426 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 427 }; 428 429 static uint16_t urtw_8225v2_rxgain[] = { 430 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 431 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 432 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 433 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 434 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 435 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 436 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 437 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 438 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 439 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 440 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 441 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 442 }; 443 444 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 445 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 446 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 447 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 448 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 449 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 450 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23 451 }; 452 453 static uint8_t urtw_8225v2_txpwr_cck[] = { 454 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 455 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 456 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 457 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 458 }; 459 460 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 461 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 462 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 463 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 464 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 465 }; 466 467 static struct urtw_pair urtw_8225v2_b_rf[] = { 468 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 469 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 470 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 471 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }, 472 { 0x00, 0x01b7 } 473 }; 474 475 static struct urtw_pair urtw_ratetable[] = { 476 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 477 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 478 { 96, 10 }, { 108, 11 } 479 }; 480 481 static int urtw_init(struct ifnet *); 482 static void urtw_stop(struct ifnet *, int); 483 static int urtw_ioctl(struct ifnet *, u_long, void *); 484 static void urtw_start(struct ifnet *); 485 static int urtw_alloc_rx_data_list(struct urtw_softc *); 486 static void urtw_free_rx_data_list(struct urtw_softc *); 487 static int urtw_alloc_tx_data_list(struct urtw_softc *); 488 static void urtw_free_tx_data_list(struct urtw_softc *); 489 static void urtw_rxeof(struct usbd_xfer *, void *, 490 usbd_status); 491 static int urtw_tx_start(struct urtw_softc *, 492 struct ieee80211_node *, struct mbuf *, int); 493 static void urtw_txeof_low(struct usbd_xfer *, void *, 494 usbd_status); 495 static void urtw_txeof_normal(struct usbd_xfer *, void *, 496 usbd_status); 497 static void urtw_next_scan(void *); 498 static void urtw_task(void *); 499 static void urtw_ledusbtask(void *); 500 static void urtw_ledtask(void *); 501 static int urtw_media_change(struct ifnet *); 502 static int urtw_newstate(struct ieee80211com *, enum ieee80211_state, int); 503 static void urtw_watchdog(struct ifnet *); 504 static void urtw_set_chan(struct urtw_softc *, struct ieee80211_channel *); 505 static int urtw_isbmode(uint16_t); 506 static uint16_t urtw_rate2rtl(int); 507 static uint16_t urtw_rtl2rate(int); 508 static usbd_status urtw_set_rate(struct urtw_softc *); 509 static usbd_status urtw_update_msr(struct urtw_softc *); 510 static usbd_status urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t); 511 static usbd_status urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t); 512 static usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t); 513 static usbd_status urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t); 514 static usbd_status urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t); 515 static usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t); 516 static usbd_status urtw_eprom_cs(struct urtw_softc *, int); 517 static usbd_status urtw_eprom_ck(struct urtw_softc *); 518 static usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 519 int); 520 static usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t, 521 uint32_t *); 522 static usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *); 523 static usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t); 524 static usbd_status urtw_get_macaddr(struct urtw_softc *); 525 static usbd_status urtw_get_txpwr(struct urtw_softc *); 526 static usbd_status urtw_get_rfchip(struct urtw_softc *); 527 static usbd_status urtw_led_init(struct urtw_softc *); 528 static usbd_status urtw_8185_rf_pins_enable(struct urtw_softc *); 529 static usbd_status urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 530 static usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t); 531 static usbd_status urtw_8187_write_phy_ofdm_c(struct urtw_softc *, uint8_t, 532 uint32_t); 533 static usbd_status urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 534 uint32_t); 535 static usbd_status urtw_8225_setgain(struct urtw_softc *, int16_t); 536 static usbd_status urtw_8225_usb_init(struct urtw_softc *); 537 static usbd_status urtw_8225_write_c(struct urtw_softc *, uint8_t, uint16_t); 538 static usbd_status urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 539 uint16_t); 540 static usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *); 541 static usbd_status urtw_8225_rf_init(struct urtw_rf *); 542 static usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int); 543 static usbd_status urtw_8225_rf_set_sens(struct urtw_rf *); 544 static usbd_status urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 545 static usbd_status urtw_8225v2_rf_init(struct urtw_rf *); 546 static usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int); 547 static usbd_status urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 548 static usbd_status urtw_8225v2_setgain(struct urtw_softc *, int16_t); 549 static usbd_status urtw_8225_isv2(struct urtw_softc *, int *); 550 static usbd_status urtw_read8e(struct urtw_softc *, int, uint8_t *); 551 static usbd_status urtw_write8e(struct urtw_softc *, int, uint8_t); 552 static usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 553 static usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 554 static usbd_status urtw_open_pipes(struct urtw_softc *); 555 static usbd_status urtw_close_pipes(struct urtw_softc *); 556 static usbd_status urtw_intr_enable(struct urtw_softc *); 557 static usbd_status urtw_intr_disable(struct urtw_softc *); 558 static usbd_status urtw_reset(struct urtw_softc *); 559 static usbd_status urtw_led_on(struct urtw_softc *, int); 560 static usbd_status urtw_led_ctl(struct urtw_softc *, int); 561 static usbd_status urtw_led_blink(struct urtw_softc *); 562 static usbd_status urtw_led_mode0(struct urtw_softc *, int); 563 static usbd_status urtw_led_mode1(struct urtw_softc *, int); 564 static usbd_status urtw_led_mode2(struct urtw_softc *, int); 565 static usbd_status urtw_led_mode3(struct urtw_softc *, int); 566 static usbd_status urtw_rx_setconf(struct urtw_softc *); 567 static usbd_status urtw_rx_enable(struct urtw_softc *); 568 static usbd_status urtw_tx_enable(struct urtw_softc *); 569 static usbd_status urtw_8187b_update_wmm(struct urtw_softc *); 570 static usbd_status urtw_8187b_reset(struct urtw_softc *); 571 static int urtw_8187b_init(struct ifnet *); 572 static usbd_status urtw_8225v2_b_config_mac(struct urtw_softc *); 573 static usbd_status urtw_8225v2_b_init_rfe(struct urtw_softc *); 574 static usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *); 575 static usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *); 576 static usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int); 577 static usbd_status urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int); 578 static int urtw_set_bssid(struct urtw_softc *, const uint8_t *); 579 static int urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 580 581 static int urtw_match(device_t, cfdata_t, void *); 582 static void urtw_attach(device_t, device_t, void *); 583 static int urtw_detach(device_t, int); 584 static int urtw_activate(device_t, enum devact); 585 586 CFATTACH_DECL_NEW(urtw, sizeof(struct urtw_softc), 587 urtw_match, 588 urtw_attach, 589 urtw_detach, 590 urtw_activate 591 ); 592 593 static int 594 urtw_match(device_t parent, cfdata_t match, void *aux) 595 { 596 struct usb_attach_arg *uaa = aux; 597 598 return urtw_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 599 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 600 } 601 602 static void 603 urtw_attach(device_t parent, device_t self, void *aux) 604 { 605 struct urtw_softc *sc = device_private(self); 606 struct usb_attach_arg *uaa = aux; 607 struct ieee80211com *ic = &sc->sc_ic; 608 struct ifnet *ifp = &sc->sc_if; 609 usbd_status error; 610 uint8_t data8; 611 uint32_t data; 612 int i; 613 614 sc->sc_dev = self; 615 sc->sc_udev = uaa->uaa_device; 616 sc->sc_hwrev = urtw_lookup(uaa->uaa_vendor, uaa->uaa_product)->rev; 617 sc->sc_init_state = URTW_INIT_NONE; 618 619 aprint_naive("\n"); 620 aprint_normal(": "); 621 622 if (sc->sc_hwrev & URTW_HWREV_8187) { 623 urtw_read32_m(sc, URTW_TX_CONF, &data); 624 data &= URTW_TX_HWREV_MASK; 625 switch (data) { 626 case URTW_TX_HWREV_8187_D: 627 sc->sc_hwrev |= URTW_HWREV_8187_D; 628 aprint_normal("RTL8187 rev D"); 629 break; 630 case URTW_TX_HWREV_8187B_D: 631 /* 632 * Detect Realtek RTL8187B devices that use 633 * USB IDs of RTL8187. 634 */ 635 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B; 636 aprint_normal("RTL8187B rev B (early)"); 637 break; 638 default: 639 sc->sc_hwrev |= URTW_HWREV_8187_B; 640 aprint_normal("RTL8187 rev 0x%02x", data >> 25); 641 break; 642 } 643 } else { 644 /* RTL8187B hwrev register. */ 645 urtw_read8_m(sc, URTW_8187B_HWREV, &data8); 646 switch (data8) { 647 case URTW_8187B_HWREV_8187B_B: 648 sc->sc_hwrev |= URTW_HWREV_8187B_B; 649 aprint_normal("RTL8187B rev B"); 650 break; 651 case URTW_8187B_HWREV_8187B_D: 652 sc->sc_hwrev |= URTW_HWREV_8187B_D; 653 aprint_normal("RTL8187B rev D"); 654 break; 655 case URTW_8187B_HWREV_8187B_E: 656 sc->sc_hwrev |= URTW_HWREV_8187B_E; 657 aprint_normal("RTL8187B rev E"); 658 break; 659 default: 660 sc->sc_hwrev |= URTW_HWREV_8187B_B; 661 aprint_normal("RTL8187B rev 0x%02x", data8); 662 break; 663 } 664 } 665 666 urtw_read32_m(sc, URTW_RX, &data); 667 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 668 URTW_EEPROM_93C46; 669 670 error = urtw_get_rfchip(sc); 671 if (error != 0) 672 goto fail; 673 error = urtw_get_macaddr(sc); 674 if (error != 0) 675 goto fail; 676 error = urtw_get_txpwr(sc); 677 if (error != 0) 678 goto fail; 679 error = urtw_led_init(sc); /* XXX incompleted */ 680 if (error != 0) 681 goto fail; 682 683 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 684 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 685 sc->sc_currate = 3; 686 /* XXX for what? */ 687 sc->sc_preamble_mode = 2; 688 689 usb_init_task(&sc->sc_task, urtw_task, sc, 0); 690 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc, 0); 691 callout_init(&sc->scan_to, 0); 692 callout_setfunc(&sc->scan_to, urtw_next_scan, sc); 693 callout_init(&sc->sc_led_ch, 0); 694 callout_setfunc(&sc->sc_led_ch, urtw_ledtask, sc); 695 696 ic->ic_ifp = ifp; 697 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 698 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 699 ic->ic_state = IEEE80211_S_INIT; 700 701 /* set device capabilities */ 702 ic->ic_caps = 703 IEEE80211_C_MONITOR | /* monitor mode supported */ 704 IEEE80211_C_TXPMGT | /* tx power management */ 705 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 706 IEEE80211_C_SHSLOT | /* short slot time supported */ 707 IEEE80211_C_WEP | /* s/w WEP */ 708 IEEE80211_C_WPA; /* WPA/RSN */ 709 710 /* set supported .11b and .11g rates */ 711 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 712 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 713 714 /* set supported .11b and .11g channels (1 through 14) */ 715 for (i = 1; i <= 14; i++) { 716 ic->ic_channels[i].ic_freq = 717 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 718 ic->ic_channels[i].ic_flags = 719 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 720 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 721 } 722 723 ifp->if_softc = sc; 724 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 725 if (sc->sc_hwrev & URTW_HWREV_8187) { 726 ifp->if_init = urtw_init; 727 } else { 728 ifp->if_init = urtw_8187b_init; 729 } 730 ifp->if_ioctl = urtw_ioctl; 731 ifp->if_start = urtw_start; 732 ifp->if_watchdog = urtw_watchdog; 733 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 734 IFQ_SET_READY(&ifp->if_snd); 735 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 736 737 if_initialize(ifp); 738 ieee80211_ifattach(ic); 739 740 /* override state transition machine */ 741 sc->sc_newstate = ic->ic_newstate; 742 ic->ic_newstate = urtw_newstate; 743 744 /* XXX media locking needs revisiting */ 745 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 746 ieee80211_media_init_with_lock(ic, 747 urtw_media_change, ieee80211_media_status, &sc->sc_media_mtx); 748 749 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 750 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 751 &sc->sc_drvbpf); 752 753 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 754 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 755 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT); 756 757 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 758 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 759 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT); 760 761 aprint_normal(", address %s\n", ether_sprintf(ic->ic_myaddr)); 762 763 ifp->if_percpuq = if_percpuq_create(ifp); 764 if_register(ifp); 765 766 ieee80211_announce(ic); 767 768 sc->sc_init_state = URTW_INIT_INITED; 769 770 return; 771 fail: 772 aprint_error(": %s failed!\n", __func__); 773 sc->sc_dying = true; 774 } 775 776 static int 777 urtw_detach(device_t self, int flags) 778 { 779 struct urtw_softc *sc = device_private(self); 780 struct ifnet *ifp = &sc->sc_if; 781 int s; 782 783 s = splusb(); 784 785 sc->sc_dying = true; 786 787 if (sc->sc_init_state < URTW_INIT_INITED) 788 goto out; 789 790 callout_halt(&sc->scan_to, NULL); 791 callout_halt(&sc->sc_led_ch, NULL); 792 callout_destroy(&sc->scan_to); 793 callout_destroy(&sc->sc_led_ch); 794 795 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, NULL); 796 usb_rem_task_wait(sc->sc_udev, &sc->sc_ledtask, USB_TASKQ_DRIVER, 797 NULL); 798 799 if (ifp->if_softc != NULL) { 800 bpf_detach(ifp); 801 ieee80211_ifdetach(&sc->sc_ic); /* free all nodes */ 802 if_detach(ifp); 803 } 804 805 /* abort and free xfers */ 806 urtw_free_tx_data_list(sc); 807 urtw_free_rx_data_list(sc); 808 urtw_close_pipes(sc); 809 810 out: 811 splx(s); 812 return 0; 813 } 814 815 static int 816 urtw_activate(device_t self, enum devact act) 817 { 818 struct urtw_softc *sc = device_private(self); 819 820 switch (act) { 821 case DVACT_DEACTIVATE: 822 sc->sc_dying = true; 823 break; 824 } 825 826 return 0; 827 } 828 829 static usbd_status 830 urtw_close_pipes(struct urtw_softc *sc) 831 { 832 usbd_status error = 0; 833 834 if (sc->sc_rxpipe != NULL) { 835 usbd_close_pipe(sc->sc_rxpipe); 836 sc->sc_rxpipe = NULL; 837 } 838 if (sc->sc_txpipe_low != NULL) { 839 usbd_close_pipe(sc->sc_txpipe_low); 840 sc->sc_txpipe_low = NULL; 841 } 842 if (sc->sc_txpipe_normal != NULL) { 843 usbd_close_pipe(sc->sc_txpipe_normal); 844 sc->sc_txpipe_normal = NULL; 845 } 846 return error; 847 } 848 849 static usbd_status 850 urtw_open_pipes(struct urtw_softc *sc) 851 { 852 usbd_status error; 853 854 /* 855 * NB: there is no way to distinguish each pipes so we need to hardcode 856 * pipe numbers 857 */ 858 859 /* tx pipe - low priority packets */ 860 if (sc->sc_hwrev & URTW_HWREV_8187) 861 error = usbd_open_pipe(sc->sc_iface, 0x2, 862 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 863 else 864 error = usbd_open_pipe(sc->sc_iface, 0x6, 865 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 866 if (error != 0) { 867 printf("%s: could not open Tx low pipe: %s\n", 868 device_xname(sc->sc_dev), usbd_errstr(error)); 869 goto fail; 870 } 871 /* tx pipe - normal priority packets */ 872 if (sc->sc_hwrev & URTW_HWREV_8187) 873 error = usbd_open_pipe(sc->sc_iface, 0x3, 874 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 875 else 876 error = usbd_open_pipe(sc->sc_iface, 0x7, 877 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 878 if (error != 0) { 879 printf("%s: could not open Tx normal pipe: %s\n", 880 device_xname(sc->sc_dev), usbd_errstr(error)); 881 goto fail; 882 } 883 /* rx pipe */ 884 if (sc->sc_hwrev & URTW_HWREV_8187) 885 error = usbd_open_pipe(sc->sc_iface, 0x81, 886 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 887 else 888 error = usbd_open_pipe(sc->sc_iface, 0x83, 889 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 890 if (error != 0) { 891 printf("%s: could not open Rx pipe: %s\n", 892 device_xname(sc->sc_dev), usbd_errstr(error)); 893 goto fail; 894 } 895 896 return 0; 897 fail: 898 (void)urtw_close_pipes(sc); 899 return error; 900 } 901 902 static int 903 urtw_alloc_rx_data_list(struct urtw_softc *sc) 904 { 905 int i, error; 906 907 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 908 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 909 910 data->sc = sc; 911 912 error = usbd_create_xfer(sc->sc_rxpipe, MCLBYTES, 913 0, 0, &data->xfer); 914 if (error) { 915 916 printf("%s: could not allocate rx xfer\n", 917 device_xname(sc->sc_dev)); 918 error = ENOMEM; 919 goto fail; 920 } 921 922 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 923 if (data->m == NULL) { 924 printf("%s: could not allocate rx mbuf\n", 925 device_xname(sc->sc_dev)); 926 error = ENOMEM; 927 goto fail; 928 } 929 MCLGET(data->m, M_DONTWAIT); 930 if (!(data->m->m_flags & M_EXT)) { 931 printf("%s: could not allocate rx mbuf cluster\n", 932 device_xname(sc->sc_dev)); 933 error = ENOMEM; 934 goto fail; 935 } 936 data->buf = mtod(data->m, uint8_t *); 937 } 938 939 return 0; 940 941 fail: 942 urtw_free_rx_data_list(sc); 943 return error; 944 } 945 946 static void 947 urtw_free_rx_data_list(struct urtw_softc *sc) 948 { 949 int i; 950 951 /* Make sure no transfers are pending. */ 952 if (sc->sc_rxpipe != NULL) 953 usbd_abort_pipe(sc->sc_rxpipe); 954 955 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 956 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 957 958 if (data->xfer != NULL) { 959 usbd_destroy_xfer(data->xfer); 960 data->xfer = NULL; 961 } 962 m_freem(data->m); 963 data->m = NULL; 964 } 965 } 966 967 static int 968 urtw_alloc_tx_data_list(struct urtw_softc *sc) 969 { 970 int i, error; 971 972 for (size_t j = 0; j < URTW_PRIORITY_MAX; j++) { 973 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 974 struct urtw_tx_data *data = &sc->sc_tx_data[j][i]; 975 976 data->sc = sc; 977 data->ni = NULL; 978 979 error = usbd_create_xfer((j == URTW_PRIORITY_LOW) ? 980 sc->sc_txpipe_low : sc->sc_txpipe_normal, 981 URTW_TX_MAXSIZE, USBD_FORCE_SHORT_XFER, 0, 982 &data->xfer); 983 if (error) { 984 printf("%s: could not allocate tx xfer\n", 985 device_xname(sc->sc_dev)); 986 goto fail; 987 } 988 989 data->buf = usbd_get_buffer(data->xfer); 990 991 if (((unsigned long)data->buf) % 4) 992 printf("%s: warn: unaligned buffer %p\n", 993 device_xname(sc->sc_dev), data->buf); 994 } 995 } 996 997 return 0; 998 999 fail: 1000 urtw_free_tx_data_list(sc); 1001 return error; 1002 } 1003 1004 static void 1005 urtw_free_tx_data_list(struct urtw_softc *sc) 1006 { 1007 int i; 1008 1009 /* Make sure no transfers are pending. */ 1010 if (sc->sc_txpipe_low != NULL) 1011 usbd_abort_pipe(sc->sc_txpipe_low); 1012 if (sc->sc_txpipe_normal != NULL) 1013 usbd_abort_pipe(sc->sc_txpipe_normal); 1014 1015 for (size_t j = 0; j < URTW_PRIORITY_MAX; j++) { 1016 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 1017 struct urtw_tx_data *data = &sc->sc_tx_data[j][i]; 1018 1019 if (data->xfer != NULL) { 1020 usbd_destroy_xfer(data->xfer); 1021 data->xfer = NULL; 1022 } 1023 if (data->ni != NULL) { 1024 ieee80211_free_node(data->ni); 1025 data->ni = NULL; 1026 } 1027 } 1028 } 1029 } 1030 1031 static int 1032 urtw_media_change(struct ifnet *ifp) 1033 { 1034 int error; 1035 1036 error = ieee80211_media_change(ifp); 1037 if (error != ENETRESET) 1038 return error; 1039 1040 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1041 (IFF_UP | IFF_RUNNING)) 1042 if_init(ifp); 1043 1044 return 0; 1045 } 1046 1047 static int 1048 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1049 { 1050 struct urtw_softc *sc = ic->ic_ifp->if_softc; 1051 1052 /* 1053 * XXXSMP: This does not wait for the task, if it is in flight, 1054 * to complete. If this code works at all, it must rely on the 1055 * kernel lock to serialize with the USB task thread. 1056 */ 1057 usb_rem_task(sc->sc_udev, &sc->sc_task); 1058 callout_stop(&sc->scan_to); 1059 1060 /* do it in a process context */ 1061 sc->sc_state = nstate; 1062 sc->sc_arg = arg; 1063 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1064 1065 return 0; 1066 } 1067 1068 static usbd_status 1069 urtw_led_init(struct urtw_softc *sc) 1070 { 1071 uint32_t rev; 1072 usbd_status error; 1073 1074 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 1075 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 1076 if (error != 0) 1077 goto fail; 1078 1079 switch (rev & URTW_EPROM_CID_MASK) { 1080 case URTW_EPROM_CID_ALPHA0: 1081 sc->sc_strategy = URTW_SW_LED_MODE1; 1082 break; 1083 case URTW_EPROM_CID_SERCOMM_PS: 1084 sc->sc_strategy = URTW_SW_LED_MODE3; 1085 break; 1086 case URTW_EPROM_CID_HW_LED: 1087 sc->sc_strategy = URTW_HW_LED; 1088 break; 1089 case URTW_EPROM_CID_RSVD0: 1090 case URTW_EPROM_CID_RSVD1: 1091 default: 1092 sc->sc_strategy = URTW_SW_LED_MODE0; 1093 break; 1094 } 1095 1096 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 1097 1098 fail: 1099 return error; 1100 } 1101 1102 static usbd_status 1103 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 1104 uint16_t data) 1105 { 1106 usb_device_request_t req; 1107 1108 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1109 req.bRequest = URTW_8187_SETREGS_REQ; 1110 USETW(req.wValue, addr); 1111 USETW(req.wIndex, index); 1112 USETW(req.wLength, sizeof(uint16_t)); 1113 1114 return usbd_do_request(sc->sc_udev, &req, &data); 1115 } 1116 1117 static usbd_status 1118 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 1119 { 1120 int i; 1121 int16_t bit; 1122 uint8_t rlen = 12, wlen = 6; 1123 uint16_t o1, o2, o3, tmp; 1124 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 1125 uint32_t mask = 0x80000000, value = 0; 1126 usbd_status error; 1127 1128 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 1129 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 1130 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 1131 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf); 1132 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf); 1133 o1 &= ~0xf; 1134 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 1135 DELAY(5); 1136 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 1137 DELAY(5); 1138 1139 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 1140 bit = ((d2w & mask) != 0) ? 1 : 0; 1141 1142 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1143 DELAY(2); 1144 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1145 URTW_BB_HOST_BANG_CLK); 1146 DELAY(2); 1147 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1148 URTW_BB_HOST_BANG_CLK); 1149 DELAY(2); 1150 mask = mask >> 1; 1151 if (i == 2) 1152 break; 1153 bit = ((d2w & mask) != 0) ? 1 : 0; 1154 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1155 URTW_BB_HOST_BANG_CLK); 1156 DELAY(2); 1157 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1158 URTW_BB_HOST_BANG_CLK); 1159 DELAY(2); 1160 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1161 DELAY(1); 1162 } 1163 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 1164 URTW_BB_HOST_BANG_CLK); 1165 DELAY(2); 1166 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 1167 DELAY(2); 1168 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 1169 DELAY(2); 1170 1171 mask = 0x800; 1172 for (i = 0; i < rlen; i++, mask = mask >> 1) { 1173 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1174 o1 | URTW_BB_HOST_BANG_RW); 1175 DELAY(2); 1176 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1177 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1178 DELAY(2); 1179 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1180 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1181 DELAY(2); 1182 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1183 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1184 DELAY(2); 1185 1186 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 1187 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 1188 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1189 o1 | URTW_BB_HOST_BANG_RW); 1190 DELAY(2); 1191 } 1192 1193 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 1194 URTW_BB_HOST_BANG_RW); 1195 DELAY(2); 1196 1197 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 1198 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 1199 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0); 1200 1201 if (data != NULL) 1202 *data = value; 1203 fail: 1204 return error; 1205 } 1206 1207 static usbd_status 1208 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 1209 { 1210 uint16_t d80, d82, d84; 1211 usbd_status error; 1212 1213 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 1214 d80 &= 0xfff3; 1215 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 1216 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 1217 d84 &= 0xfff0; 1218 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007); 1219 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007); 1220 DELAY(10); 1221 1222 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1223 DELAY(2); 1224 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 1225 DELAY(10); 1226 1227 error = urtw_8225_write_s16(sc, addr, 0x8225, data); 1228 if (error != 0) 1229 goto fail; 1230 1231 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1232 DELAY(10); 1233 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1234 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 1235 usbd_delay_ms(sc->sc_udev, 2); 1236 fail: 1237 return error; 1238 } 1239 1240 static usbd_status 1241 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 1242 { 1243 uint32_t data; 1244 usbd_status error; 1245 1246 *ret = 1; 1247 1248 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080); 1249 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080); 1250 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080); 1251 usbd_delay_ms(sc->sc_udev, 500); 1252 1253 urtw_8225_write(sc, 0x0, 0x1b7); 1254 1255 error = urtw_8225_read(sc, 0x8, &data); 1256 if (error != 0) 1257 goto fail; 1258 if (data != 0x588) 1259 *ret = 0; 1260 else { 1261 error = urtw_8225_read(sc, 0x9, &data); 1262 if (error != 0) 1263 goto fail; 1264 if (data != 0x700) 1265 *ret = 0; 1266 } 1267 1268 urtw_8225_write(sc, 0x0, 0xb7); 1269 fail: 1270 return error; 1271 } 1272 1273 static usbd_status 1274 urtw_get_rfchip(struct urtw_softc *sc) 1275 { 1276 struct urtw_rf *rf = &sc->sc_rf; 1277 int ret; 1278 uint32_t data; 1279 usbd_status error; 1280 1281 rf->rf_sc = sc; 1282 1283 if (sc->sc_hwrev & URTW_HWREV_8187) { 1284 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 1285 if (error != 0) 1286 return error; 1287 switch (data & 0xff) { 1288 case URTW_EPROM_RFCHIPID_RTL8225U: 1289 error = urtw_8225_isv2(sc, &ret); 1290 if (error != 0) 1291 goto fail; 1292 if (ret == 0) { 1293 rf->init = urtw_8225_rf_init; 1294 rf->set_chan = urtw_8225_rf_set_chan; 1295 rf->set_sens = urtw_8225_rf_set_sens; 1296 printf(", RFv1"); 1297 } else { 1298 rf->init = urtw_8225v2_rf_init; 1299 rf->set_chan = urtw_8225v2_rf_set_chan; 1300 rf->set_sens = NULL; 1301 printf(", RFv2"); 1302 } 1303 break; 1304 default: 1305 goto fail; 1306 } 1307 } else { 1308 rf->init = urtw_8225v2_b_rf_init; 1309 rf->set_chan = urtw_8225v2_b_rf_set_chan; 1310 rf->set_sens = NULL; 1311 } 1312 1313 rf->max_sens = URTW_8225_RF_MAX_SENS; 1314 rf->sens = URTW_8225_RF_DEF_SENS; 1315 1316 return 0; 1317 1318 fail: 1319 aprint_error(": unsupported RF chip %d", data & 0xff); 1320 return USBD_INVAL; 1321 } 1322 1323 static usbd_status 1324 urtw_get_txpwr(struct urtw_softc *sc) 1325 { 1326 int i, j; 1327 uint32_t data; 1328 usbd_status error; 1329 1330 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 1331 if (error != 0) 1332 goto fail; 1333 sc->sc_txpwr_cck_base = data & 0xf; 1334 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 1335 1336 for (i = 1, j = 0; i < 6; i += 2, j++) { 1337 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 1338 if (error != 0) 1339 goto fail; 1340 sc->sc_txpwr_cck[i] = data & 0xf; 1341 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 1342 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 1343 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 1344 } 1345 for (i = 1, j = 0; i < 4; i += 2, j++) { 1346 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 1347 if (error != 0) 1348 goto fail; 1349 sc->sc_txpwr_cck[i + 6] = data & 0xf; 1350 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 1351 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 1352 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 1353 } 1354 if (sc->sc_hwrev & URTW_HWREV_8187) { 1355 for (i = 1, j = 0; i < 4; i += 2, j++) { 1356 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 1357 &data); 1358 if (error != 0) 1359 goto fail; 1360 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 1361 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 1362 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 1363 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = 1364 (data & 0xf000) >> 12; 1365 } 1366 } else { 1367 /* Channel 11. */ 1368 error = urtw_eprom_read32(sc, 0x1b, &data); 1369 if (error != 0) 1370 goto fail; 1371 sc->sc_txpwr_cck[11] = data & 0xf; 1372 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4; 1373 1374 /* Channel 12. */ 1375 error = urtw_eprom_read32(sc, 0xa, &data); 1376 if (error != 0) 1377 goto fail; 1378 sc->sc_txpwr_cck[12] = data & 0xf; 1379 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4; 1380 1381 /* Channel 13, 14. */ 1382 error = urtw_eprom_read32(sc, 0x1c, &data); 1383 if (error != 0) 1384 goto fail; 1385 sc->sc_txpwr_cck[13] = data & 0xf; 1386 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4; 1387 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8; 1388 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12; 1389 } 1390 fail: 1391 return error; 1392 } 1393 1394 static usbd_status 1395 urtw_get_macaddr(struct urtw_softc *sc) 1396 { 1397 struct ieee80211com *ic = &sc->sc_ic; 1398 usbd_status error; 1399 uint32_t data; 1400 1401 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 1402 if (error != 0) 1403 goto fail; 1404 ic->ic_myaddr[0] = data & 0xff; 1405 ic->ic_myaddr[1] = (data & 0xff00) >> 8; 1406 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 1407 if (error != 0) 1408 goto fail; 1409 ic->ic_myaddr[2] = data & 0xff; 1410 ic->ic_myaddr[3] = (data & 0xff00) >> 8; 1411 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 1412 if (error != 0) 1413 goto fail; 1414 ic->ic_myaddr[4] = data & 0xff; 1415 ic->ic_myaddr[5] = (data & 0xff00) >> 8; 1416 fail: 1417 return error; 1418 } 1419 1420 static usbd_status 1421 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 1422 { 1423 #define URTW_READCMD_LEN 3 1424 int addrlen, i; 1425 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 1426 usbd_status error; 1427 1428 /* NB: make sure the buffer is initialized */ 1429 *data = 0; 1430 1431 /* enable EPROM programming */ 1432 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 1433 DELAY(URTW_EPROM_DELAY); 1434 1435 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 1436 if (error != 0) 1437 goto fail; 1438 error = urtw_eprom_ck(sc); 1439 if (error != 0) 1440 goto fail; 1441 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 1442 if (error != 0) 1443 goto fail; 1444 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 1445 addrlen = 8; 1446 addrstr[0] = addr & (1 << 7); 1447 addrstr[1] = addr & (1 << 6); 1448 addrstr[2] = addr & (1 << 5); 1449 addrstr[3] = addr & (1 << 4); 1450 addrstr[4] = addr & (1 << 3); 1451 addrstr[5] = addr & (1 << 2); 1452 addrstr[6] = addr & (1 << 1); 1453 addrstr[7] = addr & (1 << 0); 1454 } else { 1455 addrlen=6; 1456 addrstr[0] = addr & (1 << 5); 1457 addrstr[1] = addr & (1 << 4); 1458 addrstr[2] = addr & (1 << 3); 1459 addrstr[3] = addr & (1 << 2); 1460 addrstr[4] = addr & (1 << 1); 1461 addrstr[5] = addr & (1 << 0); 1462 } 1463 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 1464 if (error != 0) 1465 goto fail; 1466 1467 error = urtw_eprom_writebit(sc, 0); 1468 if (error != 0) 1469 goto fail; 1470 1471 for (i = 0; i < 16; i++) { 1472 error = urtw_eprom_ck(sc); 1473 if (error != 0) 1474 goto fail; 1475 error = urtw_eprom_readbit(sc, &data16); 1476 if (error != 0) 1477 goto fail; 1478 1479 (*data) |= (data16 << (15 - i)); 1480 } 1481 1482 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 1483 if (error != 0) 1484 goto fail; 1485 error = urtw_eprom_ck(sc); 1486 if (error != 0) 1487 goto fail; 1488 1489 /* now disable EPROM programming */ 1490 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 1491 fail: 1492 return error; 1493 #undef URTW_READCMD_LEN 1494 } 1495 1496 static usbd_status 1497 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 1498 { 1499 uint8_t data8; 1500 usbd_status error; 1501 1502 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 1503 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 1504 DELAY(URTW_EPROM_DELAY); 1505 1506 fail: 1507 return error; 1508 } 1509 1510 static usbd_status 1511 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 1512 { 1513 int i = 0; 1514 usbd_status error = 0; 1515 1516 for (i = 0; i < buflen; i++) { 1517 error = urtw_eprom_writebit(sc, buf[i]); 1518 if (error != 0) 1519 goto fail; 1520 error = urtw_eprom_ck(sc); 1521 if (error != 0) 1522 goto fail; 1523 } 1524 fail: 1525 return error; 1526 } 1527 1528 static usbd_status 1529 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 1530 { 1531 uint8_t data; 1532 usbd_status error; 1533 1534 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1535 if (bit != 0) 1536 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 1537 else 1538 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 1539 DELAY(URTW_EPROM_DELAY); 1540 fail: 1541 return error; 1542 } 1543 1544 static usbd_status 1545 urtw_eprom_ck(struct urtw_softc *sc) 1546 { 1547 uint8_t data; 1548 usbd_status error; 1549 1550 /* masking */ 1551 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1552 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 1553 DELAY(URTW_EPROM_DELAY); 1554 /* unmasking */ 1555 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1556 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 1557 DELAY(URTW_EPROM_DELAY); 1558 fail: 1559 return error; 1560 } 1561 1562 static usbd_status 1563 urtw_eprom_cs(struct urtw_softc *sc, int able) 1564 { 1565 uint8_t data; 1566 usbd_status error; 1567 1568 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1569 if (able == URTW_EPROM_ENABLE) 1570 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 1571 else 1572 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 1573 DELAY(URTW_EPROM_DELAY); 1574 fail: 1575 return error; 1576 } 1577 1578 static usbd_status 1579 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx) 1580 { 1581 usb_device_request_t req; 1582 usbd_status error; 1583 1584 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1585 req.bRequest = URTW_8187_GETREGS_REQ; 1586 USETW(req.wValue, val | 0xff00); 1587 USETW(req.wIndex, idx & 0x03); 1588 USETW(req.wLength, sizeof(uint8_t)); 1589 1590 error = usbd_do_request(sc->sc_udev, &req, data); 1591 return error; 1592 } 1593 1594 static usbd_status 1595 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 1596 { 1597 usb_device_request_t req; 1598 usbd_status error; 1599 1600 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1601 req.bRequest = URTW_8187_GETREGS_REQ; 1602 USETW(req.wValue, val | 0xfe00); 1603 USETW(req.wIndex, 0); 1604 USETW(req.wLength, sizeof(uint8_t)); 1605 1606 error = usbd_do_request(sc->sc_udev, &req, data); 1607 return error; 1608 } 1609 1610 static usbd_status 1611 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx) 1612 { 1613 usb_device_request_t req; 1614 usbd_status error; 1615 1616 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1617 req.bRequest = URTW_8187_GETREGS_REQ; 1618 USETW(req.wValue, val | 0xff00); 1619 USETW(req.wIndex, idx & 0x03); 1620 USETW(req.wLength, sizeof(uint16_t)); 1621 1622 error = usbd_do_request(sc->sc_udev, &req, data); 1623 return error; 1624 } 1625 1626 static usbd_status 1627 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx) 1628 { 1629 usb_device_request_t req; 1630 usbd_status error; 1631 1632 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1633 req.bRequest = URTW_8187_GETREGS_REQ; 1634 USETW(req.wValue, val | 0xff00); 1635 USETW(req.wIndex, idx & 0x03); 1636 USETW(req.wLength, sizeof(uint32_t)); 1637 1638 error = usbd_do_request(sc->sc_udev, &req, data); 1639 return error; 1640 } 1641 1642 static usbd_status 1643 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx) 1644 { 1645 usb_device_request_t req; 1646 1647 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1648 req.bRequest = URTW_8187_SETREGS_REQ; 1649 USETW(req.wValue, val | 0xff00); 1650 USETW(req.wIndex, idx & 0x03); 1651 USETW(req.wLength, sizeof(uint8_t)); 1652 1653 return usbd_do_request(sc->sc_udev, &req, &data); 1654 } 1655 1656 static usbd_status 1657 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 1658 { 1659 usb_device_request_t req; 1660 1661 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1662 req.bRequest = URTW_8187_SETREGS_REQ; 1663 USETW(req.wValue, val | 0xfe00); 1664 USETW(req.wIndex, 0); 1665 USETW(req.wLength, sizeof(uint8_t)); 1666 1667 return usbd_do_request(sc->sc_udev, &req, &data); 1668 } 1669 1670 static usbd_status 1671 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) 1672 { 1673 usb_device_request_t req; 1674 1675 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1676 req.bRequest = URTW_8187_SETREGS_REQ; 1677 USETW(req.wValue, val | 0xff00); 1678 USETW(req.wIndex, idx & 0x03); 1679 USETW(req.wLength, sizeof(uint16_t)); 1680 1681 return usbd_do_request(sc->sc_udev, &req, &data); 1682 } 1683 1684 static usbd_status 1685 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) 1686 { 1687 usb_device_request_t req; 1688 1689 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1690 req.bRequest = URTW_8187_SETREGS_REQ; 1691 USETW(req.wValue, val | 0xff00); 1692 USETW(req.wIndex, idx & 0x03); 1693 USETW(req.wLength, sizeof(uint32_t)); 1694 1695 return usbd_do_request(sc->sc_udev, &req, &data); 1696 } 1697 1698 static usbd_status 1699 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1700 { 1701 uint8_t data; 1702 usbd_status error; 1703 1704 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1705 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1706 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1707 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1708 fail: 1709 return error; 1710 } 1711 1712 static usbd_status 1713 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 1714 { 1715 uint8_t data; 1716 usbd_status error; 1717 1718 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1719 if (error) 1720 goto fail; 1721 1722 urtw_read8_m(sc, URTW_CONFIG3, &data); 1723 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1724 urtw_write32_m(sc, URTW_ANAPARAM, val); 1725 urtw_read8_m(sc, URTW_CONFIG3, &data); 1726 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1727 1728 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1729 if (error) 1730 goto fail; 1731 fail: 1732 return error; 1733 } 1734 1735 static usbd_status 1736 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 1737 { 1738 uint8_t data; 1739 usbd_status error; 1740 1741 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1742 if (error) 1743 goto fail; 1744 1745 urtw_read8_m(sc, URTW_CONFIG3, &data); 1746 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1747 urtw_write32_m(sc, URTW_ANAPARAM2, val); 1748 urtw_read8_m(sc, URTW_CONFIG3, &data); 1749 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1750 1751 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1752 if (error) 1753 goto fail; 1754 fail: 1755 return error; 1756 } 1757 1758 static usbd_status 1759 urtw_intr_disable(struct urtw_softc *sc) 1760 { 1761 usbd_status error; 1762 1763 urtw_write16_m(sc, URTW_INTR_MASK, 0); 1764 1765 fail: 1766 return error; 1767 } 1768 1769 static usbd_status 1770 urtw_reset(struct urtw_softc *sc) 1771 { 1772 uint8_t data; 1773 usbd_status error; 1774 1775 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1776 if (error) 1777 goto fail; 1778 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1779 if (error) 1780 goto fail; 1781 1782 error = urtw_intr_disable(sc); 1783 if (error) 1784 goto fail; 1785 usbd_delay_ms(sc->sc_udev, 100); 1786 1787 error = urtw_write8e(sc, 0x18, 0x10); 1788 if (error != 0) 1789 goto fail; 1790 error = urtw_write8e(sc, 0x18, 0x11); 1791 if (error != 0) 1792 goto fail; 1793 error = urtw_write8e(sc, 0x18, 0x00); 1794 if (error != 0) 1795 goto fail; 1796 usbd_delay_ms(sc->sc_udev, 100); 1797 1798 urtw_read8_m(sc, URTW_CMD, &data); 1799 data = (data & 2) | URTW_CMD_RST; 1800 urtw_write8_m(sc, URTW_CMD, data); 1801 usbd_delay_ms(sc->sc_udev, 100); 1802 1803 urtw_read8_m(sc, URTW_CMD, &data); 1804 if (data & URTW_CMD_RST) { 1805 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 1806 goto fail; 1807 } 1808 1809 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 1810 if (error) 1811 goto fail; 1812 usbd_delay_ms(sc->sc_udev, 100); 1813 1814 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1815 if (error) 1816 goto fail; 1817 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1818 if (error) 1819 goto fail; 1820 fail: 1821 return error; 1822 } 1823 1824 static usbd_status 1825 urtw_led_on(struct urtw_softc *sc, int type) 1826 { 1827 usbd_status error; 1828 1829 if (type == URTW_LED_GPIO) { 1830 switch (sc->sc_gpio_ledpin) { 1831 case URTW_LED_PIN_GPIO0: 1832 urtw_write8_m(sc, URTW_GPIO, 0x01); 1833 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 1834 break; 1835 default: 1836 panic("unsupported LED PIN type %#x", 1837 sc->sc_gpio_ledpin); 1838 /* NOTREACHED */ 1839 } 1840 } else { 1841 panic("unsupported LED type %#x", type); 1842 /* NOTREACHED */ 1843 } 1844 1845 sc->sc_gpio_ledon = 1; 1846 fail: 1847 return error; 1848 } 1849 1850 static usbd_status 1851 urtw_led_off(struct urtw_softc *sc, int type) 1852 { 1853 usbd_status error; 1854 1855 if (type == URTW_LED_GPIO) { 1856 switch (sc->sc_gpio_ledpin) { 1857 case URTW_LED_PIN_GPIO0: 1858 urtw_write8_m(sc, URTW_GPIO, 0x01); 1859 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01); 1860 break; 1861 default: 1862 panic("unsupported LED PIN type %#x", 1863 sc->sc_gpio_ledpin); 1864 /* NOTREACHED */ 1865 } 1866 } else { 1867 panic("unsupported LED type %#x", type); 1868 /* NOTREACHED */ 1869 } 1870 1871 sc->sc_gpio_ledon = 0; 1872 1873 fail: 1874 return error; 1875 } 1876 1877 static usbd_status 1878 urtw_led_mode0(struct urtw_softc *sc, int mode) 1879 { 1880 switch (mode) { 1881 case URTW_LED_CTL_POWER_ON: 1882 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 1883 break; 1884 case URTW_LED_CTL_TX: 1885 if (sc->sc_gpio_ledinprogress == 1) 1886 return 0; 1887 1888 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 1889 sc->sc_gpio_blinktime = 2; 1890 break; 1891 case URTW_LED_CTL_LINK: 1892 sc->sc_gpio_ledstate = URTW_LED_ON; 1893 break; 1894 default: 1895 panic("unsupported LED mode %#x", mode); 1896 /* NOTREACHED */ 1897 } 1898 1899 switch (sc->sc_gpio_ledstate) { 1900 case URTW_LED_ON: 1901 if (sc->sc_gpio_ledinprogress != 0) 1902 break; 1903 urtw_led_on(sc, URTW_LED_GPIO); 1904 break; 1905 case URTW_LED_BLINK_NORMAL: 1906 if (sc->sc_gpio_ledinprogress != 0) 1907 break; 1908 sc->sc_gpio_ledinprogress = 1; 1909 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 1910 URTW_LED_OFF : URTW_LED_ON; 1911 if (!sc->sc_dying) 1912 callout_schedule(&sc->sc_led_ch, mstohz(100)); 1913 break; 1914 case URTW_LED_POWER_ON_BLINK: 1915 urtw_led_on(sc, URTW_LED_GPIO); 1916 usbd_delay_ms(sc->sc_udev, 100); 1917 urtw_led_off(sc, URTW_LED_GPIO); 1918 break; 1919 default: 1920 panic("unknown LED status %#x", sc->sc_gpio_ledstate); 1921 /* NOTREACHED */ 1922 } 1923 return 0; 1924 } 1925 1926 static usbd_status 1927 urtw_led_mode1(struct urtw_softc *sc, int mode) 1928 { 1929 return USBD_INVAL; 1930 } 1931 1932 static usbd_status 1933 urtw_led_mode2(struct urtw_softc *sc, int mode) 1934 { 1935 return USBD_INVAL; 1936 } 1937 1938 static usbd_status 1939 urtw_led_mode3(struct urtw_softc *sc, int mode) 1940 { 1941 return USBD_INVAL; 1942 } 1943 1944 static void 1945 urtw_ledusbtask(void *arg) 1946 { 1947 struct urtw_softc *sc = arg; 1948 1949 if (sc->sc_strategy != URTW_SW_LED_MODE0) 1950 panic("could not process a LED strategy %#x", sc->sc_strategy); 1951 1952 urtw_led_blink(sc); 1953 } 1954 1955 static void 1956 urtw_ledtask(void *arg) 1957 { 1958 struct urtw_softc *sc = arg; 1959 1960 /* 1961 * NB: to change a status of the led we need at least a sleep so we 1962 * can't do it here 1963 */ 1964 usb_add_task(sc->sc_udev, &sc->sc_ledtask, USB_TASKQ_DRIVER); 1965 } 1966 1967 static usbd_status 1968 urtw_led_ctl(struct urtw_softc *sc, int mode) 1969 { 1970 usbd_status error = 0; 1971 1972 switch (sc->sc_strategy) { 1973 case URTW_SW_LED_MODE0: 1974 error = urtw_led_mode0(sc, mode); 1975 break; 1976 case URTW_SW_LED_MODE1: 1977 error = urtw_led_mode1(sc, mode); 1978 break; 1979 case URTW_SW_LED_MODE2: 1980 error = urtw_led_mode2(sc, mode); 1981 break; 1982 case URTW_SW_LED_MODE3: 1983 error = urtw_led_mode3(sc, mode); 1984 break; 1985 default: 1986 panic("unsupported LED mode %d", sc->sc_strategy); 1987 /* NOTREACHED */ 1988 } 1989 1990 return error; 1991 } 1992 1993 static usbd_status 1994 urtw_led_blink(struct urtw_softc *sc) 1995 { 1996 uint8_t ing = 0; 1997 1998 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 1999 (void)urtw_led_on(sc, URTW_LED_GPIO); 2000 else 2001 (void)urtw_led_off(sc, URTW_LED_GPIO); 2002 sc->sc_gpio_blinktime--; 2003 if (sc->sc_gpio_blinktime == 0) 2004 ing = 1; 2005 else { 2006 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 2007 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 2008 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 2009 ing = 1; 2010 } 2011 if (ing == 1) { 2012 if (sc->sc_gpio_ledstate == URTW_LED_ON && 2013 sc->sc_gpio_ledon == 0) 2014 (void)urtw_led_on(sc, URTW_LED_GPIO); 2015 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 2016 sc->sc_gpio_ledon == 1) 2017 (void)urtw_led_off(sc, URTW_LED_GPIO); 2018 2019 sc->sc_gpio_blinktime = 0; 2020 sc->sc_gpio_ledinprogress = 0; 2021 return 0; 2022 } 2023 2024 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 2025 URTW_LED_ON : URTW_LED_OFF; 2026 2027 switch (sc->sc_gpio_ledstate) { 2028 case URTW_LED_BLINK_NORMAL: 2029 if (!sc->sc_dying) 2030 callout_schedule(&sc->sc_led_ch, mstohz(100)); 2031 break; 2032 default: 2033 panic("unknown LED status %#x", sc->sc_gpio_ledstate); 2034 /* NOTREACHED */ 2035 } 2036 return 0; 2037 } 2038 2039 static usbd_status 2040 urtw_update_msr(struct urtw_softc *sc) 2041 { 2042 struct ieee80211com *ic = &sc->sc_ic; 2043 uint8_t data; 2044 usbd_status error; 2045 2046 urtw_read8_m(sc, URTW_MSR, &data); 2047 data &= ~URTW_MSR_LINK_MASK; 2048 2049 /* Should always be set. */ 2050 if (sc->sc_hwrev & URTW_HWREV_8187B) 2051 data |= URTW_MSR_LINK_ENEDCA; 2052 2053 if (sc->sc_state == IEEE80211_S_RUN) { 2054 switch (ic->ic_opmode) { 2055 case IEEE80211_M_STA: 2056 case IEEE80211_M_MONITOR: 2057 data |= URTW_MSR_LINK_STA; 2058 break; 2059 default: 2060 panic("unsupported operation mode %#x", 2061 ic->ic_opmode); 2062 /* NOTREACHED */ 2063 } 2064 } else 2065 data |= URTW_MSR_LINK_NONE; 2066 2067 urtw_write8_m(sc, URTW_MSR, data); 2068 fail: 2069 return error; 2070 } 2071 2072 static uint16_t 2073 urtw_rate2rtl(int rate) 2074 { 2075 unsigned int i; 2076 2077 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2078 if (rate == urtw_ratetable[i].reg) 2079 return urtw_ratetable[i].val; 2080 } 2081 2082 return 3; 2083 } 2084 2085 static uint16_t 2086 urtw_rtl2rate(int rate) 2087 { 2088 unsigned int i; 2089 2090 for (i = 0; i < __arraycount(urtw_ratetable); i++) { 2091 if (rate == urtw_ratetable[i].val) 2092 return urtw_ratetable[i].reg; 2093 } 2094 2095 return 0; 2096 } 2097 2098 static usbd_status 2099 urtw_set_rate(struct urtw_softc *sc) 2100 { 2101 int i, basic_rate, min_rr_rate, max_rr_rate; 2102 uint16_t data; 2103 usbd_status error; 2104 2105 basic_rate = urtw_rate2rtl(48); 2106 min_rr_rate = urtw_rate2rtl(12); 2107 max_rr_rate = urtw_rate2rtl(48); 2108 2109 urtw_write8_m(sc, URTW_RESP_RATE, 2110 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 2111 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 2112 2113 urtw_read16_m(sc, URTW_8187_BRSR, &data); 2114 data &= ~URTW_BRSR_MBR_8185; 2115 2116 for (i = 0; i <= basic_rate; i++) 2117 data |= (1 << i); 2118 2119 urtw_write16_m(sc, URTW_8187_BRSR, data); 2120 fail: 2121 return error; 2122 } 2123 2124 static usbd_status 2125 urtw_intr_enable(struct urtw_softc *sc) 2126 { 2127 usbd_status error; 2128 2129 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 2130 fail: 2131 return error; 2132 } 2133 2134 static usbd_status 2135 urtw_rx_setconf(struct urtw_softc *sc) 2136 { 2137 struct ifnet *ifp = sc->sc_ic.ic_ifp; 2138 struct ieee80211com *ic = &sc->sc_ic; 2139 uint32_t data; 2140 usbd_status error; 2141 2142 urtw_read32_m(sc, URTW_RX, &data); 2143 data = data &~ URTW_RX_FILTER_MASK; 2144 #if 0 2145 data = data | URTW_RX_FILTER_CTL; 2146 #endif 2147 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 2148 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 2149 2150 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2151 data = data | URTW_RX_FILTER_ICVERR; 2152 data = data | URTW_RX_FILTER_PWR; 2153 } 2154 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 2155 data = data | URTW_RX_FILTER_CRCERR; 2156 2157 if (ic->ic_opmode == IEEE80211_M_MONITOR || 2158 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) { 2159 data = data | URTW_RX_FILTER_ALLMAC; 2160 } else { 2161 data = data | URTW_RX_FILTER_NICMAC; 2162 data = data | URTW_RX_CHECK_BSSID; 2163 } 2164 2165 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 2166 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY; 2167 data = data &~ URTW_MAX_RX_DMA_MASK; 2168 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 2169 2170 urtw_write32_m(sc, URTW_RX, data); 2171 fail: 2172 return error; 2173 } 2174 2175 static usbd_status 2176 urtw_rx_enable(struct urtw_softc *sc) 2177 { 2178 int i; 2179 struct urtw_rx_data *rx_data; 2180 uint8_t data; 2181 usbd_status error; 2182 2183 /* 2184 * Start up the receive pipe. 2185 */ 2186 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 2187 rx_data = &sc->sc_rx_data[i]; 2188 2189 usbd_setup_xfer(rx_data->xfer, rx_data, rx_data->buf, MCLBYTES, 2190 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 2191 error = usbd_transfer(rx_data->xfer); 2192 if (error != USBD_IN_PROGRESS && error != 0) { 2193 printf("%s: could not queue Rx transfer\n", 2194 device_xname(sc->sc_dev)); 2195 goto fail; 2196 } 2197 } 2198 2199 error = urtw_rx_setconf(sc); 2200 if (error != 0) 2201 goto fail; 2202 2203 urtw_read8_m(sc, URTW_CMD, &data); 2204 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 2205 fail: 2206 return error; 2207 } 2208 2209 static usbd_status 2210 urtw_tx_enable(struct urtw_softc *sc) 2211 { 2212 uint8_t data8; 2213 uint32_t data; 2214 usbd_status error; 2215 2216 if (sc->sc_hwrev & URTW_HWREV_8187) { 2217 urtw_read8_m(sc, URTW_CW_CONF, &data8); 2218 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | 2219 URTW_CW_CONF_PERPACKET_RETRY); 2220 urtw_write8_m(sc, URTW_CW_CONF, data8); 2221 2222 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 2223 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 2224 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 2225 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 2226 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 2227 2228 urtw_read32_m(sc, URTW_TX_CONF, &data); 2229 data &= ~URTW_TX_LOOPBACK_MASK; 2230 data |= URTW_TX_LOOPBACK_NONE; 2231 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 2232 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 2233 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 2234 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 2235 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 2236 data &= ~URTW_TX_SWPLCPLEN; 2237 data |= URTW_TX_NOICV; 2238 urtw_write32_m(sc, URTW_TX_CONF, data); 2239 } else { 2240 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE | 2241 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY | 2242 URTW_TX_LONGRETRY; 2243 urtw_write32_m(sc, URTW_TX_CONF, data); 2244 } 2245 2246 urtw_read8_m(sc, URTW_CMD, &data8); 2247 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 2248 fail: 2249 return error; 2250 } 2251 2252 static int 2253 urtw_init(struct ifnet *ifp) 2254 { 2255 struct urtw_softc *sc = ifp->if_softc; 2256 struct urtw_rf *rf = &sc->sc_rf; 2257 struct ieee80211com *ic = &sc->sc_ic; 2258 usbd_status error; 2259 2260 urtw_stop(ifp, 0); 2261 2262 error = urtw_reset(sc); 2263 if (error) 2264 goto fail; 2265 2266 urtw_write8_m(sc, 0x85, 0); 2267 urtw_write8_m(sc, URTW_GPIO, 0); 2268 2269 /* for led */ 2270 urtw_write8_m(sc, 0x85, 4); 2271 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 2272 if (error != 0) 2273 goto fail; 2274 2275 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2276 if (error) 2277 goto fail; 2278 2279 /* applying MAC address again. */ 2280 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 2281 error = urtw_set_macaddr(sc, ic->ic_myaddr); 2282 if (error) 2283 goto fail; 2284 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2285 if (error) 2286 goto fail; 2287 2288 error = urtw_update_msr(sc); 2289 if (error) 2290 goto fail; 2291 2292 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 2293 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 2294 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81); 2295 error = urtw_set_rate(sc); 2296 if (error != 0) 2297 goto fail; 2298 2299 error = rf->init(rf); 2300 if (error != 0) 2301 goto fail; 2302 if (rf->set_sens != NULL) 2303 rf->set_sens(rf); 2304 2305 urtw_write16_m(sc, 0x5e, 1); 2306 urtw_write16_m(sc, 0xfe, 0x10); 2307 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 2308 urtw_write8_m(sc, 0xff, 0x60); 2309 urtw_write16_m(sc, 0x5e, 0); 2310 urtw_write8_m(sc, 0x85, 4); 2311 2312 error = urtw_intr_enable(sc); 2313 if (error != 0) 2314 goto fail; 2315 2316 /* reset softc variables */ 2317 for (size_t j = 0; j < URTW_PRIORITY_MAX; j++) { 2318 sc->sc_txidx[j] = sc->sc_tx_queued[j] = 0; 2319 } 2320 sc->sc_txtimer = 0; 2321 2322 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 2323 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 2324 if (error != 0) { 2325 aprint_error_dev(sc->sc_dev, "failed to set configuration" 2326 ", err=%s\n", usbd_errstr(error)); 2327 goto fail; 2328 } 2329 /* get the first interface handle */ 2330 error = usbd_device2interface_handle(sc->sc_udev, 2331 URTW_IFACE_INDEX, &sc->sc_iface); 2332 if (error != 0) { 2333 printf("%s: could not get interface handle\n", 2334 device_xname(sc->sc_dev)); 2335 goto fail; 2336 } 2337 error = urtw_open_pipes(sc); 2338 if (error != 0) 2339 goto fail; 2340 error = urtw_alloc_rx_data_list(sc); 2341 if (error != 0) 2342 goto fail; 2343 error = urtw_alloc_tx_data_list(sc); 2344 if (error != 0) 2345 goto fail; 2346 sc->sc_flags |= URTW_INIT_ONCE; 2347 } 2348 2349 error = urtw_rx_enable(sc); 2350 if (error != 0) 2351 goto fail; 2352 error = urtw_tx_enable(sc); 2353 if (error != 0) 2354 goto fail; 2355 2356 ifp->if_flags &= ~IFF_OACTIVE; 2357 ifp->if_flags |= IFF_RUNNING; 2358 2359 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2360 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2361 else 2362 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2363 2364 return 0; 2365 fail: 2366 return error; 2367 } 2368 2369 static int 2370 urtw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2371 { 2372 #define IS_RUNNING(ifp) \ 2373 (((ifp)->if_flags & IFF_UP) && ((ifp)->if_flags & IFF_RUNNING)) 2374 2375 struct urtw_softc *sc = ifp->if_softc; 2376 struct ieee80211com *ic = &sc->sc_ic; 2377 int s, error = 0; 2378 2379 if (sc->sc_dying) 2380 return ENXIO; 2381 2382 s = splnet(); 2383 2384 switch (cmd) { 2385 case SIOCSIFFLAGS: 2386 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2387 break; 2388 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2389 case IFF_UP|IFF_RUNNING: 2390 break; 2391 case IFF_UP: 2392 if_init(ifp); 2393 break; 2394 case IFF_RUNNING: 2395 urtw_stop(ifp, 1); 2396 break; 2397 case 0: 2398 break; 2399 } 2400 break; 2401 2402 case SIOCADDMULTI: 2403 case SIOCDELMULTI: 2404 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) 2405 error = 0; 2406 break; 2407 2408 default: 2409 error = ieee80211_ioctl(ic, cmd, data); 2410 break; 2411 } 2412 2413 if (error == ENETRESET) { 2414 if (IS_RUNNING(ifp) && 2415 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)) 2416 if_init(ifp); 2417 error = 0; 2418 } 2419 2420 splx(s); 2421 2422 return error; 2423 #undef IS_RUNNING 2424 } 2425 2426 static void 2427 urtw_start(struct ifnet *ifp) 2428 { 2429 struct urtw_softc *sc = ifp->if_softc; 2430 struct ieee80211com *ic = &sc->sc_ic; 2431 struct ieee80211_node *ni; 2432 struct ether_header *eh; 2433 struct mbuf *m0; 2434 2435 /* 2436 * net80211 may still try to send management frames even if the 2437 * IFF_RUNNING flag is not set... 2438 */ 2439 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2440 return; 2441 2442 for (;;) { 2443 IF_POLL(&ic->ic_mgtq, m0); 2444 if (m0 != NULL) { 2445 2446 if (sc->sc_tx_queued[URTW_PRIORITY_NORMAL] >= 2447 URTW_TX_DATA_LIST_COUNT) { 2448 ifp->if_flags |= IFF_OACTIVE; 2449 break; 2450 } 2451 IF_DEQUEUE(&ic->ic_mgtq, m0); 2452 ni = M_GETCTX(m0, struct ieee80211_node *); 2453 M_CLEARCTX(m0); 2454 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 2455 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2456 != 0) 2457 break; 2458 } else { 2459 if (ic->ic_state != IEEE80211_S_RUN) 2460 break; 2461 IFQ_POLL(&ifp->if_snd, m0); 2462 if (m0 == NULL) 2463 break; 2464 if (sc->sc_tx_queued[URTW_PRIORITY_NORMAL] >= 2465 URTW_TX_DATA_LIST_COUNT) { 2466 ifp->if_flags |= IFF_OACTIVE; 2467 break; 2468 } 2469 IFQ_DEQUEUE(&ifp->if_snd, m0); 2470 if (m0->m_len < sizeof(struct ether_header) && 2471 !(m0 = m_pullup(m0, sizeof(struct ether_header)))) 2472 continue; 2473 2474 eh = mtod(m0, struct ether_header *); 2475 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2476 if (ni == NULL) { 2477 m_freem(m0); 2478 continue; 2479 } 2480 bpf_mtap(ifp, m0, BPF_D_OUT); 2481 m0 = ieee80211_encap(ic, m0, ni); 2482 if (m0 == NULL) { 2483 ieee80211_free_node(ni); 2484 continue; 2485 } 2486 bpf_mtap3(ic->ic_rawbpf, m0, BPF_D_OUT); 2487 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2488 != 0) { 2489 ieee80211_free_node(ni); 2490 if_statinc(ifp, if_oerrors); 2491 break; 2492 } 2493 } 2494 sc->sc_txtimer = 5; 2495 ifp->if_timer = 1; 2496 } 2497 } 2498 2499 static void 2500 urtw_watchdog(struct ifnet *ifp) 2501 { 2502 struct urtw_softc *sc = ifp->if_softc; 2503 2504 ifp->if_timer = 0; 2505 2506 if (sc->sc_txtimer > 0) { 2507 if (--sc->sc_txtimer == 0) { 2508 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 2509 if_statinc(ifp, if_oerrors); 2510 return; 2511 } 2512 ifp->if_timer = 1; 2513 } 2514 2515 ieee80211_watchdog(&sc->sc_ic); 2516 } 2517 2518 static void 2519 urtw_txeof_low(struct usbd_xfer *xfer, void *priv, 2520 usbd_status status) 2521 { 2522 struct urtw_tx_data *data = priv; 2523 struct urtw_softc *sc = data->sc; 2524 struct ieee80211com *ic = &sc->sc_ic; 2525 struct ifnet *ifp = ic->ic_ifp; 2526 int s; 2527 2528 if (status != USBD_NORMAL_COMPLETION) { 2529 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2530 return; 2531 2532 printf("%s: could not transmit buffer: %s\n", 2533 device_xname(sc->sc_dev), usbd_errstr(status)); 2534 2535 if (status == USBD_STALLED) 2536 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low); 2537 2538 if_statinc(ifp, if_oerrors); 2539 return; 2540 } 2541 2542 s = splnet(); 2543 2544 ieee80211_free_node(data->ni); 2545 data->ni = NULL; 2546 2547 sc->sc_txtimer = 0; 2548 if_statinc(ifp, if_opackets); 2549 2550 sc->sc_tx_queued[URTW_PRIORITY_LOW]--; 2551 ifp->if_flags &= ~IFF_OACTIVE; 2552 urtw_start(ifp); 2553 2554 splx(s); 2555 } 2556 2557 static void 2558 urtw_txeof_normal(struct usbd_xfer *xfer, void *priv, 2559 usbd_status status) 2560 { 2561 struct urtw_tx_data *data = priv; 2562 struct urtw_softc *sc = data->sc; 2563 struct ieee80211com *ic = &sc->sc_ic; 2564 struct ifnet *ifp = ic->ic_ifp; 2565 int s; 2566 2567 if (status != USBD_NORMAL_COMPLETION) { 2568 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2569 return; 2570 2571 printf("%s: could not transmit buffer: %s\n", 2572 device_xname(sc->sc_dev), usbd_errstr(status)); 2573 2574 if (status == USBD_STALLED) 2575 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal); 2576 2577 if_statinc(ifp, if_oerrors); 2578 return; 2579 } 2580 2581 s = splnet(); 2582 2583 ieee80211_free_node(data->ni); 2584 data->ni = NULL; 2585 2586 sc->sc_txtimer = 0; 2587 if_statinc(ifp, if_opackets); 2588 2589 sc->sc_tx_queued[URTW_PRIORITY_NORMAL]--; 2590 ifp->if_flags &= ~IFF_OACTIVE; 2591 urtw_start(ifp); 2592 2593 splx(s); 2594 } 2595 2596 static int 2597 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 2598 int prior) 2599 { 2600 struct ieee80211com *ic = &sc->sc_ic; 2601 struct urtw_tx_data *data; 2602 struct ieee80211_frame *wh; 2603 struct ieee80211_key *k; 2604 usbd_status error; 2605 int xferlen; 2606 2607 wh = mtod(m0, struct ieee80211_frame *); 2608 2609 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2610 k = ieee80211_crypto_encap(ic, ni, m0); 2611 if (k == NULL) { 2612 m_freem(m0); 2613 return ENOBUFS; 2614 } 2615 /* packet header may have moved, reset our local pointer */ 2616 wh = mtod(m0, struct ieee80211_frame *); 2617 } 2618 2619 if (sc->sc_drvbpf != NULL) { 2620 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 2621 2622 tap->wt_flags = 0; 2623 tap->wt_rate = 0; 2624 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2625 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2626 2627 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0, BPF_D_OUT); 2628 } 2629 2630 if (sc->sc_hwrev & URTW_HWREV_8187) 2631 xferlen = m0->m_pkthdr.len + 4 * 3; 2632 else 2633 xferlen = m0->m_pkthdr.len + 4 * 8; 2634 2635 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 2636 xferlen += 1; 2637 2638 data = &sc->sc_tx_data[prior][sc->sc_txidx[prior]]; 2639 sc->sc_txidx[prior] = 2640 (sc->sc_txidx[prior] + 1) % URTW_TX_DATA_LIST_COUNT; 2641 2642 memset(data->buf, 0, URTW_TX_MAXSIZE); 2643 data->buf[0] = m0->m_pkthdr.len & 0xff; 2644 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8; 2645 data->buf[1] |= (1 << 7); 2646 2647 /* XXX sc_preamble_mode is always 2. */ 2648 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2649 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 2650 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0)) 2651 data->buf[2] |= 1; 2652 if ((m0->m_pkthdr.len > ic->ic_rtsthreshold) && 2653 prior == URTW_PRIORITY_LOW) 2654 panic("TODO tx."); 2655 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2656 data->buf[2] |= (1 << 1); 2657 /* RTS rate - 10 means we use a basic rate. */ 2658 data->buf[2] |= (urtw_rate2rtl(2) << 3); 2659 /* 2660 * XXX currently TX rate control depends on the rate value of 2661 * RX descriptor because I don't know how to we can control TX rate 2662 * in more smart way. Please fix me you find a thing. 2663 */ 2664 data->buf[3] = sc->sc_currate; 2665 if (prior == URTW_PRIORITY_NORMAL) { 2666 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2667 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]); 2668 else if (ic->ic_fixed_rate != -1) 2669 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate); 2670 } 2671 2672 if (sc->sc_hwrev & URTW_HWREV_8187) { 2673 data->buf[8] = 3; /* CW minimum */ 2674 data->buf[8] |= (7 << 4); /* CW maximum */ 2675 data->buf[9] |= 11; /* retry limitation */ 2676 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]); 2677 } else { 2678 data->buf[21] |= 11; /* retry limitation */ 2679 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]); 2680 } 2681 2682 data->ni = ni; 2683 2684 /* mbuf is no longer needed. */ 2685 m_freem(m0); 2686 2687 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2688 USBD_FORCE_SHORT_XFER, URTW_DATA_TIMEOUT, 2689 (prior == URTW_PRIORITY_LOW) ? urtw_txeof_low : urtw_txeof_normal); 2690 error = usbd_transfer(data->xfer); 2691 if (error != USBD_IN_PROGRESS && error != USBD_NORMAL_COMPLETION) { 2692 printf("%s: could not send frame: %s\n", 2693 device_xname(sc->sc_dev), usbd_errstr(error)); 2694 return EIO; 2695 } 2696 2697 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 2698 if (error != 0) 2699 printf("%s: could not control LED (%d)\n", 2700 device_xname(sc->sc_dev), error); 2701 2702 sc->sc_tx_queued[prior]++; 2703 2704 return 0; 2705 } 2706 2707 static usbd_status 2708 urtw_8225_usb_init(struct urtw_softc *sc) 2709 { 2710 uint8_t data; 2711 usbd_status error; 2712 2713 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2714 urtw_write8_m(sc, URTW_GPIO, 0); 2715 error = urtw_read8e(sc, 0x53, &data); 2716 if (error) 2717 goto fail; 2718 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2719 if (error) 2720 goto fail; 2721 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2722 urtw_write8_m(sc, URTW_GPIO, 0x20); 2723 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2724 2725 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2726 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2727 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2728 2729 usbd_delay_ms(sc->sc_udev, 500); 2730 fail: 2731 return error; 2732 } 2733 2734 static usbd_status 2735 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2736 { 2737 usbd_status error = 0; 2738 2739 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2740 fail: 2741 return error; 2742 } 2743 2744 static usbd_status 2745 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2746 { 2747 uint32_t phyw; 2748 usbd_status error; 2749 2750 phyw = ((data << 8) | (addr | 0x80)); 2751 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24)); 2752 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16)); 2753 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8)); 2754 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff))); 2755 /* 2756 * Delay removed from 8185 to 8187. 2757 * usbd_delay_ms(sc->sc_udev, 1); 2758 */ 2759 fail: 2760 return error; 2761 } 2762 2763 static usbd_status 2764 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2765 { 2766 data = data & 0xff; 2767 return urtw_8187_write_phy(sc, addr, data); 2768 } 2769 2770 static usbd_status 2771 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2772 { 2773 data = data & 0xff; 2774 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2775 } 2776 2777 static usbd_status 2778 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2779 { 2780 usbd_status error; 2781 2782 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2783 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2784 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2785 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2786 fail: 2787 return error; 2788 } 2789 2790 static usbd_status 2791 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2792 { 2793 int i, idx, set; 2794 uint8_t *cck_pwltable; 2795 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2796 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2797 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2798 usbd_status error; 2799 2800 cck_pwrlvl_max = 11; 2801 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2802 ofdm_pwrlvl_min = 10; 2803 2804 /* CCK power setting */ 2805 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2806 idx = cck_pwrlvl % 6; 2807 set = cck_pwrlvl / 6; 2808 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2809 urtw_8225_txpwr_cck; 2810 2811 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2812 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2813 for (i = 0; i < 8; i++) { 2814 urtw_8187_write_phy_cck(sc, 0x44 + i, 2815 cck_pwltable[idx * 8 + i]); 2816 } 2817 usbd_delay_ms(sc->sc_udev, 1); 2818 2819 /* OFDM power setting */ 2820 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2821 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2822 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2823 2824 idx = ofdm_pwrlvl % 6; 2825 set = ofdm_pwrlvl / 6; 2826 2827 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 2828 if (error) 2829 goto fail; 2830 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2831 urtw_8187_write_phy_ofdm(sc, 6, 0); 2832 urtw_8187_write_phy_ofdm(sc, 8, 0); 2833 2834 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2835 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2836 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2837 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2838 usbd_delay_ms(sc->sc_udev, 1); 2839 fail: 2840 return error; 2841 } 2842 2843 static usbd_status 2844 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2845 { 2846 usbd_status error; 2847 2848 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2849 usbd_delay_ms(sc->sc_udev, 1); 2850 fail: 2851 return error; 2852 } 2853 2854 static usbd_status 2855 urtw_8225_rf_init(struct urtw_rf *rf) 2856 { 2857 struct urtw_softc *sc = rf->rf_sc; 2858 unsigned int i; 2859 uint16_t data; 2860 usbd_status error; 2861 2862 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 2863 if (error) 2864 goto fail; 2865 2866 error = urtw_8225_usb_init(sc); 2867 if (error) 2868 goto fail; 2869 2870 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2871 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 2872 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 2873 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2874 2875 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2876 if (error) 2877 goto fail; 2878 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2879 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2880 if (error) 2881 goto fail; 2882 2883 error = urtw_8185_rf_pins_enable(sc); 2884 if (error) 2885 goto fail; 2886 2887 usbd_delay_ms(sc->sc_udev, 500); 2888 2889 for (i = 0; i < __arraycount(urtw_8225_rf_part1); i++) { 2890 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2891 urtw_8225_rf_part1[i].val); 2892 } 2893 usbd_delay_ms(sc->sc_udev, 50); 2894 urtw_8225_write(sc, 0x2, 0xc4d); 2895 usbd_delay_ms(sc->sc_udev, 200); 2896 urtw_8225_write(sc, 0x2, 0x44d); 2897 usbd_delay_ms(sc->sc_udev, 200); 2898 urtw_8225_write(sc, 0x0, 0x127); 2899 2900 for (i = 0; i < __arraycount(urtw_8225_rxgain); i++) { 2901 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 2902 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]); 2903 } 2904 2905 urtw_8225_write(sc, 0x0, 0x27); 2906 urtw_8225_write(sc, 0x0, 0x22f); 2907 2908 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 2909 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2910 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2911 } 2912 2913 for (i = 0; i < __arraycount(urtw_8225_rf_part2); i++) { 2914 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2915 urtw_8225_rf_part2[i].val); 2916 usbd_delay_ms(sc->sc_udev, 1); 2917 } 2918 2919 error = urtw_8225_setgain(sc, 4); 2920 if (error) 2921 goto fail; 2922 2923 for (i = 0; i < __arraycount(urtw_8225_rf_part3); i++) { 2924 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2925 urtw_8225_rf_part3[i].val); 2926 usbd_delay_ms(sc->sc_udev, 1); 2927 } 2928 2929 urtw_write8_m(sc, 0x5b, 0x0d); 2930 2931 error = urtw_8225_set_txpwrlvl(sc, 1); 2932 if (error) 2933 goto fail; 2934 2935 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2936 usbd_delay_ms(sc->sc_udev, 1); 2937 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2938 usbd_delay_ms(sc->sc_udev, 1); 2939 2940 /* TX ant A, 0x0 for B */ 2941 error = urtw_8185_tx_antenna(sc, 0x3); 2942 if (error) 2943 goto fail; 2944 urtw_write32_m(sc, 0x94, 0x3dc00002); 2945 2946 error = urtw_8225_rf_set_chan(rf, 1); 2947 fail: 2948 return error; 2949 } 2950 2951 static usbd_status 2952 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan) 2953 { 2954 struct urtw_softc *sc = rf->rf_sc; 2955 struct ieee80211com *ic = &sc->sc_ic; 2956 struct ieee80211_channel *c = ic->ic_ibss_chan; 2957 usbd_status error; 2958 2959 error = urtw_8225_set_txpwrlvl(sc, chan); 2960 if (error) 2961 goto fail; 2962 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 2963 usbd_delay_ms(sc->sc_udev, 10); 2964 2965 urtw_write8_m(sc, URTW_SIFS, 0x22); 2966 2967 if (sc->sc_state == IEEE80211_S_ASSOC && 2968 ic->ic_flags & IEEE80211_F_SHSLOT) 2969 urtw_write8_m(sc, URTW_SLOT, 0x9); 2970 else 2971 urtw_write8_m(sc, URTW_SLOT, 0x14); 2972 2973 if (IEEE80211_IS_CHAN_G(c)) { 2974 urtw_write8_m(sc, URTW_DIFS, 0x14); 2975 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 2976 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 2977 } else { 2978 urtw_write8_m(sc, URTW_DIFS, 0x24); 2979 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 2980 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 2981 } 2982 2983 fail: 2984 return error; 2985 } 2986 2987 static usbd_status 2988 urtw_8225_rf_set_sens(struct urtw_rf *rf) 2989 { 2990 struct urtw_softc *sc = rf->rf_sc; 2991 usbd_status error; 2992 2993 if (rf->sens > 6) 2994 return -1; 2995 2996 if (rf->sens > 4) 2997 urtw_8225_write(sc, 0x0c, 0x850); 2998 else 2999 urtw_8225_write(sc, 0x0c, 0x50); 3000 3001 rf->sens = 6 - rf->sens; 3002 error = urtw_8225_setgain(sc, rf->sens); 3003 if (error) 3004 goto fail; 3005 3006 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]); 3007 3008 fail: 3009 return error; 3010 } 3011 3012 static void 3013 urtw_stop(struct ifnet *ifp, int disable) 3014 { 3015 struct urtw_softc *sc = ifp->if_softc; 3016 struct ieee80211com *ic = &sc->sc_ic; 3017 uint8_t data; 3018 usbd_status error; 3019 3020 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3021 3022 sc->sc_txtimer = 0; 3023 ifp->if_timer = 0; 3024 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3025 3026 callout_stop(&sc->scan_to); 3027 callout_stop(&sc->sc_led_ch); 3028 3029 urtw_intr_disable(sc); 3030 urtw_read8_m(sc, URTW_CMD, &data); 3031 data &= ~URTW_CMD_TX_ENABLE; 3032 data &= ~URTW_CMD_RX_ENABLE; 3033 urtw_write8_m(sc, URTW_CMD, data); 3034 3035 if (sc->sc_rxpipe != NULL) 3036 usbd_abort_pipe(sc->sc_rxpipe); 3037 if (sc->sc_txpipe_low != NULL) 3038 usbd_abort_pipe(sc->sc_txpipe_low); 3039 if (sc->sc_txpipe_normal != NULL) 3040 usbd_abort_pipe(sc->sc_txpipe_normal); 3041 3042 fail: 3043 return; 3044 } 3045 3046 static int 3047 urtw_isbmode(uint16_t rate) 3048 { 3049 rate = urtw_rtl2rate(rate); 3050 3051 return ((rate <= 22 && rate != 12 && rate != 18) || 3052 rate == 44) ? 1 : 0; 3053 } 3054 3055 static void 3056 urtw_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 3057 { 3058 struct urtw_rx_data *data = priv; 3059 struct urtw_softc *sc = data->sc; 3060 struct ieee80211com *ic = &sc->sc_ic; 3061 struct ifnet *ifp = ic->ic_ifp; 3062 struct ieee80211_frame *wh; 3063 struct ieee80211_node *ni; 3064 struct mbuf *m, *mnew; 3065 uint8_t *desc, quality, rate; 3066 int actlen, flen, len, rssi, s; 3067 3068 if (status != USBD_NORMAL_COMPLETION) { 3069 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 3070 return; 3071 3072 if (status == USBD_STALLED) 3073 usbd_clear_endpoint_stall_async(sc->sc_rxpipe); 3074 if_statinc(ifp, if_ierrors); 3075 goto skip; 3076 } 3077 3078 usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); 3079 if (actlen < URTW_MIN_RXBUFSZ) { 3080 if_statinc(ifp, if_ierrors); 3081 goto skip; 3082 } 3083 3084 if (sc->sc_hwrev & URTW_HWREV_8187) 3085 /* 4 dword and 4 byte CRC */ 3086 len = actlen - (4 * 4); 3087 else 3088 /* 5 dword and 4 byte CRC */ 3089 len = actlen - (4 * 5); 3090 3091 desc = data->buf + len; 3092 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff); 3093 if (flen > actlen) { 3094 if_statinc(ifp, if_ierrors); 3095 goto skip; 3096 } 3097 3098 rate = (desc[2] & 0xf0) >> 4; 3099 if (sc->sc_hwrev & URTW_HWREV_8187) { 3100 quality = desc[4] & 0xff; 3101 rssi = (desc[6] & 0xfe) >> 1; 3102 3103 /* XXX correct? */ 3104 if (!urtw_isbmode(rate)) { 3105 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi); 3106 rssi = ((90 - rssi) * 100) / 65; 3107 } else { 3108 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi); 3109 rssi = ((95 - rssi) * 100) / 65; 3110 } 3111 } else { 3112 quality = desc[12]; 3113 rssi = 14 - desc[14] / 2; 3114 } 3115 3116 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 3117 if (mnew == NULL) { 3118 printf("%s: could not allocate rx mbuf\n", 3119 device_xname(sc->sc_dev)); 3120 if_statinc(ifp, if_ierrors); 3121 goto skip; 3122 } 3123 MCLGET(mnew, M_DONTWAIT); 3124 if (!(mnew->m_flags & M_EXT)) { 3125 printf("%s: could not allocate rx mbuf cluster\n", 3126 device_xname(sc->sc_dev)); 3127 m_freem(mnew); 3128 if_statinc(ifp, if_ierrors); 3129 goto skip; 3130 } 3131 3132 m = data->m; 3133 data->m = mnew; 3134 data->buf = mtod(mnew, uint8_t *); 3135 3136 /* finalize mbuf */ 3137 m_set_rcvif(m, ifp); 3138 m->m_pkthdr.len = m->m_len = flen - 4; 3139 3140 s = splnet(); 3141 3142 if (sc->sc_drvbpf != NULL) { 3143 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3144 3145 /* XXX Are variables correct? */ 3146 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 3147 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 3148 tap->wr_dbm_antsignal = (int8_t)rssi; 3149 3150 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 3151 } 3152 wh = mtod(m, struct ieee80211_frame *); 3153 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3154 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3155 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3156 3157 /* XXX correct? */ 3158 if (!urtw_isbmode(rate)) { 3159 if (quality > 127) 3160 quality = 0; 3161 else if (quality < 27) 3162 quality = 100; 3163 else 3164 quality = 127 - quality; 3165 } else 3166 quality = (quality > 64) ? 0 : ((64 - quality) * 100) / 64; 3167 3168 /* send the frame to the 802.11 layer */ 3169 ieee80211_input(ic, m, ni, rssi, 0); 3170 3171 /* node is no longer needed */ 3172 ieee80211_free_node(ni); 3173 3174 splx(s); 3175 3176 skip: /* setup a new transfer */ 3177 usbd_setup_xfer(xfer, data, data->buf, MCLBYTES, 3178 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 3179 (void)usbd_transfer(xfer); 3180 } 3181 3182 static usbd_status 3183 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3184 { 3185 uint8_t *gainp; 3186 usbd_status error; 3187 3188 /* XXX for A? */ 3189 gainp = urtw_8225v2_gain_bg; 3190 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3191 usbd_delay_ms(sc->sc_udev, 1); 3192 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3193 usbd_delay_ms(sc->sc_udev, 1); 3194 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3195 usbd_delay_ms(sc->sc_udev, 1); 3196 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3197 usbd_delay_ms(sc->sc_udev, 1); 3198 fail: 3199 return error; 3200 } 3201 3202 static usbd_status 3203 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3204 { 3205 int i; 3206 uint8_t *cck_pwrtable; 3207 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3208 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3209 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3210 usbd_status error; 3211 3212 /* CCK power setting */ 3213 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3214 cck_pwrlvl += sc->sc_txpwr_cck_base; 3215 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3216 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3217 urtw_8225v2_txpwr_cck; 3218 3219 for (i = 0; i < 8; i++) { 3220 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3221 } 3222 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3223 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3224 usbd_delay_ms(sc->sc_udev, 1); 3225 3226 /* OFDM power setting */ 3227 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3228 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3229 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3230 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3231 3232 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 3233 if (error) 3234 goto fail; 3235 3236 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3237 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3238 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3239 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3240 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3241 3242 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3243 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3244 usbd_delay_ms(sc->sc_udev, 1); 3245 fail: 3246 return error; 3247 } 3248 3249 static usbd_status 3250 urtw_8225v2_rf_init(struct urtw_rf *rf) 3251 { 3252 struct urtw_softc *sc = rf->rf_sc; 3253 int i; 3254 uint16_t data; 3255 uint32_t data32; 3256 usbd_status error; 3257 3258 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 3259 if (error) 3260 goto fail; 3261 3262 error = urtw_8225_usb_init(sc); 3263 if (error) 3264 goto fail; 3265 3266 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 3267 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 3268 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 3269 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 3270 3271 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3272 if (error) 3273 goto fail; 3274 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 3275 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3276 if (error) 3277 goto fail; 3278 3279 error = urtw_8185_rf_pins_enable(sc); 3280 if (error) 3281 goto fail; 3282 3283 usbd_delay_ms(sc->sc_udev, 1000); 3284 3285 for (i = 0; i < __arraycount(urtw_8225v2_rf_part1); i++) { 3286 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 3287 urtw_8225v2_rf_part1[i].val); 3288 usbd_delay_ms(sc->sc_udev, 1); 3289 } 3290 usbd_delay_ms(sc->sc_udev, 50); 3291 3292 urtw_8225_write(sc, 0x0, 0x1b7); 3293 3294 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3295 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3296 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3297 } 3298 3299 urtw_8225_write(sc, 0x3, 0x2); 3300 urtw_8225_write(sc, 0x5, 0x4); 3301 urtw_8225_write(sc, 0x0, 0xb7); 3302 urtw_8225_write(sc, 0x2, 0xc4d); 3303 usbd_delay_ms(sc->sc_udev, 100); 3304 urtw_8225_write(sc, 0x2, 0x44d); 3305 usbd_delay_ms(sc->sc_udev, 100); 3306 3307 error = urtw_8225_read(sc, 0x6, &data32); 3308 if (error != 0) 3309 goto fail; 3310 if (data32 != 0xe6) 3311 printf("%s: expect 0xe6!! (%#x)\n", device_xname(sc->sc_dev), 3312 data32); 3313 if (!(data32 & 0x80)) { 3314 urtw_8225_write(sc, 0x02, 0x0c4d); 3315 usbd_delay_ms(sc->sc_udev, 200); 3316 urtw_8225_write(sc, 0x02, 0x044d); 3317 usbd_delay_ms(sc->sc_udev, 100); 3318 error = urtw_8225_read(sc, 0x6, &data32); 3319 if (error != 0) 3320 goto fail; 3321 if (!(data32 & 0x80)) 3322 printf("%s: RF calibration failed\n", 3323 device_xname(sc->sc_dev)); 3324 } 3325 usbd_delay_ms(sc->sc_udev, 100); 3326 3327 urtw_8225_write(sc, 0x0, 0x2bf); 3328 for (i = 0; i < __arraycount(urtw_8225_agc); i++) { 3329 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 3330 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 3331 } 3332 3333 for (i = 0; i < __arraycount(urtw_8225v2_rf_part2); i++) { 3334 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 3335 urtw_8225v2_rf_part2[i].val); 3336 } 3337 3338 error = urtw_8225v2_setgain(sc, 4); 3339 if (error) 3340 goto fail; 3341 3342 for (i = 0; i < __arraycount(urtw_8225v2_rf_part3); i++) { 3343 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 3344 urtw_8225v2_rf_part3[i].val); 3345 } 3346 3347 urtw_write8_m(sc, 0x5b, 0x0d); 3348 3349 error = urtw_8225v2_set_txpwrlvl(sc, 1); 3350 if (error) 3351 goto fail; 3352 3353 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 3354 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 3355 3356 /* TX ant A, 0x0 for B */ 3357 error = urtw_8185_tx_antenna(sc, 0x3); 3358 if (error) 3359 goto fail; 3360 urtw_write32_m(sc, 0x94, 0x3dc00002); 3361 3362 error = urtw_8225_rf_set_chan(rf, 1); 3363 fail: 3364 return error; 3365 } 3366 3367 static usbd_status 3368 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan) 3369 { 3370 struct urtw_softc *sc = rf->rf_sc; 3371 struct ieee80211com *ic = &sc->sc_ic; 3372 struct ieee80211_channel *c = ic->ic_ibss_chan; 3373 usbd_status error; 3374 3375 error = urtw_8225v2_set_txpwrlvl(sc, chan); 3376 if (error) 3377 goto fail; 3378 3379 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3380 usbd_delay_ms(sc->sc_udev, 10); 3381 3382 urtw_write8_m(sc, URTW_SIFS, 0x22); 3383 3384 if(sc->sc_state == IEEE80211_S_ASSOC && 3385 ic->ic_flags & IEEE80211_F_SHSLOT) 3386 urtw_write8_m(sc, URTW_SLOT, 0x9); 3387 else 3388 urtw_write8_m(sc, URTW_SLOT, 0x14); 3389 3390 if (IEEE80211_IS_CHAN_G(c)) { 3391 urtw_write8_m(sc, URTW_DIFS, 0x14); 3392 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 3393 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 3394 } else { 3395 urtw_write8_m(sc, URTW_DIFS, 0x24); 3396 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 3397 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 3398 } 3399 3400 fail: 3401 return error; 3402 } 3403 3404 static void 3405 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c) 3406 { 3407 struct urtw_rf *rf = &sc->sc_rf; 3408 struct ieee80211com *ic = &sc->sc_ic; 3409 usbd_status error = 0; 3410 uint32_t data; 3411 u_int chan; 3412 3413 chan = ieee80211_chan2ieee(ic, c); 3414 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3415 return; 3416 /* 3417 * During changing the channel we need to temporary disable 3418 * TX. 3419 */ 3420 urtw_read32_m(sc, URTW_TX_CONF, &data); 3421 data &= ~URTW_TX_LOOPBACK_MASK; 3422 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 3423 error = rf->set_chan(rf, chan); 3424 if (error != 0) { 3425 printf("%s could not change the channel\n", 3426 device_xname(sc->sc_dev)); 3427 return; 3428 } 3429 usbd_delay_ms(sc->sc_udev, 10); 3430 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE); 3431 3432 fail: return; 3433 3434 } 3435 3436 static void 3437 urtw_next_scan(void *arg) 3438 { 3439 struct urtw_softc *sc = arg; 3440 struct ieee80211com *ic = &sc->sc_ic; 3441 int s; 3442 3443 if (sc->sc_dying) 3444 return; 3445 3446 s = splnet(); 3447 if (ic->ic_state == IEEE80211_S_SCAN) 3448 ieee80211_next_scan(ic); 3449 splx(s); 3450 } 3451 3452 static void 3453 urtw_task(void *arg) 3454 { 3455 struct urtw_softc *sc = arg; 3456 struct ieee80211com *ic = &sc->sc_ic; 3457 struct ieee80211_node *ni; 3458 enum ieee80211_state ostate; 3459 usbd_status error = 0; 3460 3461 if (sc->sc_dying) 3462 return; 3463 3464 ostate = ic->ic_state; 3465 3466 switch (sc->sc_state) { 3467 case IEEE80211_S_INIT: 3468 if (ostate == IEEE80211_S_RUN) { 3469 /* turn link LED off */ 3470 (void)urtw_led_off(sc, URTW_LED_GPIO); 3471 } 3472 break; 3473 3474 case IEEE80211_S_SCAN: 3475 urtw_set_chan(sc, ic->ic_curchan); 3476 if (!sc->sc_dying) 3477 callout_schedule(&sc->scan_to, mstohz(200)); 3478 break; 3479 3480 case IEEE80211_S_AUTH: 3481 case IEEE80211_S_ASSOC: 3482 urtw_set_chan(sc, ic->ic_curchan); 3483 break; 3484 3485 case IEEE80211_S_RUN: 3486 ni = ic->ic_bss; 3487 3488 urtw_set_chan(sc, ic->ic_curchan); 3489 3490 /* setting bssid. */ 3491 error = urtw_set_bssid(sc, ni->ni_bssid); 3492 if (error != 0) 3493 goto fail; 3494 urtw_update_msr(sc); 3495 /* XXX maybe the below would be incorrect. */ 3496 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3497 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 3498 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 3499 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff); 3500 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 3501 if (error != 0) 3502 printf("%s: could not control LED (%d)\n", 3503 device_xname(sc->sc_dev), error); 3504 break; 3505 } 3506 3507 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg); 3508 3509 fail: 3510 if (error != 0) { 3511 DPRINTF(("%s: error duing processing RUN state.", 3512 device_xname(sc->sc_dev))); 3513 } 3514 } 3515 3516 static usbd_status 3517 urtw_8187b_update_wmm(struct urtw_softc *sc) 3518 { 3519 struct ieee80211com *ic = &sc->sc_ic; 3520 struct ieee80211_channel *c = ic->ic_ibss_chan; 3521 uint32_t data; 3522 uint8_t aifs, sifs, slot, ecwmin, ecwmax; 3523 usbd_status error; 3524 3525 sifs = 0xa; 3526 if (IEEE80211_IS_CHAN_G(c)) 3527 slot = 0x9; 3528 else 3529 slot = 0x14; 3530 3531 aifs = (2 * slot) + sifs; 3532 ecwmin = 3; 3533 ecwmax = 7; 3534 3535 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */ 3536 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */ 3537 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */ 3538 3539 urtw_write32_m(sc, URTW_AC_VO, data); 3540 urtw_write32_m(sc, URTW_AC_VI, data); 3541 urtw_write32_m(sc, URTW_AC_BE, data); 3542 urtw_write32_m(sc, URTW_AC_BK, data); 3543 3544 fail: 3545 return error; 3546 } 3547 3548 static usbd_status 3549 urtw_8187b_reset(struct urtw_softc *sc) 3550 { 3551 uint8_t data; 3552 usbd_status error; 3553 3554 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3555 if (error) 3556 goto fail; 3557 3558 urtw_read8_m(sc, URTW_CONFIG3, &data); 3559 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE | 3560 URTW_CONFIG3_GNT_SELECT); 3561 3562 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 3563 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 3564 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 3565 3566 urtw_write8_m(sc, 0x61, 0x10); 3567 urtw_read8_m(sc, 0x62, &data); 3568 urtw_write8_m(sc, 0x62, data & ~(1 << 5)); 3569 urtw_write8_m(sc, 0x62, data | (1 << 5)); 3570 3571 urtw_read8_m(sc, URTW_CONFIG3, &data); 3572 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3573 3574 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3575 if (error) 3576 goto fail; 3577 3578 urtw_read8_m(sc, URTW_CMD, &data); 3579 data = (data & 2) | URTW_CMD_RST; 3580 urtw_write8_m(sc, URTW_CMD, data); 3581 usbd_delay_ms(sc->sc_udev, 100); 3582 3583 urtw_read8_m(sc, URTW_CMD, &data); 3584 if (data & URTW_CMD_RST) { 3585 printf("%s: reset timeout\n", device_xname(sc->sc_dev)); 3586 goto fail; 3587 } 3588 3589 fail: 3590 return error; 3591 } 3592 3593 static int 3594 urtw_8187b_init(struct ifnet *ifp) 3595 { 3596 struct urtw_softc *sc = ifp->if_softc; 3597 struct urtw_rf *rf = &sc->sc_rf; 3598 struct ieee80211com *ic = &sc->sc_ic; 3599 uint8_t data; 3600 usbd_status error; 3601 3602 urtw_stop(ifp, 0); 3603 3604 error = urtw_8187b_update_wmm(sc); 3605 if (error != 0) 3606 goto fail; 3607 error = urtw_8187b_reset(sc); 3608 if (error) 3609 goto fail; 3610 3611 /* Applying MAC address again. */ 3612 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3613 if (error) 3614 goto fail; 3615 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3616 error = urtw_set_macaddr(sc, ic->ic_myaddr); 3617 if (error) 3618 goto fail; 3619 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3620 if (error) 3621 goto fail; 3622 3623 error = urtw_update_msr(sc); 3624 if (error) 3625 goto fail; 3626 3627 error = rf->init(rf); 3628 if (error != 0) 3629 goto fail; 3630 3631 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE | 3632 URTW_CMD_RX_ENABLE); 3633 error = urtw_intr_enable(sc); 3634 if (error != 0) 3635 goto fail; 3636 3637 error = urtw_write8e(sc, 0x41, 0xf4); 3638 if (error != 0) 3639 goto fail; 3640 error = urtw_write8e(sc, 0x40, 0x00); 3641 if (error != 0) 3642 goto fail; 3643 error = urtw_write8e(sc, 0x42, 0x00); 3644 if (error != 0) 3645 goto fail; 3646 error = urtw_write8e(sc, 0x42, 0x01); 3647 if (error != 0) 3648 goto fail; 3649 error = urtw_write8e(sc, 0x40, 0x0f); 3650 if (error != 0) 3651 goto fail; 3652 error = urtw_write8e(sc, 0x42, 0x00); 3653 if (error != 0) 3654 goto fail; 3655 error = urtw_write8e(sc, 0x42, 0x01); 3656 if (error != 0) 3657 goto fail; 3658 3659 urtw_read8_m(sc, 0xdb, &data); 3660 urtw_write8_m(sc, 0xdb, data | (1 << 2)); 3661 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3); 3662 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3); 3663 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3); 3664 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3); 3665 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3); 3666 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3); 3667 urtw_write8_m(sc, 0x61, 0); 3668 urtw_write8_idx_m(sc, 0x80, 0x0f, 1); 3669 urtw_write8_idx_m(sc, 0x83, 0x03, 1); 3670 urtw_write8_m(sc, 0xda, 0x10); 3671 urtw_write8_idx_m(sc, 0x4d, 0x08, 2); 3672 3673 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 3674 3675 urtw_write16_idx_m(sc, 0xec, 0x0800, 1); 3676 3677 urtw_write8_m(sc, URTW_ACM_CONTROL, 0); 3678 3679 /* Reset softc variables. */ 3680 for (size_t j = 0; j < URTW_PRIORITY_MAX; j++) { 3681 sc->sc_txidx[j] = sc->sc_tx_queued[j] = 0; 3682 } 3683 sc->sc_txtimer = 0; 3684 3685 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 3686 error = usbd_set_config_no(sc->sc_udev, URTW_CONFIG_NO, 0); 3687 if (error != 0) { 3688 aprint_error_dev(sc->sc_dev, "failed to set configuration" 3689 ", err=%s\n", usbd_errstr(error)); 3690 3691 goto fail; 3692 } 3693 /* Get the first interface handle. */ 3694 error = usbd_device2interface_handle(sc->sc_udev, 3695 URTW_IFACE_INDEX, &sc->sc_iface); 3696 if (error != 0) { 3697 printf("%s: could not get interface handle\n", 3698 device_xname(sc->sc_dev)); 3699 goto fail; 3700 } 3701 error = urtw_open_pipes(sc); 3702 if (error != 0) 3703 goto fail; 3704 error = urtw_alloc_rx_data_list(sc); 3705 if (error != 0) 3706 goto fail; 3707 error = urtw_alloc_tx_data_list(sc); 3708 if (error != 0) 3709 goto fail; 3710 sc->sc_flags |= URTW_INIT_ONCE; 3711 } 3712 3713 error = urtw_rx_enable(sc); 3714 if (error != 0) 3715 goto fail; 3716 error = urtw_tx_enable(sc); 3717 if (error != 0) 3718 goto fail; 3719 3720 ifp->if_flags &= ~IFF_OACTIVE; 3721 ifp->if_flags |= IFF_RUNNING; 3722 3723 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3724 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3725 else 3726 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3727 3728 fail: 3729 return error; 3730 } 3731 3732 static usbd_status 3733 urtw_8225v2_b_config_mac(struct urtw_softc *sc) 3734 { 3735 int i; 3736 usbd_status error; 3737 3738 for (i = 0; i < __arraycount(urtw_8187b_regtbl); i++) { 3739 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg, 3740 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx); 3741 } 3742 3743 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3744 urtw_write16_m(sc, URTW_INT_MIG, 0); 3745 3746 urtw_write32_idx_m(sc, 0xf0, 0, 1); 3747 urtw_write32_idx_m(sc, 0xf4, 0, 1); 3748 urtw_write8_idx_m(sc, 0xf8, 0, 1); 3749 3750 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001); 3751 3752 fail: 3753 return error; 3754 } 3755 3756 static usbd_status 3757 urtw_8225v2_b_init_rfe(struct urtw_softc *sc) 3758 { 3759 usbd_status error; 3760 3761 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3762 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3763 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3764 usbd_delay_ms(sc->sc_udev, 100); 3765 3766 fail: 3767 return error; 3768 } 3769 3770 static usbd_status 3771 urtw_8225v2_b_update_chan(struct urtw_softc *sc) 3772 { 3773 struct ieee80211com *ic = &sc->sc_ic; 3774 struct ieee80211_channel *c = ic->ic_ibss_chan; 3775 uint8_t aifs, difs, eifs, sifs, slot; 3776 usbd_status error; 3777 3778 urtw_write8_m(sc, URTW_SIFS, 0x22); 3779 3780 sifs = 0xa; 3781 if (IEEE80211_IS_CHAN_G(c)) { 3782 slot = 0x9; 3783 difs = 0x1c; 3784 eifs = 0x5b; 3785 } else { 3786 slot = 0x14; 3787 difs = 0x32; 3788 eifs = 0x5b; 3789 } 3790 aifs = (2 * slot) + sifs; 3791 3792 urtw_write8_m(sc, URTW_SLOT, slot); 3793 3794 urtw_write8_m(sc, URTW_AC_VO, aifs); 3795 urtw_write8_m(sc, URTW_AC_VI, aifs); 3796 urtw_write8_m(sc, URTW_AC_BE, aifs); 3797 urtw_write8_m(sc, URTW_AC_BK, aifs); 3798 3799 urtw_write8_m(sc, URTW_DIFS, difs); 3800 urtw_write8_m(sc, URTW_8187B_EIFS, eifs); 3801 3802 fail: 3803 return error; 3804 } 3805 3806 static usbd_status 3807 urtw_8225v2_b_rf_init(struct urtw_rf *rf) 3808 { 3809 struct urtw_softc *sc = rf->rf_sc; 3810 unsigned int i; 3811 uint8_t data; 3812 usbd_status error; 3813 3814 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */ 3815 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff); 3816 urtw_read8_m(sc, URTW_CW_CONF, &data); 3817 urtw_write8_m(sc, URTW_CW_CONF, data | 3818 URTW_CW_CONF_PERPACKET_RETRY); 3819 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data); 3820 urtw_write8_m(sc, URTW_TX_AGC_CTL, data | 3821 URTW_TX_AGC_CTL_PERPACKET_GAIN | 3822 URTW_TX_AGC_CTL_PERPACKET_ANTSEL); 3823 3824 /* Auto rate fallback control. */ 3825 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */ 3826 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data); 3827 urtw_write8_m(sc, URTW_RATE_FALLBACK, data | 3828 URTW_RATE_FALLBACK_ENABLE); 3829 3830 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3831 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3832 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1); 3833 3834 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3835 if (error) 3836 goto fail; 3837 urtw_read8_m(sc, URTW_CONFIG1, &data); 3838 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80); 3839 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3840 if (error) 3841 goto fail; 3842 3843 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3844 urtw_8225v2_b_config_mac(sc); 3845 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2); 3846 3847 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3848 if (error) 3849 goto fail; 3850 urtw_read8_m(sc, URTW_CONFIG3, &data); 3851 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3852 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3853 if (error) 3854 goto fail; 3855 3856 urtw_8225v2_b_init_rfe(sc); 3857 3858 for (i = 0; i < __arraycount(urtw_8225v2_b_rf); i++) { 3859 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg, 3860 urtw_8225v2_b_rf[i].val); 3861 } 3862 3863 for (i = 0; i < __arraycount(urtw_8225v2_rxgain); i++) { 3864 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3865 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3866 } 3867 3868 urtw_8225_write(sc, 0x03, 0x080); 3869 urtw_8225_write(sc, 0x05, 0x004); 3870 urtw_8225_write(sc, 0x00, 0x0b7); 3871 urtw_8225_write(sc, 0x02, 0xc4d); 3872 urtw_8225_write(sc, 0x02, 0x44d); 3873 urtw_8225_write(sc, 0x00, 0x2bf); 3874 3875 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3876 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3877 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3878 3879 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3880 for (i = 0; i < __arraycount(urtw_8225v2_agc); i++) { 3881 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]); 3882 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80); 3883 urtw_8187_write_phy_ofdm(sc, 0x0e, 0); 3884 } 3885 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3886 3887 for (i = 0; i < __arraycount(urtw_8225v2_ofdm); i++) 3888 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]); 3889 3890 urtw_8225v2_b_update_chan(sc); 3891 3892 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3893 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3894 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3895 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3896 3897 error = urtw_8225v2_b_rf_set_chan(rf, 1); 3898 fail: 3899 return error; 3900 } 3901 3902 static usbd_status 3903 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan) 3904 { 3905 struct urtw_softc *sc = rf->rf_sc; 3906 usbd_status error; 3907 3908 error = urtw_8225v2_b_set_txpwrlvl(sc, chan); 3909 if (error) 3910 goto fail; 3911 3912 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3913 /* 3914 * Delay removed from 8185 to 8187. 3915 * usbd_delay_ms(sc->sc_udev, 10); 3916 */ 3917 3918 urtw_write16_m(sc, URTW_AC_VO, 0x5114); 3919 urtw_write16_m(sc, URTW_AC_VI, 0x5114); 3920 urtw_write16_m(sc, URTW_AC_BE, 0x5114); 3921 urtw_write16_m(sc, URTW_AC_BK, 0x5114); 3922 3923 fail: 3924 return error; 3925 } 3926 3927 static usbd_status 3928 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3929 { 3930 int i; 3931 uint8_t *cck_pwrtable; 3932 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min, 3933 ofdm_pwrlvl_max; 3934 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3935 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3936 usbd_status error; 3937 3938 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3939 cck_pwrlvl_min = 0; 3940 cck_pwrlvl_max = 15; 3941 ofdm_pwrlvl_min = 2; 3942 ofdm_pwrlvl_max = 17; 3943 } else { 3944 cck_pwrlvl_min = 7; 3945 cck_pwrlvl_max = 22; 3946 ofdm_pwrlvl_min = 10; 3947 ofdm_pwrlvl_max = 25; 3948 } 3949 3950 /* CCK power setting */ 3951 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ? 3952 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min); 3953 3954 cck_pwrlvl += sc->sc_txpwr_cck_base; 3955 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3956 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl; 3957 3958 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3959 urtw_8225v2_txpwr_cck; 3960 3961 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3962 if (cck_pwrlvl <= 6) 3963 ; /* do nothing */ 3964 else if (cck_pwrlvl <= 11) 3965 cck_pwrtable += 8; 3966 else 3967 cck_pwrtable += 16; 3968 } else { 3969 if (cck_pwrlvl <= 5) 3970 ; /* do nothing */ 3971 else if (cck_pwrlvl <= 11) 3972 cck_pwrtable += 8; 3973 else if (cck_pwrlvl <= 17) 3974 cck_pwrtable += 16; 3975 else 3976 cck_pwrtable += 24; 3977 } 3978 3979 for (i = 0; i < 8; i++) { 3980 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3981 } 3982 3983 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3984 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3985 /* 3986 * Delay removed from 8185 to 8187. 3987 * usbd_delay_ms(sc->sc_udev, 1); 3988 */ 3989 3990 /* OFDM power setting */ 3991 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3992 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3993 3994 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3995 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3996 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl; 3997 3998 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3999 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 4000 4001 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 4002 if (ofdm_pwrlvl <= 11) { 4003 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 4004 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 4005 } else { 4006 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4007 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4008 } 4009 } else { 4010 if (ofdm_pwrlvl <= 11) { 4011 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4012 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4013 } else if (ofdm_pwrlvl <= 17) { 4014 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 4015 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 4016 } else { 4017 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 4018 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 4019 } 4020 } 4021 4022 /* 4023 * Delay removed from 8185 to 8187. 4024 * usbd_delay_ms(sc->sc_udev, 1); 4025 */ 4026 fail: 4027 return error; 4028 } 4029 4030 static int 4031 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid) 4032 { 4033 int error; 4034 4035 urtw_write32_m(sc, URTW_BSSID, 4036 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 4037 urtw_write16_m(sc, URTW_BSSID + 4, 4038 bssid[4] | bssid[5] << 8); 4039 4040 return 0; 4041 4042 fail: 4043 return error; 4044 } 4045 4046 static int 4047 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr) 4048 { 4049 int error; 4050 4051 urtw_write32_m(sc, URTW_MAC0, 4052 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 4053 urtw_write16_m(sc, URTW_MAC4, 4054 addr[4] | addr[5] << 8); 4055 4056 return 0; 4057 4058 fail: 4059 return error; 4060 } 4061 4062 MODULE(MODULE_CLASS_DRIVER, if_urtw, NULL); 4063 4064 #ifdef _MODULE 4065 #include "ioconf.c" 4066 #endif 4067 4068 static int 4069 if_urtw_modcmd(modcmd_t cmd, void *aux) 4070 { 4071 int error = 0; 4072 4073 switch (cmd) { 4074 case MODULE_CMD_INIT: 4075 #ifdef _MODULE 4076 error = config_init_component(cfdriver_ioconf_urtw, 4077 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4078 #endif 4079 return error; 4080 case MODULE_CMD_FINI: 4081 #ifdef _MODULE 4082 error = config_fini_component(cfdriver_ioconf_urtw, 4083 cfattach_ioconf_urtw, cfdata_ioconf_urtw); 4084 #endif 4085 return error; 4086 default: 4087 return ENOTTY; 4088 } 4089 } 4090
Indexes created Sun Oct 25 00:26:45 UTC 2026