1 /* $NetBSD: ehci_pci.c,v 1.80 2026/05/02 07:23:00 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.80 2026/05/02 07:23:00 tsutsui Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 enum ehci_pci_quirk_flags { 64 EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */ 65 EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */ 66 }; 67 68 static const struct pci_quirkdata ehci_pci_quirks[] = { 69 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI, 70 EHCI_PCI_QUIRK_AMD_SB600 }, 71 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI, 72 EHCI_PCI_QUIRK_AMD_SB700 }, 73 }; 74 75 static void ehci_release_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t); 76 static void ehci_get_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t); 77 static bool ehci_pci_suspend(device_t, const pmf_qual_t *); 78 static bool ehci_pci_resume(device_t, const pmf_qual_t *); 79 80 struct ehci_pci_softc { 81 ehci_softc_t sc; 82 pci_chipset_tag_t sc_pc; 83 pcitag_t sc_tag; 84 pci_intr_handle_t *sc_pihp; 85 void *sc_ih; /* interrupt vectoring */ 86 enum { 87 EHCI_INIT_NONE, 88 EHCI_INIT_OWNER, 89 EHCI_INIT_INITED 90 } sc_init_state; 91 }; 92 93 static void ehci_pci_release_resources(struct ehci_pci_softc *); 94 static int ehci_sb700_match(const struct pci_attach_args *); 95 static int ehci_apply_amd_quirks(struct ehci_pci_softc *); 96 static enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t, 97 pci_product_id_t); 98 99 #define EHCI_MAX_BIOS_WAIT 100 /* ms*10 */ 100 #define EHCI_SBx00_WORKAROUND_REG 0x50 101 #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27) 102 103 static int 104 ehci_pci_match(device_t parent, cfdata_t match, void *aux) 105 { 106 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 107 108 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 109 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 110 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 111 return 1; 112 113 return 0; 114 } 115 116 static void 117 ehci_pci_attach(device_t parent, device_t self, void *aux) 118 { 119 struct ehci_pci_softc *sc = device_private(self); 120 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 121 pci_chipset_tag_t pc = pa->pa_pc; 122 pcitag_t tag = pa->pa_tag; 123 char intrbuf[PCI_INTRSTR_LEN]; 124 char const *intrstr; 125 struct usb_pci *up; 126 int ncomp, quirk; 127 pcireg_t csr; 128 129 sc->sc_init_state = EHCI_INIT_NONE; 130 sc->sc.sc_dev = self; 131 sc->sc.sc_bus.ub_hcpriv = sc; 132 133 pci_aprint_devinfo(pa, "USB controller"); 134 135 /* Check for quirks */ 136 quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 137 PCI_PRODUCT(pa->pa_id)); 138 139 /* Map I/O registers */ 140 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 141 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 142 sc->sc.sc_size = 0; 143 aprint_error_dev(self, "can't map memory space\n"); 144 return; 145 } 146 147 sc->sc_pc = pc; 148 sc->sc_tag = tag; 149 150 const uint32_t hccparams = EREAD4(&sc->sc, EHCI_HCCPARAMS); 151 152 if (EHCI_HCC_64BIT(hccparams)) { 153 aprint_verbose_dev(self, "64-bit DMA"); 154 if (pci_dma64_available(pa)) { 155 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat64; 156 aprint_verbose("\n"); 157 } else { 158 aprint_verbose(" - limited\n"); 159 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; 160 } 161 } else { 162 aprint_verbose_dev(self, "32-bit DMA\n"); 163 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; 164 } 165 166 /* Disable interrupts, so we don't get any spurious ones. */ 167 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 168 DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs)); 169 EOWRITE4(&sc->sc, EHCI_USBINTR, 0); 170 171 pcireg_t intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 172 int pin = PCI_INTERRUPT_PIN(intr); 173 174 /* Enable the device. */ 175 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 176 csr |= PCI_COMMAND_MASTER_ENABLE; 177 csr &= ~(pin ? PCI_COMMAND_INTERRUPT_DISABLE : 0); 178 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 179 180 /* Handle quirks */ 181 switch (quirk) { 182 case EHCI_PCI_QUIRK_AMD_SB600: 183 ehci_apply_amd_quirks(sc); 184 sc->sc.sc_flags |= EHCIF_SB600_ASYNCLIST_RELOAD; 185 break; 186 case EHCI_PCI_QUIRK_AMD_SB700: 187 if (pci_find_device(NULL, ehci_sb700_match)) 188 ehci_apply_amd_quirks(sc); 189 break; 190 } 191 192 /* Map and establish the interrupt. */ 193 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) != 0) { 194 aprint_error_dev(self, "couldn't map interrupt\n"); 195 goto fail; 196 } 197 198 /* 199 * Allocate IRQ 200 */ 201 intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, sizeof(intrbuf)); 202 pci_intr_setattr(pc, &sc->sc_pihp[0], PCI_INTR_MPSAFE, true); 203 sc->sc_ih = pci_intr_establish_xname(pc, sc->sc_pihp[0], IPL_USB, 204 ehci_intr, sc, device_xname(self)); 205 if (sc->sc_ih == NULL) { 206 aprint_error_dev(self, "couldn't establish interrupt"); 207 if (intrstr != NULL) 208 aprint_error(" at %s", intrstr); 209 aprint_error("\n"); 210 goto fail; 211 } 212 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 213 214 switch (pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 215 case PCI_USBREV_PRE_1_0: 216 case PCI_USBREV_1_0: 217 case PCI_USBREV_1_1: 218 sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; 219 aprint_verbose_dev(self, "pre-2.0 USB rev, device ignored\n"); 220 goto fail; 221 case PCI_USBREV_2_0: 222 sc->sc.sc_bus.ub_revision = USBREV_2_0; 223 break; 224 default: 225 sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; 226 break; 227 } 228 229 /* Enable workaround for dropped interrupts as required */ 230 switch (PCI_VENDOR(pa->pa_id)) { 231 case PCI_VENDOR_ATI: 232 case PCI_VENDOR_VIATECH: 233 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 234 aprint_normal_dev(self, "dropped intr workaround enabled\n"); 235 break; 236 default: 237 break; 238 } 239 240 /* 241 * Find companion controllers. According to the spec they always 242 * have lower function numbers so they should be enumerated already. 243 */ 244 const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS)); 245 KASSERT(maxncomp <= EHCI_COMPANION_MAX); 246 ncomp = 0; 247 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP ehci_pci_alldevs */ 248 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 249 if (up->bus == pa->pa_bus && up->device == pa->pa_device && 250 !up->claimed) { 251 DPRINTF(("ehci_pci_attach: companion %s\n", 252 device_xname(up->usb))); 253 sc->sc.sc_comps[ncomp++] = up->usb; 254 up->claimed = true; 255 if (ncomp == maxncomp) 256 break; 257 } 258 } 259 sc->sc.sc_ncomp = ncomp; 260 261 ehci_get_ownership(&sc->sc, pc, tag); 262 sc->sc_init_state = EHCI_INIT_OWNER; 263 264 int err = ehci_init(&sc->sc); 265 if (err) { 266 aprint_error_dev(self, "init failed, error=%d\n", err); 267 goto fail; 268 } 269 sc->sc_init_state = EHCI_INIT_INITED; 270 271 pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 272 ehci_shutdown); 273 274 /* Attach usb device. */ 275 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint, 276 CFARGS_NONE); 277 return; 278 279 fail: 280 ehci_pci_release_resources(sc); 281 pmf_device_register(self, NULL, NULL); 282 } 283 284 static void 285 ehci_pci_release_resources(struct ehci_pci_softc *sc) 286 { 287 if (sc->sc_init_state >= EHCI_INIT_OWNER) 288 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 289 290 if (sc->sc_ih) { 291 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 292 sc->sc_ih = NULL; 293 } 294 if (sc->sc_pihp != NULL) { 295 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 296 sc->sc_pihp = NULL; 297 } 298 299 if (sc->sc.sc_size) { 300 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 301 sc->sc.sc_size = 0; 302 } 303 304 sc->sc_init_state = EHCI_INIT_NONE; 305 } 306 307 static int 308 ehci_pci_detach(device_t self, int flags) 309 { 310 struct ehci_pci_softc *sc = device_private(self); 311 int rv; 312 313 if (sc->sc_init_state >= EHCI_INIT_INITED) { 314 rv = ehci_detach(&sc->sc, flags); 315 if (rv) 316 return rv; 317 } 318 319 pmf_device_deregister(self); 320 ehci_shutdown(self, flags); 321 322 if (sc->sc_init_state >= EHCI_INIT_INITED) { 323 /* disable interrupts */ 324 EOWRITE4(&sc->sc, EHCI_USBINTR, 0); 325 /* XXX grotty hack to flush the write */ 326 (void)EOREAD4(&sc->sc, EHCI_USBINTR); 327 } 328 329 ehci_pci_release_resources(sc); 330 331 #if 1 332 /* XXX created in ehci.c */ 333 if (sc->sc_init_state >= EHCI_INIT_INITED) { 334 mutex_destroy(&sc->sc.sc_rhlock); 335 mutex_destroy(&sc->sc.sc_lock); 336 mutex_destroy(&sc->sc.sc_intr_lock); 337 softint_disestablish(sc->sc.sc_doorbell_si); 338 softint_disestablish(sc->sc.sc_pcd_si); 339 } 340 #endif 341 342 return 0; 343 } 344 345 CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 346 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 347 ehci_childdet, DVF_DETACH_SHUTDOWN); 348 349 #ifdef EHCI_DEBUG 350 static void 351 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 352 { 353 uint32_t cparams, legctlsts, addr, cap, id; 354 int maxdump = 10; 355 356 cparams = EREAD4(sc, EHCI_HCCPARAMS); 357 addr = EHCI_HCC_EECP(cparams); 358 while (addr != 0) { 359 cap = pci_conf_read(pc, tag, addr); 360 id = EHCI_CAP_GET_ID(cap); 361 switch (id) { 362 case EHCI_CAP_ID_LEGACY: 363 legctlsts = pci_conf_read(pc, tag, 364 addr + PCI_EHCI_USBLEGCTLSTS); 365 printf("ehci_dump_caps: legsup=0x%08x " 366 "legctlsts=0x%08x\n", cap, legctlsts); 367 break; 368 default: 369 printf("ehci_dump_caps: cap=0x%08x\n", cap); 370 break; 371 } 372 if (--maxdump < 0) 373 break; 374 addr = EHCI_CAP_GET_NEXT(cap); 375 } 376 } 377 #endif 378 379 static void 380 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 381 { 382 const char *devname = device_xname(sc->sc_dev); 383 uint32_t cparams, addr, cap; 384 pcireg_t legsup; 385 int maxcap = 10; 386 387 cparams = EREAD4(sc, EHCI_HCCPARAMS); 388 addr = EHCI_HCC_EECP(cparams); 389 while (addr != 0) { 390 cap = pci_conf_read(pc, tag, addr); 391 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 392 goto next; 393 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 394 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 395 legsup & ~EHCI_LEG_HC_OS_OWNED); 396 397 next: 398 if (--maxcap < 0) { 399 aprint_normal("%s: broken extended capabilities " 400 "ignored\n", devname); 401 return; 402 } 403 addr = EHCI_CAP_GET_NEXT(cap); 404 } 405 } 406 407 static void 408 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 409 { 410 const char *devname = device_xname(sc->sc_dev); 411 uint32_t cparams, addr, cap; 412 pcireg_t legsup; 413 int maxcap = 10; 414 int ms; 415 416 #ifdef EHCI_DEBUG 417 if (ehcidebug) 418 ehci_dump_caps(sc, pc, tag); 419 #endif 420 cparams = EREAD4(sc, EHCI_HCCPARAMS); 421 addr = EHCI_HCC_EECP(cparams); 422 while (addr != 0) { 423 cap = pci_conf_read(pc, tag, addr); 424 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 425 goto next; 426 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 427 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 428 /* Ask BIOS to give up ownership */ 429 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 430 legsup | EHCI_LEG_HC_OS_OWNED); 431 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 432 legsup = pci_conf_read(pc, tag, 433 addr + PCI_EHCI_USBLEGSUP); 434 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 435 break; 436 delay(10000); 437 } 438 if (ms == EHCI_MAX_BIOS_WAIT) { 439 aprint_normal("%s: BIOS refuses to give up " 440 "ownership, using force\n", devname); 441 pci_conf_write(pc, tag, 442 addr + PCI_EHCI_USBLEGSUP, 0); 443 } else 444 aprint_verbose("%s: BIOS has given up " 445 "ownership\n", devname); 446 } 447 448 /* Disable SMIs */ 449 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0); 450 451 next: 452 if (--maxcap < 0) { 453 aprint_normal("%s: broken extended capabilities " 454 "ignored\n", devname); 455 return; 456 } 457 addr = EHCI_CAP_GET_NEXT(cap); 458 } 459 460 } 461 462 static bool 463 ehci_pci_suspend(device_t dv, const pmf_qual_t *qual) 464 { 465 struct ehci_pci_softc *sc = device_private(dv); 466 467 ehci_suspend(dv, qual); 468 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 469 470 return true; 471 } 472 473 static bool 474 ehci_pci_resume(device_t dv, const pmf_qual_t *qual) 475 { 476 struct ehci_pci_softc *sc = device_private(dv); 477 478 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 479 return ehci_resume(dv, qual); 480 } 481 482 static int 483 ehci_sb700_match(const struct pci_attach_args *pa) 484 { 485 if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 486 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB)) 487 return 0; 488 489 switch (PCI_REVISION(pa->pa_class)) { 490 case 0x3a: 491 case 0x3b: 492 return 1; 493 } 494 495 return 0; 496 } 497 498 static int 499 ehci_apply_amd_quirks(struct ehci_pci_softc *sc) 500 { 501 pcireg_t value; 502 503 aprint_normal_dev(sc->sc.sc_dev, 504 "applying AMD SB600/SB700 USB freeze workaround\n"); 505 value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG); 506 pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG, 507 value | EHCI_SBx00_WORKAROUND_ENABLE); 508 509 return 0; 510 } 511 512 static enum ehci_pci_quirk_flags 513 ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 514 { 515 int i; 516 517 for (i = 0; i < __arraycount(ehci_pci_quirks); i++) { 518 if (vendor == ehci_pci_quirks[i].vendor && 519 product == ehci_pci_quirks[i].product) 520 return ehci_pci_quirks[i].quirks; 521 } 522 return 0; 523 } 524 525
Indexes created Sun Oct 25 00:26:45 UTC 2026