| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu_mux.c | 53 if (mux->parents[index] != NULL &&
54 strcmp(mux->parents[index], name) == 0)
81 return mux->parents[index];
|
| sunxi_ccu_prediv.c | 110 if (prediv->parents[index] != NULL &&
111 strcmp(prediv->parents[index], name) == 0)
138 return prediv->parents[index];
|
| sunxi_ccu_div.c | 114 pname = div->parents[index];
197 if (div->parents[index] != NULL &&
198 strcmp(div->parents[index], name) == 0)
223 return div->parents[0];
228 return div->parents[index];
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru_arm.c | 85 main_parent = rk_cru_clock_find(sc, arm->parents[arm->mux_main]);
86 alt_parent = rk_cru_clock_find(sc, arm->parents[arm->mux_alt]);
88 device_printf(sc->sc_dev, "couldn't get clock parents\n");
92 error = rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_alt]);
113 rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_main]);
140 main_parent = rk_cru_clock_find(sc, arm->parents[arm->mux_main]);
141 alt_parent = rk_cru_clock_find(sc, arm->parents[arm->mux_alt]);
143 device_printf(sc->sc_dev, "couldn't get clock parents\n");
149 error = rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_alt]);
179 rk_cru_arm_set_parent(sc, clk, arm->parents[arm->mux_main])
[all...] |
| rk_cru_mux.c | 60 return mux->parents[index];
76 if (strcmp(mux->parents[index], parent) == 0) {
|
| rk_cru_composite.c | 171 rclk_parent = rk_cru_clock_find(sc, composite->parents[mux]);
175 clk_parent = fdtbus_clock_byname(composite->parents[mux]);
233 return composite->parents[mux];
248 if (strcmp(composite->parents[mux], parent) == 0) {
|
| rk_cru.h | 100 const char **parents; member in struct:rk_cru_pll
117 .u.pll.parents = (_parents), \
177 const char **parents; member in struct:rk_cru_arm
196 .u.arm.parents = (_parents), \
218 .u.arm.parents = (_parents), \
283 const char **parents; member in struct:rk_cru_composite
305 .u.composite.parents = (_parents), \
382 const char **parents; member in struct:rk_cru_mux
397 .u.mux.parents = (_parents), \
|
| /src/sys/arch/arm/nxp/ |
| imx_ccm_mux.c | 55 return mux->parents[sel];
68 if (strcmp(mux->parents[sel], parent) == 0) {
|
| imx_ccm_composite.c | 120 rclk_parent = imx_ccm_clock_find(sc, composite->parents[mux]);
124 clk_parent = fdtbus_clock_byname(composite->parents[mux]);
178 return composite->parents[mux];
191 if (strcmp(composite->parents[mux], parent) == 0) {
|
| /src/external/gpl3/gcc.old/dist/contrib/gcc-changelog/ |
| git_update_version.py | 94 assert len(commit.parents) <= 2
95 commit = commit.parents[-1]
105 assert len(head.parents) <= 2
106 if len(head.parents) == 2:
107 head = head.parents[1]
|
| /src/sys/arch/arm/amlogic/ |
| meson_clk_mux.c | 56 return mux->parents[sel];
|
| /src/sys/arch/arm/nvidia/ |
| tegra_clock.h | 57 const char **parents; member in struct:tegra_mux_clk
|
| /src/sys/arch/arm/samsung/ |
| exynos_clock.h | 54 const char **parents; member in struct:exynos_mux_clk
|
| /src/external/gpl3/binutils/dist/gprofng/src/ |
| symtab.h | 98 struct arc *parents; /* List of caller arcs. */ member in struct:sym::__anon10313
|
| gmon_cg_arcs.cc | 126 /* prepend this parent to the parents of this child: */
127 arc->next_parent = child->cg.parents;
128 child->cg.parents = arc;
|
| /src/external/gpl3/gcc/dist/contrib/gcc-changelog/ |
| git_update_version.py | 108 assert len(commit.parents) <= 2
109 commit = commit.parents[-1]
119 assert len(head.parents) <= 2
120 if len(head.parents) == 2:
121 head = head.parents[1]
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/ |
| k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 56 assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */
|
| /src/external/bsd/tre/dist/lib/ |
| regexec.c | 44 int *parents; local
86 parents = submatch_data[i].parents;
87 if (parents != NULL)
88 for (j = 0; parents[j] >= 0; j++)
90 DPRINT(("pmatch[%d] parent %d\n", i, parents[j]));
91 if (pmatch[i].rm_so < pmatch[parents[j]].rm_so
92 || pmatch[i].rm_eo > pmatch[parents[j]].rm_eo)
|
| /src/external/gpl3/gdb.old/dist/libctf/ |
| ctf-dedup.c | 60 and values, are only 32 bits wide). We track which inputs are parents of
62 traversed in children may cite types in parents, and so that we can process
63 the parents first.)
202 relationships, so we simply sort all types that first appear in parents
222 ctf_id_t's with parents in the process by simply chasing to the parent dict
488 ctf_dict_t **inputs, uint32_t *parents,
555 uint32_t *parents, int input_num, ctf_id_t type,
714 if ((hval = ctf_dedup_hash_type (fp, input, inputs, parents, input_num,
743 if ((hval = ctf_dedup_hash_type (fp, input, inputs, parents, input_num,
776 if ((hval = ctf_dedup_hash_type (fp, input, inputs, parents, input_num
[all...] |
| /src/external/bsd/zstd/dist/build/meson/ |
| InstallSymlink.py | 18 install_dir.mkdir(mode=dir_mode, parents=True, exist_ok=True)
|
| /src/external/gpl3/binutils/dist/gprof/ |
| symtab.h | 96 struct arc *parents; /* List of caller arcs. */ member in struct:sym::__anon10173
|
| /src/external/gpl3/binutils.old/dist/gprof/ |
| symtab.h | 96 struct arc *parents; /* List of caller arcs. */ member in struct:sym::__anon11646
|
| /src/external/gpl3/gcc/dist/gcc/ |
| vtable-verify.h | 86 vec<struct vtv_graph_node *> parents; /* Vector of parents in the graph. */ member in struct:vtv_graph_node
|
| /src/external/gpl3/gcc.old/dist/gcc/ |
| vtable-verify.h | 86 vec<struct vtv_graph_node *> parents; /* Vector of parents in the graph. */ member in struct:vtv_graph_node
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/ |
| imx7d-cl-som-imx7.dts | 49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
|
