| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64MacroFusion.cpp | 1 //===- AArch64MacroFusion.cpp - AArch64 Macro Fusion ----------------------===//
9 /// \file This file contains the AArch64 implementation of the DAG scheduling
24 if (SecondMI.getOpcode() != AArch64::Bcc)
33 if (CmpOnly && !(FirstMI->getOperand(0).getReg() == AArch64::XZR ||
34 FirstMI->getOperand(0).getReg() == AArch64::WZR)) {
39 case AArch64::ADDSWri:
40 case AArch64::ADDSWrr:
41 case AArch64::ADDSXri:
42 case AArch64::ADDSXrr:
43 case AArch64::ANDSWri
[all...] |
| AArch64FalkorHWPFFix.cpp | 15 #include "AArch64.h"
57 #define DEBUG_TYPE "aarch64-falkor-hwpf-fix"
227 INITIALIZE_PASS_BEGIN(FalkorHWPFFix, "aarch64-falkor-hwpf-fix-late",
230 INITIALIZE_PASS_END(FalkorHWPFFix, "aarch64-falkor-hwpf-fix-late",
247 case AArch64::LD1i64:
248 case AArch64::LD2i64:
255 case AArch64::LD1i8:
256 case AArch64::LD1i16:
257 case AArch64::LD1i32:
258 case AArch64::LD2i8
[all...] |
| AArch64DeadRegisterDefinitionsPass.cpp | 13 #include "AArch64.h"
28 #define DEBUG_TYPE "aarch64-dead-defs"
32 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
61 INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
79 case AArch64::LDADDB: case AArch64::LDADDH:
80 case AArch64::LDADDW: case AArch64::LDADDX:
81 case AArch64::LDADDLB: case AArch64::LDADDLH
[all...] |
| AArch64CondBrTuning.cpp | 1 //===-- AArch64CondBrTuning.cpp --- Conditional branch tuning for AArch64 -===//
28 #include "AArch64.h"
43 #define DEBUG_TYPE "aarch64-cond-br-tuning"
44 #define AARCH64_CONDBR_TUNING_NAME "AArch64 Conditional Branch Tuning"
72 INITIALIZE_PASS(AArch64CondBrTuning, "aarch64-cond-br-tuning",
94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
103 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
120 case AArch64::CBZW:
121 case AArch64::CBZX
[all...] |
| AArch64PBQPRegAlloc.cpp | 1 //===-- AArch64PBQPRegAlloc.cpp - AArch64 specific PBQP constraints -------===//
8 // This file contains the AArch64 / Cortex-A57 specific register allocation
17 #define DEBUG_TYPE "aarch64-pbqp"
20 #include "AArch64.h"
37 return AArch64::FPR32RegClass.contains(reg) ||
38 AArch64::FPR64RegClass.contains(reg) ||
39 AArch64::FPR128RegClass.contains(reg);
47 case AArch64::S1:
48 case AArch64::S3:
49 case AArch64::S5
[all...] |
| AArch64SIMDInstrOpt.cpp | 56 #define DEBUG_TYPE "aarch64-simdinstr-opt"
62 "AArch64 SIMD instructions optimization pass"
103 RuleST2(AArch64::ST2Twov2d, AArch64::ZIP1v2i64, AArch64::ZIP2v2i64,
104 AArch64::STPQi, AArch64::FPR128RegClass),
105 RuleST2(AArch64::ST2Twov4s, AArch64::ZIP1v4i32, AArch64::ZIP2v4i32
[all...] |
| AArch64CallingConvention.cpp | 1 //=== AArch64CallingConvention.cpp - AArch64 CC impl ------------*- C++ -*-===//
9 // This file contains the table-generated and custom routines for the AArch64
15 #include "AArch64.h"
23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
24 AArch64::X3, AArch64::X4, AArch64::X5,
25 AArch64::X6, AArch64::X7}
[all...] |
| AArch64InstrInfo.cpp | 1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
9 // This file contains the AArch64 implementation of the TargetInstrInfo class.
59 "aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
63 "aarch64-cbz-offset-bits", cl::Hidden, cl::init(19),
67 BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
71 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP,
72 AArch64::CATCHRET),
84 if (Op == AArch64::INLINEASM || Op == AArch64::INLINEASM_BR
[all...] |
| AArch64SLSHardening.cpp | 37 #define DEBUG_TYPE "aarch64-sls-hardening"
39 #define AARCH64_SLS_HARDENING_NAME "AArch64 sls hardening pass"
70 INITIALIZE_PASS(AArch64SLSHardening, "aarch64-sls-hardening",
87 ? AArch64::SpeculationBarrierSBEndBB
88 : AArch64::SpeculationBarrierISBDSBEndBB;
90 (MBBI->getOpcode() != AArch64::SpeculationBarrierSBEndBB &&
91 MBBI->getOpcode() != AArch64::SpeculationBarrierISBDSBEndBB))
111 case AArch64::BLR:
112 case AArch64::BLRNoIP:
114 case AArch64::BLRAA
[all...] |
| AArch64LoadStoreOptimizer.cpp | 1 //===- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -------===//
49 #define DEBUG_TYPE "aarch64-ldst-opt"
63 static cl::opt<unsigned> LdStLimit("aarch64-load-store-scan-limit",
68 static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
72 static cl::opt<bool> EnableRenaming("aarch64-load-store-renaming",
75 #define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
211 INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
218 case AArch64::STRBBui:
219 case AArch64::STURBBi:
220 case AArch64::STRHHui
[all...] |
| AArch64ExpandPseudoInsts.cpp | 47 #define AARCH64_EXPAND_PSEUDO_NAME "AArch64 pseudo instruction expansion pass"
97 INITIALIZE_PASS(AArch64ExpandPseudo, "aarch64-expand-pseudo",
127 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
145 case AArch64::ORRWri:
146 case AArch64::ORRXri:
149 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
152 case AArch64::MOVNWi:
153 case AArch64::MOVNXi
[all...] |
| AArch64StackTaggingPreRA.cpp | 1 //===-- AArch64StackTaggingPreRA.cpp --- Stack Tagging for AArch64 -----===//
11 #include "AArch64.h"
35 #define DEBUG_TYPE "aarch64-stack-tagging-pre-ra"
83 return "AArch64 Stack Tagging PreRA";
95 INITIALIZE_PASS_BEGIN(AArch64StackTaggingPreRA, "aarch64-stack-tagging-pre-ra",
96 "AArch64 Stack Tagging PreRA Pass", false, false)
97 INITIALIZE_PASS_END(AArch64StackTaggingPreRA, "aarch64-stack-tagging-pre-ra",
98 "AArch64 Stack Tagging PreRA Pass", false, false)
106 case AArch64::LDRBBui:
107 case AArch64::LDRHHui
[all...] |
| AArch64RedundantCopyElimination.cpp | 1 //=- AArch64RedundantCopyElimination.cpp - Remove useless copy for AArch64 -=//
52 #include "AArch64.h"
64 #define DEBUG_TYPE "aarch64-copyelim"
103 return "AArch64 Redundant Copy Elimination";
109 INITIALIZE_PASS(AArch64RedundantCopyElimination, "aarch64-copyelim",
110 "AArch64 redundant copy elimination pass", false, false)
131 if (((Opc == AArch64::CBZW || Opc == AArch64::CBZX) &&
133 ((Opc == AArch64::CBNZW || Opc == AArch64::CBNZX) &
[all...] |
| AArch64CollectLOH.cpp | 1 //===---------- AArch64CollectLOH.cpp - AArch64 collect LOH pass --*- C++ -*-=//
100 #include "AArch64.h"
119 #define DEBUG_TYPE "aarch64-collect-loh"
130 #define AARCH64_COLLECT_LOH_NAME "AArch64 Collect Linker Optimization Hint (LOH)"
157 INITIALIZE_PASS(AArch64CollectLOH, "aarch64-collect-loh",
180 case AArch64::ADRP:
182 case AArch64::ADDXri:
184 case AArch64::LDRXui:
185 case AArch64::LDRWui:
202 case AArch64::STRBBui
[all...] |
| AArch64ConditionalCompares.cpp | 1 //===-- AArch64ConditionalCompares.cpp --- CCMP formation for AArch64 -----===//
19 #include "AArch64.h"
43 #define DEBUG_TYPE "aarch64-ccmp"
48 "aarch64-ccmp-limit", cl::init(30), cl::Hidden,
52 static cl::opt<bool> Stress("aarch64-stress-ccmp", cl::Hidden,
99 // instructions. The AArch64 conditional compare instructions have an immediate
261 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
286 case AArch64::CBZW:
287 case AArch64::CBZX
[all...] |
| AArch64AsmPrinter.cpp | 1 //===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
10 // of machine-dependent LLVM code to the AArch64 assembly language.
14 #include "AArch64.h"
82 StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
307 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));
310 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
319 MI.getOpcode() == AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES;
328 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" +
336 MCInstBuilder(AArch64::BL)
387 OutStreamer->emitInstruction(MCInstBuilder(AArch64::SBFMXri
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
10 // the AArch64 target useful for the compiler back-end and the MC libraries.
21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
31 case AArch64::X0: return AArch64::W0;
32 case AArch64::X1: return AArch64::W1;
33 case AArch64::X2: return AArch64::W2;
34 case AArch64::X3: return AArch64::W3
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
33 #define DEBUG_TYPE "aarch64-disassembler"
320 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
321 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64InstPrinter.cpp | 1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
9 // This class prints an AArch64 MCInst to a .s file.
66 if (Opcode == AArch64::SYSxt)
73 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
74 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
80 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
81 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri)
[all...] |
| AArch64MCTargetDesc.cpp | 1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
9 // This file provides AArch64 specific target descriptions.
69 {codeview::RegisterId::ARM64_W0, AArch64::W0},
70 {codeview::RegisterId::ARM64_W1, AArch64::W1},
71 {codeview::RegisterId::ARM64_W2, AArch64::W2},
72 {codeview::RegisterId::ARM64_W3, AArch64::W3},
73 {codeview::RegisterId::ARM64_W4, AArch64::W4},
74 {codeview::RegisterId::ARM64_W5, AArch64::W5},
75 {codeview::RegisterId::ARM64_W6, AArch64::W6},
76 {codeview::RegisterId::ARM64_W7, AArch64::W7}
[all...] |
| AArch64WinCOFFObjectWriter.cpp | 1 //= AArch64WinCOFFObjectWriter.cpp - AArch64 Windows COFF Object Writer C++ =//
113 case AArch64::fixup_aarch64_add_imm12:
123 case AArch64::fixup_aarch64_ldst_imm12_scale1:
124 case AArch64::fixup_aarch64_ldst_imm12_scale2:
125 case AArch64::fixup_aarch64_ldst_imm12_scale4:
126 case AArch64::fixup_aarch64_ldst_imm12_scale8:
127 case AArch64::fixup_aarch64_ldst_imm12_scale16:
135 case AArch64::fixup_aarch64_pcrel_adr_imm21:
138 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
141 case AArch64::fixup_aarch64_pcrel_branch14
[all...] |
| AArch64AsmBackend.cpp | 1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
46 return AArch64::NumTargetFixupKinds;
52 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
118 case AArch64::fixup_aarch64_movw:
119 case AArch64::fixup_aarch64_pcrel_branch14:
120 case AArch64::fixup_aarch64_add_imm12:
121 case AArch64::fixup_aarch64_ldst_imm12_scale1:
122 case AArch64::fixup_aarch64_ldst_imm12_scale2:
123 case AArch64::fixup_aarch64_ldst_imm12_scale4:
124 case AArch64::fixup_aarch64_ldst_imm12_scale8
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Support/ |
| AArch64TargetParser.cpp | 1 //===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
9 // This file implements a target parser to recognise AArch64 hardware features
27 unsigned AArch64::getDefaultFPU(StringRef CPU, AArch64::ArchKind AK) {
38 uint64_t AArch64::getDefaultExtensions(StringRef CPU, AArch64::ArchKind AK) {
48 .Default(AArch64::AEK_INVALID);
51 AArch64::ArchKind AArch64::getCPUArchKind(StringRef CPU) {
55 return StringSwitch<AArch64::ArchKind>(CPU
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64PostSelectOptimize.cpp | 14 #include "AArch64.h"
24 #define DEBUG_TYPE "aarch64-post-select-optimize"
36 return "AArch64 Post Select Optimizer";
64 case AArch64::SUBSXrr:
65 return AArch64::SUBXrr;
66 case AArch64::SUBSWrr:
67 return AArch64::SUBWrr;
68 case AArch64::SUBSXrs:
69 return AArch64::SUBXrs;
70 case AArch64::SUBSXri
[all...] |
| /src/external/apache2/llvm/lib/libLLVMAArch64AsmParser/ |
| Makefile | 8 CPPFLAGS+= -I${AARCH64_OBJDIR} -I${LLVM_SRCDIR}/lib/Target/AArch64
10 .PATH: ${LLVM_SRCDIR}/lib/Target/AArch64/AsmParser
|
