| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMFeatures.h | 1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
9 // This file contains the code shared between ARM CodeGen and ARM MC
28 case ARM::tADC:
29 case ARM::tADDi3:
30 case ARM::tADDi8:
31 case ARM::tADDrr:
32 case ARM::tAND:
33 case ARM::tASRri:
34 case ARM::tASRrr
[all...] |
| ARMInstrInfo.cpp | 1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
9 // This file contains the ARM implementation of the TargetInstrInfo class.
14 #include "ARM.h"
38 NopInst.setOpcode(ARM::HINT);
43 NopInst.setOpcode(ARM::MOVr);
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
45 NopInst.addOperand(MCOperand::createReg(ARM::R0));
57 case ARM::LDR_PRE_IMM:
58 case ARM::LDR_PRE_REG:
59 case ARM::LDR_POST_IMM
[all...] |
| ARMExpandPseudoInsts.cpp | 16 #include "ARM.h"
30 #define DEBUG_TYPE "arm-pseudo"
33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34 cl::desc("Verify machine code after expanding ARM pseudos"));
36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
185 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
186 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
187 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}
[all...] |
| Thumb2SizeReduction.cpp | 9 #include "ARM.h"
83 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
84 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
85 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
86 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 }
[all...] |
| ARMRegisterBankInfo.cpp | 9 /// This file implements the targeting of the RegisterBankInfo class for ARM.
30 namespace ARM {
129 } // end namespace arm
137 // (ARM::RegBanks) is unique in the compiler. At some point, it
142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
144 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
147 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
149 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
151 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
153 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &
[all...] |
| ARMBaseInstrInfo.cpp | 1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
72 #define DEBUG_TYPE "arm-instrinfo"
78 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
79 cl::desc("Enable ARM 2-addr to 3-addr conv"));
93 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
94 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false }
[all...] |
| Thumb2InstrInfo.cpp | 53 return MCInstBuilder(ARM::tHINT).addImm(0).addImm(ARMCC::AL).addReg(0);
92 if (MBBI->getOpcode() == ARM::t2IT) {
140 get(ARM::t2CSEL), DestReg)
155 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
158 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
177 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
178 BuildMI(MBB, I, DL, get(ARM::t2STRi12))
187 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
193 MRI->constrainRegClass(SrcReg, &ARM::GPRPairnospRegClass);
196 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8))
[all...] |
| ARMTargetTransformInfo.h | 1 //===- ARMTargetTransformInfo.h - ARM specific TTI --------------*- C++ -*-===//
11 /// ARM target machine. It uses the target's detailed information to
20 #include "ARM.h"
70 // fail if the callee uses ARM only instructions, e.g. in inline asm.
72 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
73 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8
[all...] |
| ARMBaseInstrInfo.h | 1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
9 // This file contains the Base ARM implementation of the TargetInstrInfo class.
111 /// enhance debug entry value descriptions for ARM targets.
348 /// ARM supports the MachineOutliner.
368 return MI->getOpcode() == ARM::t2LoopEndDec ||
369 MI->getOpcode() == ARM::t2DoLoopStartTP ||
370 MI->getOpcode() == ARM::t2WhileLoopStartLR;
556 return MachineOperand::CreateReg(ARM::CPSR,
563 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B
[all...] |
| MVETailPredUtils.h | 30 case ARM::MVE_VCTP8:
31 return IsDoLoop ? ARM::MVE_DLSTP_8 : ARM::MVE_WLSTP_8;
32 case ARM::MVE_VCTP16:
33 return IsDoLoop ? ARM::MVE_DLSTP_16 : ARM::MVE_WLSTP_16;
34 case ARM::MVE_VCTP32:
35 return IsDoLoop ? ARM::MVE_DLSTP_32 : ARM::MVE_WLSTP_32;
36 case ARM::MVE_VCTP64
[all...] |
| ARMMacroFusion.cpp | 1 //===- ARMMacroFusion.cpp - ARM Macro Fusion ----------------------===//
9 /// \file This file contains the ARM implementation of the DAG scheduling
27 case ARM::AESMC :
28 return FirstMI == nullptr || FirstMI->getOpcode() == ARM::AESE;
30 case ARM::AESIMC:
31 return FirstMI == nullptr || FirstMI->getOpcode() == ARM::AESD;
41 if ((FirstMI == nullptr || FirstMI->getOpcode() == ARM::MOVi16) &&
42 SecondMI.getOpcode() == ARM::MOVTi16)
|
| Thumb1FrameLowering.cpp | 57 // stack frame. ARM (especially Thumb) has small immediate offset to
79 if (ScratchReg == ARM::NoRegister)
84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg)
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP)
91 .addReg(ARM::SP)
99 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
109 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII
[all...] |
| /src/sys/arch/hpc/stand/include/machine/ |
| coff_machdep.h | 8 #ifdef ARM
|
| elf_machdep.h | 12 #ifdef ARM
13 #include "../../../../arm/include/elf_machdep.h"
|
| int_const.h | 3 #if defined ARM
4 #include "../../../../arm/include/int_const.h"
|
| int_fmtio.h | 3 #if defined ARM
4 #include "../../../../arm/include/int_fmtio.h"
|
| int_limits.h | 3 #if defined ARM
4 #include "../../../../arm/include/int_limits.h"
|
| int_mwgwtypes.h | 3 #if defined ARM
4 #include "../../../../arm/include/int_mwgwtypes.h"
|
| int_types.h | 3 #if defined ARM
4 #include "../../../../arm/include/int_types.h"
|
| platid.h | 9 #ifdef ARM
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMTargetStreamer.cpp | 110 void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {}
112 void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {}
123 if (STI.hasFeature(ARM::HasV8Ops)) {
124 if (STI.hasFeature(ARM::FeatureRClass))
127 } else if (STI.hasFeature(ARM::HasV8_1MMainlineOps))
129 else if (STI.hasFeature(ARM::HasV8MMainlineOps))
131 else if (STI.hasFeature(ARM::HasV7Ops)) {
132 if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP))
135 } else if (STI.hasFeature(ARM::HasV6T2Ops)
[all...] |
| ARMMCTargetDesc.cpp | 1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
9 // This file provides ARM specific target descriptions.
41 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
68 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
80 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
92 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
104 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
110 if (MI.getOperand(OI).getReg() == ARM::PC) {
120 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
130 case ARM::LR
[all...] |
| ARMAsmBackend.cpp | 1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
56 #include "llvm/BinaryFormat/ELFRelocs/ARM.def"
71 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
125 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
209 bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2];
210 bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps];
215 case ARM::tBcc:
216 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
217 case ARM::tLDRpci:
218 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op
[all...] |
| /src/sys/arch/cats/conf/ |
| Makefile.cats.inc | 3 MACHINE_ARCH?= arm
22 ${ARM}/conf/kern.ldscript.head \
23 ${ARM}/conf/kern.ldscript.tail \
26 ( cat ${ARM}/conf/kern.ldscript.head ; \
29 cat ${ARM}/conf/kern.ldscript.tail ) > $@
|
| /src/sys/arch/shark/conf/ |
| Makefile.shark.inc | 16 ${ARM}/conf/kern.ldscript.head \
17 ${ARM}/conf/kern.ldscript.tail \
20 ( cat ${ARM}/conf/kern.ldscript.head ; \
23 cat ${ARM}/conf/kern.ldscript.tail ) > ldscript
|
