| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/MCTargetDesc/ |
| AVRELFStreamer.cpp | 16 if (Features[AVR::ELFArchAVR1])
18 else if (Features[AVR::ELFArchAVR2])
20 else if (Features[AVR::ELFArchAVR25])
22 else if (Features[AVR::ELFArchAVR3])
24 else if (Features[AVR::ELFArchAVR31])
26 else if (Features[AVR::ELFArchAVR35])
28 else if (Features[AVR::ELFArchAVR4])
30 else if (Features[AVR::ELFArchAVR5])
32 else if (Features[AVR::ELFArchAVR51])
34 else if (Features[AVR::ELFArchAVR6]
[all...] |
| AVRELFObjectWriter.cpp | 1 //===-- AVRELFObjectWriter.cpp - AVR ELF Writer ---------------------------===//
23 /// Writes AVR machine code into an ELF32 object file.
81 case AVR::fixup_32:
83 case AVR::fixup_7_pcrel:
85 case AVR::fixup_13_pcrel:
87 case AVR::fixup_16:
89 case AVR::fixup_16_pm:
91 case AVR::fixup_lo8_ldi:
93 case AVR::fixup_hi8_ldi:
95 case AVR::fixup_hh8_ldi
[all...] |
| AVRInstPrinter.cpp | 1 //===-- AVRInstPrinter.cpp - Convert AVR MCInst to assembly syntax --------===//
9 // This class prints an AVR MCInst to a .s file.
44 case AVR::LDRdPtr:
45 case AVR::LDRdPtrPi:
46 case AVR::LDRdPtrPd:
51 if (Opcode == AVR::LDRdPtrPd)
56 if (Opcode == AVR::LDRdPtrPi)
59 case AVR::STPtrRr:
65 case AVR::STPtrPiRr:
66 case AVR::STPtrPdRr
[all...] |
| AVRAsmBackend.cpp | 1 //===-- AVRAsmBackend.cpp - AVR Asm Backend ------------------------------===//
84 AVR::fixups::adjustBranchTarget(Value);
95 AVR::fixups::adjustBranchTarget(Value);
253 case AVR::fixup_7_pcrel:
256 case AVR::fixup_13_pcrel:
259 case AVR::fixup_call:
262 case AVR::fixup_ldi:
265 case AVR::fixup_lo8_ldi:
268 case AVR::fixup_lo8_ldi_pm:
269 case AVR::fixup_lo8_ldi_gs
[all...] |
| AVRMCExpr.cpp | 1 //===-- AVRMCExpr.cpp - AVR specific MC expression classes ----------------===//
149 AVR::Fixups AVRMCExpr::getFixupKind() const {
150 AVR::Fixups Kind = AVR::Fixups::LastTargetFixupKind;
154 Kind = isNegated() ? AVR::fixup_lo8_ldi_neg : AVR::fixup_lo8_ldi;
157 Kind = isNegated() ? AVR::fixup_hi8_ldi_neg : AVR::fixup_hi8_ldi;
160 Kind = isNegated() ? AVR::fixup_hh8_ldi_neg : AVR::fixup_hh8_ldi
[all...] |
| AVRMCCodeEmitter.cpp | 1 //===-- AVRMCCodeEmitter.cpp - Convert AVR Code to Machine Code -----------===//
77 bool IsRegX = MI.getOperand(0).getReg() == AVR::R27R26 ||
78 MI.getOperand(1).getReg() == AVR::R27R26;
80 bool IsPredec = Opcode == AVR::LDRdPtrPd || Opcode == AVR::STPtrPdRr;
81 bool IsPostinc = Opcode == AVR::LDRdPtrPi || Opcode == AVR::STPtrPiRr;
91 template <AVR::Fixups Fixup>
109 AVR::fixups::adjustBranchTarget(target);
122 case AVR::R27R26: return 0x03; // X: 0b1
[all...] |
| AVRFixupKinds.h | 1 //===-- AVRFixupKinds.h - AVR Specific Fixup Entries ------------*- C++ -*-===//
15 namespace AVR {
24 /// MCFixupKindInfo Infos[AVR::NumTargetFixupKinds]
27 /// A 32-bit AVR fixup.
37 /// The nonmenclature is that AVR branch targets are
136 /// All branch targets in AVR are rightshifted by 1 to take advantage
145 } // end of namespace llvm::AVR
|
| AVRMCCodeEmitter.h | 1 //===-- AVRMCCodeEmitter.h - Convert AVR Code to Machine Code -------------===//
36 /// Writes AVR machine code to a stream.
50 template <AVR::Fixups Fixup>
72 template <AVR::Fixups Fixup, unsigned Offset>
|
| AVRAsmBackend.h | 1 //===-- AVRAsmBackend.h - AVR Asm Backend --------------------------------===//
9 // \file The AVR assembly backend implementation.
28 /// Utilities for manipulating generated AVR machine code.
48 return AVR::NumTargetFixupKinds;
|
| AVRInstPrinter.h | 1 //===- AVRInstPrinter.h - Convert AVR MCInst to assembly syntax -*- C++ -*-===//
9 // This class prints an AVR MCInst to a .s file.
22 /// Prints AVR instructions to a textual stream.
37 unsigned AltIdx = AVR::NoRegAltName);
|
| AVRMCExpr.h | 1 //===-- AVRMCExpr.h - AVR specific MC expression classes --------*- C++ -*-===//
18 /// A expression in AVR machine code.
41 /// Creates an AVR machine code expression.
51 AVR::Fixups getFixupKind() const;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.cpp | 1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
9 // This file contains the AVR implementation of the TargetRegisterInfo class.
23 #include "AVR.h"
60 Reserved.set(AVR::R0);
61 Reserved.set(AVR::R1);
62 Reserved.set(AVR::R1R0);
65 Reserved.set(AVR::SPL);
66 Reserved.set(AVR::SPH);
67 Reserved.set(AVR::SP);
78 Reserved.set(AVR::R28)
[all...] |
| AVRFrameLowering.cpp | 1 //===-- AVRFrameLowering.cpp - AVR Frame Information ----------------------===//
9 // This file contains the AVR implementation of TargetFrameLowering class.
15 #include "AVR.h"
63 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
72 .addReg(AVR::R1R0, RegState::Kill)
75 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
78 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
79 .addReg(AVR::R0, RegState::Kill
[all...] |
| AVRInstrInfo.cpp | 1 //===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===//
9 // This file contains the AVR implementation of the TargetInstrInfo class.
27 #include "AVR.h"
39 : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
49 // Not all AVR devices support the 16-bit `MOVW` instruction.
50 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
51 if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) {
52 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
61 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo
[all...] |
| AVRExpandPseudoInsts.cpp | 15 #include "AVR.h"
28 #define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
33 /// actual AVR instructions.
54 const Register SCRATCH_REGISTER = AVR::R0;
56 const Register ZERO_REGISTER = AVR::R1;
211 if (Op == AVR::ANDIRdK && ImmVal == 0xff)
215 if (Op == AVR::ORIRdK && ImmVal == 0x0)
259 bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
260 return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI)
[all...] |
| AVRISelLowering.cpp | 1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
9 // This file defines the interfaces that AVR uses to lower LLVM code into a
27 #include "AVR.h"
39 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
48 setStackPointerRegisterToSaveRestore(AVR::SP);
162 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
267 assert(!VT.isVector() && "No AVR SetCC type for vectors!");
494 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
544 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code fo
[all...] |
| AVRRelaxMemOperations.cpp | 14 #include "AVR.h"
26 #define AVR_RELAX_MEM_OPS_NAME "AVR memory operation relaxation pass"
88 bool AVRRelaxMem::relax<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
99 buildMI(MBB, MBBI, AVR::PUSHWRr)
103 buildMI(MBB, MBBI, AVR::SBCIWRdK)
110 buildMI(MBB, MBBI, AVR::STWPtrRr)
115 buildMI(MBB, MBBI, AVR::POPWRd)
133 RELAX(AVR::STDWPtrQRr);
141 INITIALIZE_PASS(AVRRelaxMem, "avr-relax-mem",
|
| AVRTargetObjectFile.cpp | 1 //===-- AVRTargetObjectFile.cpp - AVR Object Files ------------------------===//
18 #include "AVR.h"
33 if (AVR::isProgramMemoryAddress(GO) && !GO->hasSection() && Kind.isReadOnly())
|
| AVRISelDAGToDAG.cpp | 1 //===-- AVRISelDAGToDAG.cpp - A dag to dag inst selector for AVR ----------===//
9 // This file defines an instruction selector for the AVR target.
13 #include "AVR.h"
22 #define DEBUG_TYPE "avr-isel"
26 /// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form).
33 return "AVR DAG->DAG Instruction Selection";
144 Opcode = (isPre) ? AVR::LDRdPtrPd : AVR::LDRdPtrPi;
152 Opcode = (isPre) ? AVR::LDWRdPtrPd : AVR::LDWRdPtrPi
[all...] |
| AVRAsmPrinter.cpp | 1 //===-- AVRAsmPrinter.cpp - AVR LLVM assembly writer ----------------------===//
10 // of machine-dependent LLVM code to GAS-format AVR assembly language.
14 #include "AVR.h"
34 #define DEBUG_TYPE "avr-asm-printer"
38 /// An AVR assembly code printer.
45 StringRef getPassName() const override { return "AVR Assembly Printer"; }
124 Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi
125 : AVR::sub_lo);
154 if (MI->getOperand(OpNum).getReg() == AVR::R31R30) {
157 assert(MI->getOperand(OpNum).getReg() == AVR::R29R28 &
[all...] |
| AVR.h | 1 //===-- AVR.h - Top-level interface for AVR representation ------*- C++ -*-===//
10 // AVR back-end.
36 /// Contains the AVR backend.
37 namespace AVR {
39 /// An integer that identifies all of the supported AVR address spaces.
53 } // end of namespace AVR
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/Disassembler/ |
| AVRDisassembler.cpp | 1 //===- AVRDisassembler.cpp - Disassembler for AVR ---------------*- C++ -*-===//
9 // This file is part of the AVR Disassembler.
13 #include "AVR.h"
28 #define DEBUG_TYPE "avr-disassembler"
34 /// A disassembler class for AVR.
61 AVR::R0, AVR::R1, AVR::R2, AVR::R3,
62 AVR::R4, AVR::R5, AVR::R6, AVR::R7
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/Driver/ToolChains/ |
| AVR.h | 1 //===--- AVR.h - AVR Tool and ToolChain Implementations ---------*- C++ -*-===//
42 namespace AVR {
46 : Tool("AVR::Linker", "avr-ld", TC), Triple(Triple),
60 } // end namespace AVR
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/AsmParser/ |
| AVRAsmParser.cpp | 1 //===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
9 #include "AVR.h"
34 #define DEBUG_TYPE "avr-asm-parser"
39 /// Parses AVR assembly from a stream.
77 unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
78 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
103 /// An parsed AVR assembly operand.
340 // GCC supports case insensitive register names. Some of the AVR registers
344 if (RegNum == AVR::NoRegister) {
347 if (RegNum == AVR::NoRegister)
[all...] |
| /src/external/apache2/llvm/lib/libclangBasic/ |
| Makefile | 53 AVR.cpp \
|
