| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86MachineFunctionInfo.cpp | 23 for (const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
24 unsigned Reg = *CSR; ++CSR) {
|
| /src/sys/arch/sh3/dev/ |
| adc.c | 75 ADC_(CSR) = 0;
124 uint8_t csr; local
141 csr = ADC_(CSR);
142 if ((csr & SH7709_ADCSR_ADST) != 0) {
144 snprintb(bits, sizeof(bits), SH7709_ADCSR_BITS, csr);
145 printf("adc_sample_channel(%d): CSR=%s", chan, bits);
155 ADC_(CSR) = chan | SH7709_ADCSR_ADST | SH7709_ADCSR_CKS;
158 csr = ADC_(CSR);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonGenExtract.cpp | 100 ConstantInt *CSL = nullptr, *CSR = nullptr, *CM = nullptr;
107 bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
114 Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
121 CSR = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
131 Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
138 Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
145 Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
152 Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
165 uint32_t SR = CSR->getZExtValue();
|
| HexagonVLIWPacketizer.cpp | 353 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
354 if (MI.modifiesRegister(*CSR, TRI))
|
| HexagonFrameLowering.cpp | 121 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
282 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
312 if (CSR[*S])
322 for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) {
324 // If this regmask does not preserve a CSR, a frame will be needed.
438 BitVector CSR(Hexagon::NUM_TARGET_REGS);
441 CSR[*S] = true;
444 if (needsStackFrame(I, CSR, HRI))
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LiveRegUnits.cpp | 85 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) {
86 const unsigned N = *CSR;
|
| RegisterClassInfo.cpp | 58 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
59 if (Update || CSR != CalleeSavedRegs) {
60 // Build a CSRAlias map. Every CSR alias saves the last
61 // overlapping CSR.
63 for (const MCPhysReg *I = CSR; *I; ++I)
69 CalleeSavedRegs = CSR;
90 /// registers filtered out. Volatile registers come first followed by CSR
91 /// aliases ordered according to the CSR order specified by the target.
122 // PhysReg aliases a CSR, save it for later.
134 // CSR aliases go after the volatile registers, preserve the target's order
[all...] |
| MachineFrameInfo.cpp | 125 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR;
126 ++CSR)
127 BV.set(*CSR);
|
| LivePhysRegs.cpp | 175 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR)
176 LiveRegs.addReg(*CSR);
|
| MachineRegisterInfo.cpp | 604 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
605 for (const MCPhysReg *I = CSR; *I; ++I)
|
| RegAllocPBQP.cpp | 583 const MCPhysReg *CSR = MF.getRegInfo().getCalleeSavedRegs();
584 for (unsigned i = 0; CSR[i] != 0; ++i)
585 if (TRI.regsOverlap(Reg, CSR[i]))
|
| /src/external/gpl3/gdb/dist/gdb/ |
| mep-tdep.c | 629 #define IS_CSR_REGNUM(n) (IN_SET (CSR, (n)))
653 The following table describes the special properties of each CSR. */
656 /* The number of this CSR's raw register. */
659 /* The number of this CSR's pseudoregister. */
668 /* mep_csr_registers[i] describes the i'th CSR.
671 #define CSR(name) MEP_RAW_ ## name ## _REGNUM, MEP_ ## name ## _REGNUM
673 { CSR(PC), 0xffffffff }, /* manual says r/o, but we can write it */
674 { CSR(LP), 0xffffffff },
675 { CSR(SAR), 0x0000003f },
676 { CSR(CSR3), 0xffffffff }
[all...] |
| /src/external/gpl3/gdb.old/dist/gdb/ |
| mep-tdep.c | 629 #define IS_CSR_REGNUM(n) (IN_SET (CSR, (n)))
653 The following table describes the special properties of each CSR. */
656 /* The number of this CSR's raw register. */
659 /* The number of this CSR's pseudoregister. */
668 /* mep_csr_registers[i] describes the i'th CSR.
671 #define CSR(name) MEP_RAW_ ## name ## _REGNUM, MEP_ ## name ## _REGNUM
673 { CSR(PC), 0xffffffff }, /* manual says r/o, but we can write it */
674 { CSR(LP), 0xffffffff },
675 { CSR(SAR), 0x0000003f },
676 { CSR(CSR3), 0xffffffff }
[all...] |
| /src/sys/arch/arm/marvell/ |
| mvsocpmu.c | 101 uint32_t csr; local
104 csr = MVSOCPMU_TM_READ(sc, CSR);
105 sc->sc_deflims.sel_warnmin = UC2UK(sc->sc_val2uc(TM_CSR_COOLTHR(csr)));
107 UC2UK(sc->sc_val2uc(TM_CSR_OVERHEATTHR(csr)));
140 uint32_t csr, uc, uk; local
142 csr = MVSOCPMU_TM_READ(sc, CSR);
143 if (csr & TM_CSR_TMDIS) {
147 uc = sc->sc_val2uc(TM_CSR_THERMTEMPOUT(csr)); /* uC *
158 uint32_t csr; local
171 uint32_t csr, mask; local
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVFrameLowering.cpp | 41 [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
89 [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| lm32-opc.c | 398 /* rcsr $r2,$csr */
401 { { MNEM, ' ', OP (R2), ',', OP (CSR), 0 } },
482 /* wcsr $csr,$r1 */
485 { { MNEM, ' ', OP (CSR), ',', OP (R1), 0 } },
|
| lm32-opinst.c | 151 { INPUT, "csr", HW_H_CSR, CGEN_MODE_SI, OP_ENT (CSR), 0, 0 },
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| lm32-opc.c | 398 /* rcsr $r2,$csr */
401 { { MNEM, ' ', OP (R2), ',', OP (CSR), 0 } },
482 /* wcsr $csr,$r1 */
485 { { MNEM, ' ', OP (CSR), ',', OP (R1), 0 } },
|
| lm32-opinst.c | 151 { INPUT, "csr", HW_H_CSR, CGEN_MODE_SI, OP_ENT (CSR), 0, 0 },
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| lm32-opc.c | 398 /* rcsr $r2,$csr */
401 { { MNEM, ' ', OP (R2), ',', OP (CSR), 0 } },
482 /* wcsr $csr,$r1 */
485 { { MNEM, ' ', OP (CSR), ',', OP (R1), 0 } },
|
| lm32-opinst.c | 151 { INPUT, "csr", HW_H_CSR, CGEN_MODE_SI, OP_ENT (CSR), 0, 0 },
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| lm32-opc.c | 398 /* rcsr $r2,$csr */
401 { { MNEM, ' ', OP (R2), ',', OP (CSR), 0 } },
482 /* wcsr $csr,$r1 */
485 { { MNEM, ' ', OP (CSR), ',', OP (R1), 0 } },
|
| /src/sys/arch/arm/sociox/ |
| sni_i2c.c | 80 #define CSR 0x14 /* 5:0 clock divisor */
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 457 for (const CalleeSavedInfo &CSR : CSI) {
458 unsigned Reg = CSR.getReg();
463 TII.loadRegFromStackSlot(MBB, MI, Reg, CSR.getFrameIdx(), RC, TRI);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/ADT/ |
| Triple.h | 156 CSR,
|
