| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonDepTimingClasses.h | 21 case Hexagon::Sched::tc_112d30d6:
22 case Hexagon::Sched::tc_151bf368:
23 case Hexagon::Sched::tc_1c2c7a4a:
24 case Hexagon::Sched::tc_1d41f8b7:
25 case Hexagon::Sched::tc_23708a21:
26 case Hexagon::Sched::tc_24f426ab:
27 case Hexagon::Sched::tc_2f573607:
28 case Hexagon::Sched::tc_388f9897:
29 case Hexagon::Sched::tc_3d14a17b:
30 case Hexagon::Sched::tc_3fbf1042
[all...] |
| HexagonRegisterInfo.cpp | 1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
9 // This file contains the Hexagon implementation of the TargetRegisterInfo
15 #include "Hexagon.h"
48 "hexagon-frame-index-search-range", cl::init(32), cl::Hidden,
52 "hexagon-frame-index-reuse-limit", cl::init(~0), cl::Hidden,
57 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
62 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
63 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1
[all...] |
| HexagonInstrInfo.cpp | 1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
14 #include "Hexagon.h"
64 #define DEBUG_TYPE "hexagon-instrinfo"
72 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
76 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
79 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
102 /// Constants for Hexagon instructions.
118 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP)
[all...] |
| HexagonAsmPrinter.cpp | 1 //===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
10 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
16 #include "Hexagon.h"
68 assert(Hexagon::IntRegsRegClass.contains(Reg));
71 assert(Hexagon::DoubleRegsRegClass.contains(Pair));
135 if (Hexagon::DoubleRegsRegClass.contains(RegNumber))
137 Hexagon::isub_lo :
138 Hexagon::isub_hi);
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
277 case Hexagon::A2_iconst:
[all...] |
| HexagonNewValueJump.cpp | 1 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
9 // This implements NewValueJump pass in Hexagon.
24 #include "Hexagon.h"
55 #define DEBUG_TYPE "hexagon-nvj"
86 StringRef getPassName() const override { return "Hexagon NewValueJump"; }
109 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
110 "Hexagon NewValueJump", false, false)
112 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
113 "Hexagon NewValueJump", false, false)
157 if (!Hexagon::IntRegsRegClass.contains(Op.getReg())
[all...] |
| HexagonCFGOptimizer.cpp | 9 #include "Hexagon.h"
49 StringRef getPassName() const override { return "Hexagon CFG Optimizer"; }
64 case Hexagon::J2_jumpt:
65 case Hexagon::J2_jumptpt:
66 case Hexagon::J2_jumpf:
67 case Hexagon::J2_jumpfpt:
68 case Hexagon::J2_jumptnew:
69 case Hexagon::J2_jumpfnew:
70 case Hexagon::J2_jumptnewpt:
71 case Hexagon::J2_jumpfnewpt
[all...] |
| HexagonSubtarget.h | 1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
9 // This file declares the Hexagon specific subclass of TargetSubtarget.
66 Hexagon::ArchEnum HexagonArchVersion;
67 Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
141 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
144 return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
147 return getHexagonArchVersion() >= Hexagon::ArchEnum::V55;
150 return getHexagonArchVersion() == Hexagon::ArchEnum::V55;
153 return getHexagonArchVersion() >= Hexagon::ArchEnum::V60
[all...] |
| HexagonVectorPrint.cpp | 37 #define DEBUG_TYPE "hexagon-vector-print"
64 StringRef getPassName() const override { return "Hexagon VectorPrint pass"; }
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) ||
75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) ||
76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) ||
77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3)
[all...] |
| HexagonDepArch.h | 23 namespace Hexagon {
39 {"generic", Hexagon::ArchEnum::V5},
40 {"hexagonv5", Hexagon::ArchEnum::V5},
41 {"hexagonv55", Hexagon::ArchEnum::V55},
42 {"hexagonv60", Hexagon::ArchEnum::V60},
43 {"hexagonv62", Hexagon::ArchEnum::V62},
44 {"hexagonv65", Hexagon::ArchEnum::V65},
45 {"hexagonv66", Hexagon::ArchEnum::V66},
46 {"hexagonv67", Hexagon::ArchEnum::V67},
47 {"hexagonv67t", Hexagon::ArchEnum::V67}
[all...] |
| HexagonConstExtenders.cpp | 27 #define DEBUG_TYPE "hexagon-cext-opt"
31 static cl::opt<unsigned> CountThreshold("hexagon-cext-threshold",
35 static cl::opt<unsigned> ReplaceLimit("hexagon-cext-limit", cl::init(0),
225 return "Hexagon constant-extender optimization";
568 INITIALIZE_PASS_BEGIN(HexagonConstExtenders, "hexagon-cext-opt",
569 "Hexagon constant-extender optimization", false, false)
571 INITIALIZE_PASS_END(HexagonConstExtenders, "hexagon-cext-opt",
572 "Hexagon constant-extender optimization", false, false)
799 case Hexagon::S4_storeirbt_io:
800 case Hexagon::S4_storeirbf_io
[all...] |
| HexagonGenPredicate.cpp | 92 return "Hexagon generate predicate operations";
131 INITIALIZE_PASS_BEGIN(HexagonGenPredicate, "hexagon-gen-pred",
132 "Hexagon generate predicate operations", false, false)
134 INITIALIZE_PASS_END(HexagonGenPredicate, "hexagon-gen-pred",
135 "Hexagon generate predicate operations", false, false)
141 return RC == &Hexagon::PredRegsRegClass;
145 using namespace Hexagon;
198 case Hexagon::C2_cmpeqi:
199 case Hexagon::C4_cmpneqi:
214 case Hexagon::C2_tfrpr
[all...] |
| HexagonMachineFunctionInfo.h | 1 //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
17 namespace Hexagon {
22 } // end namespace Hexagon
24 /// Hexagon target-specific information for each MachineFunction.
62 PacketInfo[MI] |= Hexagon::StartPacket;
65 PacketInfo[MI] |= Hexagon::EndPacket;
69 (PacketInfo.find(MI)->second & Hexagon::StartPacket));
73 (PacketInfo.find(MI)->second & Hexagon::EndPacket));
|
| HexagonFixupHwLoops.cpp | 14 #include "Hexagon.h"
28 "hexagon-loop-range", cl::Hidden, cl::init(200),
53 return "Hexagon Hardware Loop Fixup";
77 "Hexagon Hardware Loops Fixup", false, false)
85 return MI.getOpcode() == Hexagon::J2_loop0r ||
86 MI.getOpcode() == Hexagon::J2_loop0i ||
87 MI.getOpcode() == Hexagon::J2_loop1r ||
88 MI.getOpcode() == Hexagon::J2_loop1i;
97 /// For Hexagon, if the loop label is to far from the
176 case Hexagon::J2_loop0r
[all...] |
| HexagonFrameLowering.h | 1 //==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
12 #include "Hexagon.h"
93 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
94 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
95 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }
[all...] |
| HexagonSplitConst32AndConst64.cpp | 46 return "Hexagon Split Const32s and Const64s";
59 "Hexagon Split Const32s and Const64s", false, false)
78 if (Opc == Hexagon::CONST32) {
82 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg)
85 } else if (Opc == Hexagon::CONST64) {
89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo);
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
95 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo)
97 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestHi)
|
| HexagonVExtract.cpp | 12 #include "Hexagon.h"
30 static cl::opt<unsigned> VExtractThreshold("hexagon-vextract-threshold",
46 return "Hexagon optimize vextract";
64 INITIALIZE_PASS(HexagonVExtract, "hexagon-vextract",
65 "Hexagon optimize vextract", false, false)
71 Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
79 if (DI->getOpcode() == Hexagon::A2_tfrsi) {
83 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L2_loadri_io), ElemR)
90 Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
91 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::A2_andir), IdxR
[all...] |
| HexagonRDFOpt.cpp | 68 return "Hexagon RDF optimizations";
105 INITIALIZE_PASS_BEGIN(HexagonRDFOpt, "hexagon-rdf-opt",
106 "Hexagon RDF optimizations", false, false)
109 INITIALIZE_PASS_END(HexagonRDFOpt, "hexagon-rdf-opt",
110 "Hexagon RDF optimizations", false, false)
120 case Hexagon::A2_combinew: {
125 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi),
127 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo),
131 case Hexagon::A2_addi: {
137 case Hexagon::A2_tfr:
[all...] |
| HexagonCopyToCombine.cpp | 1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
34 #define DEBUG_TYPE "hexagon-copy-combine"
82 return "Hexagon Copy-To-Combine Pass";
126 INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
127 "Hexagon Copy-To-Combine Pass", false, false)
132 case Hexagon::A2_tfr: {
140 return Hexagon::IntRegsRegClass.contains(DestReg) &&
141 Hexagon::IntRegsRegClass.contains(SrcReg);
144 case Hexagon::A2_tfrsi: {
160 return Hexagon::IntRegsRegClass.contains(DestReg) &
[all...] |
| HexagonPeephole.cpp | 1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
36 #include "Hexagon.h"
57 #define DEBUG_TYPE "hexagon-peephole"
59 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
63 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
67 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
71 static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
95 return "Hexagon optimize redundant zero and size extends";
106 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole"
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
9 #define DEBUG_TYPE "hexagon-disassembler"
36 using namespace Hexagon;
42 /// Hexagon disassembler for all Hexagon platforms.
173 MI.setOpcode(Hexagon::BUNDLE);
203 case Hexagon::S2_allocframe:
204 if (MI.getOperand(0).getReg() == Hexagon::R29) {
205 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
210 case Hexagon::L2_deallocframe
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 30 using namespace Hexagon;
32 #define DEBUG_TYPE "hexagon-mcduplex-info"
200 case Hexagon::L2_loadri_io:
207 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
217 case Hexagon::L2_loadrub_io:
237 case Hexagon::L2_loadrh_io:
238 case Hexagon::L2_loadruh_io:
248 case Hexagon::L2_loadrb_io:
258 case Hexagon::L2_loadrd_io:
263 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &
[all...] |
| HexagonMCCompound.cpp | 1 //=== HexagonMCCompound.cpp - Hexagon Compound checker -------------------===//
26 using namespace Hexagon;
28 #define DEBUG_TYPE "hexagon-mccompound"
92 case Hexagon::C2_cmpeq:
93 case Hexagon::C2_cmpgt:
94 case Hexagon::C2_cmpgtu:
100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
105 case Hexagon::C2_cmpeqi:
106 case Hexagon::C2_cmpgti
[all...] |
| HexagonMCInstrInfo.cpp | 1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
9 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
36 return Register != Hexagon::NoRegister;
39 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
45 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
50 Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
71 MCInst const &Hexagon::PacketIterator::operator*() const {
77 bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const {
102 iterator_range<Hexagon::PacketIterator
[all...] |
| HexagonMCChecker.h | 10 // packet constraint rules of the Hexagon ISA.
106 return (Hexagon::P0 == R || Hexagon::P1 == R || Hexagon::P2 == R ||
107 Hexagon::P3 == R);
111 return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R ||
112 Hexagon::LC1 == R);
|
| HexagonMCChecker.cpp | 10 // packet constraint rules of the Hexagon ISA.
35 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
39 ReadOnly.insert(Hexagon::PC);
40 ReadOnly.insert(Hexagon::C9_8);
44 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
45 Defs[Hexagon::LC0].insert(Unconditional);
48 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
49 Defs[Hexagon::LC1].insert(Unconditional);
91 unsigned PredReg = Hexagon::NoRegister;
106 if (Hexagon::R31 != R && MCID.isCall()
[all...] |
