| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
30 return STI.isPositionIndependent() ? Mips::B : Mips::J;
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) |
[all...] |
| MipsInstrInfo.cpp | 1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
9 // This file contains the Mips implementation of the TargetInstrInfo class.
41 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
62 BuildMI(MBB, MI, DL, get(Mips::NOP));
137 "# of Mips branch conditions must be <= 3!");
186 "Invalid Mips branch condition!");
282 case Mips::B:
283 case Mips::BAL:
284 case Mips::BAL_BR
[all...] |
| MipsRegisterInfo.cpp | 1 //===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
9 // This file contains the MIPS implementation of the TargetRegisterInfo class.
15 #include "Mips.h"
37 #define DEBUG_TYPE "mips-reg-info"
42 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
44 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
56 return &Mips::GPRMM16RegClass;
58 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass
[all...] |
| MipsExpandPseudo.cpp | 16 // spills between ll and sc. These stores cause some MIPS implementations to
21 #include "Mips.h"
30 #define DEBUG_TYPE "mips-pseudo"
49 return "Mips pseudo instruction expansion pass";
84 unsigned ZERO = Mips::ZERO;
85 unsigned BNE = Mips::BNE;
86 unsigned BEQ = Mips::BEQ;
88 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH
[all...] |
| Mips16InstrInfo.cpp | 43 : MipsInstrInfo(STI, Mips::Bimm16) {}
75 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
76 Mips::GPR32RegClass.contains(SrcReg))
77 Opc = Mips::MoveR3216;
78 else if (Mips::GPR32RegClass.contains(DestReg) &&
79 Mips::CPU16RegsRegClass.contains(SrcReg))
80 Opc = Mips::Move32R16;
81 else if ((SrcReg == Mips::HI0) &&
82 (Mips::CPU16RegsRegClass.contains(DestReg)))
83 Opc = Mips::Mfhi16, SrcReg = 0
[all...] |
| MipsSERegisterInfo.cpp | 15 #include "Mips.h"
39 #define DEBUG_TYPE "mips-reg-info"
56 return &Mips::GPR32RegClass;
59 return &Mips::GPR64RegClass;
68 case Mips::LD_B:
69 case Mips::ST_B:
71 case Mips::LD_H:
72 case Mips::ST_H:
74 case Mips::LD_W:
75 case Mips::ST_W
[all...] |
| MipsOptionRecord.h | 10 // ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
11 // specific ELF sections like .Mips.options. Specific records should subclass
14 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID))
[all...] |
| MicroMipsSizeReduction.cpp | 13 #include "Mips.h"
214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
218 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
220 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
222 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM)
[all...] |
| MipsMachineFunction.cpp | 1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
22 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
36 return Mips::CPU16RegsRegClass;
39 return Mips::GPRMM16RegClass;
42 return Mips::GPR64RegClass;
44 return Mips::GPR32RegClass;
74 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
80 MF.getRegInfo().addLiveIn(Mips::T9_64);
81 MBB.addLiveIn(Mips::T9_64)
[all...] |
| MipsBranchExpansion.cpp | 78 #include "Mips.h"
107 #define DEBUG_TYPE "mips-branch-expansion"
113 SkipLongBranch("skip-mips-long-branch", cl::init(false),
114 cl::desc("MIPS: Skip branch expansion pass."), cl::Hidden);
117 ForceLongBranch("force-mips-long-branch", cl::init(false),
118 cl::desc("MIPS: Expand all branches to long format."),
143 return "Mips Branch Expansion Pass";
380 unsigned JR = ABI.IsN64() ? Mips::JR64 : Mips::JR;
381 unsigned JIC = ABI.IsN64() ? Mips::JIC64 : Mips::JIC
[all...] |
| MipsAsmPrinter.cpp | 1 //===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
10 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
20 #include "Mips.h"
70 #define DEBUG_TYPE "mips-asm-printer"
123 TmpInst0.setOpcode(Mips::JALR64);
128 TmpInst0.setOpcode(Mips::JRC16_MMR6);
130 TmpInst0.setOpcode(Mips::JALR);
135 TmpInst0.setOpcode(Mips::JR_MM);
138 TmpInst0.setOpcode(Mips::JR);
144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO
[all...] |
| MipsInstructionSelector.cpp | 10 /// Mips.
23 #define DEBUG_TYPE "mips-isel"
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID;
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID;
128 return &Mips::GPR32RegClass;
136 return &Mips::FGR32RegClass;
137 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)}
[all...] |
| Mips16ISelLowering.cpp | 24 #define DEBUG_TYPE "mips-lower"
30 "pseudos for Mips 16"),
125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
169 case Mips::SelBeqZ:
170 return emitSel16(Mips::BeqzRxImm16, MI, BB);
171 case Mips::SelBneZ:
172 return emitSel16(Mips::BnezRxImm16, MI, BB);
173 case Mips::SelTBteqZCmpi:
174 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsABIInfo.cpp | 1 //===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
20 EmitJalrReloc("mips-jalr-reloc", cl::Hidden,
21 cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"),
25 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
28 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
[all...] |
| MipsAsmBackend.cpp | 1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
48 case Mips::fixup_Mips_LO16:
49 case Mips::fixup_Mips_GPREL16:
50 case Mips::fixup_Mips_GPOFF_HI:
51 case Mips::fixup_Mips_GPOFF_LO:
52 case Mips::fixup_Mips_GOT_PAGE:
53 case Mips::fixup_Mips_GOT_OFST:
54 case Mips::fixup_Mips_GOT_DISP:
55 case Mips::fixup_Mips_GOT_LO16:
56 case Mips::fixup_Mips_CALL_LO16
[all...] |
| MipsInstPrinter.cpp | 1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
9 // This class prints an Mips MCInst to a .s file.
36 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
84 case Mips::RDHWR:
85 case Mips::RDHWR64:
89 case Mips::Save16:
94 case Mips::SaveX16:
99 case Mips::Restore16:
104 case Mips::RestoreX16
[all...] |
| MipsNaClELFStreamer.cpp | 1 //===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===//
9 // This file implements MCELFStreamer for Mips NaCl. It emits .o object files
19 #include "Mips.h"
33 #define DEBUG_TYPE "mips-mc-nacl"
37 const unsigned IndirectBranchMaskReg = Mips::T6;
38 const unsigned LoadStoreStackMaskReg = Mips::T7;
59 if (MI.getOpcode() == Mips::JALR) {
63 return MI.getOperand(0).getReg() == Mips::ZERO;
65 return MI.getOpcode() == Mips::JR;
70 && MI.getOperand(0).getReg() == Mips::SP)
[all...] |
| MipsABIFlagsSection.cpp | 1 //===- MipsABIFlagsSection.cpp - Mips ELF ABI Flags Section ---------------===//
20 return Mips::Val_GNU_MIPS_ABI_FP_ANY;
22 return Mips::Val_GNU_MIPS_ABI_FP_SOFT;
24 return Mips::Val_GNU_MIPS_ABI_FP_XX;
26 return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
29 return OddSPReg ? Mips::Val_GNU_MIPS_ABI_FP_64
30 : Mips::Val_GNU_MIPS_ABI_FP_64A;
31 return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
52 return (uint8_t)Mips::AFL_REG_32;
|
| MipsMCCodeEmitter.cpp | 1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
76 case Mips::DSLL:
77 Inst.setOpcode(Mips::DSLL32);
79 case Mips::DSRL:
80 Inst.setOpcode(Mips::DSRL32);
82 case Mips::DSRA:
83 Inst.setOpcode(Mips::DSRA32);
85 case Mips::DROTR:
86 Inst.setOpcode(Mips::DROTR32);
101 if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC |
[all...] |
| MipsABIFlagsSection.h | 1 //===- MipsABIFlagsSection.h - Mips ELF ABI Flags Section -------*- C++ -*-===//
29 // The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
32 Mips::AFL_REG GPRSize = Mips::AFL_REG_NONE;
34 Mips::AFL_REG CPR1Size = Mips::AFL_REG_NONE;
36 Mips::AFL_REG CPR2Size = Mips::AFL_REG_NONE;
38 Mips::AFL_EXT ISAExtension = Mips::AFL_EXT_NONE
[all...] |
| MipsELFObjectWriter.cpp | 1 //===-- MipsELFObjectWriter.cpp - Mips ELF Writer -------------------------===//
31 #define DEBUG_TYPE "mips-elf-object-writer"
139 /// R_(MIPS|MICROMIPS|MIPS16)_HI16 for all symbols and
140 /// R_(MIPS|MICROMIPS|MIPS16)_GOT16 for local symbols only.
229 "MIPS does not support one byte relocations");
231 case Mips::fixup_Mips_16:
234 case Mips::fixup_Mips_32:
237 case Mips::fixup_Mips_64:
246 case Mips::fixup_Mips_Branch_PCRel:
247 case Mips::fixup_Mips_PC16
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
62 #define DEBUG_TYPE "mips-asm-parser"
122 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
123 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
124 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5
[all...] |
| /src/external/apache2/llvm/lib/libLLVMMipsAsmParser/ |
| Makefile | 8 CPPFLAGS+= -I${MIPS_OBJDIR} -I${LLVM_SRCDIR}/lib/Target/Mips
10 .PATH: ${LLVM_SRCDIR}/lib/Target/Mips/AsmParser
|
| /src/external/apache2/llvm/lib/libLLVMMipsDisassembler/ |
| Makefile | 8 CPPFLAGS+= -I${MIPS_OBJDIR} -I${LLVM_SRCDIR}/lib/Target/Mips
10 .PATH: ${LLVM_SRCDIR}/lib/Target/Mips/Disassembler
|
| /src/external/apache2/llvm/lib/libLLVMMipsTargetInfo/ |
| Makefile | 8 CPPFLAGS+= -I${MIPS_OBJDIR} -I${LLVM_SRCDIR}/lib/Target/Mips
10 .PATH: ${LLVM_SRCDIR}/lib/Target/Mips/TargetInfo
|
