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  /src/external/mit/isl/dist/test_inputs/codegen/omega/
p.delft2-0.c 1 if (P1 >= 0 && P1 <= 3 && P2 >= 0 && P2 <= 3)
2 for (int c0 = P1 - 1; c0 <= 3; c0 += 1)
6 if (P1 >= 1 && c0 + 1 == P1 && 4 * P1 >= 2 * c2 + 9 * floord(4 * P1 - 2 * c2 - 1, 9) + 7) {
7 s0(P1 - 1, P2, c2, c3, ((-4 * P1 + 2 * c2 + 9) % 9) + 1, -4 * P2 + 2 * c3 - 9 * floord(-4 * P2 + 2 * c3, 9));
8 } else if (P1 == 0 && c0 == 3 && c2 % 4 == 0)
    [all...]
hpf-0.c 1 if (P2 >= 0 && P2 <= 3 && P1 == P2)
p.delft-0.c 1 if (P2 >= 0 && P2 <= 3 && P1 == P2)
  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
s1.s 10 P1 = R1;
11 LSETUP ( ls0 , ls0 ) LC0 = P1;
19 P1 = R1;
20 LSETUP ( ls1 , ls1 ) LC1 = P1;
issue126.s 8 P1 = R0;
12 P1 = ( P1 + P0 ) << 2;
brcc.s 12 p1 = p0; define
24 P1 += 8;
25 r6 = p1;
49 P1 += 8;
50 R6 = P1;
67 P1 += 0xc;
68 R6 = P1;
75 P1 += 4;
76 R6 = P1;
90 P1 += 8
    [all...]
a3.s 6 loadsym P1, middle;
8 R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 );
9 R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 );
10 R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 );
11 R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 );
12 R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 );
13 R0 = W [ P1 + -12 ] (Z); DBGA ( R0.L , 44 );
14 R0 = W [ P1 + -14 ] (Z); DBGA ( R0.L , 43 );
15 R0 = W [ P1 + -16 ] (Z); DBGA ( R0.L , 42 );
16 R0 = W [ P1 + -18 ] (Z); DBGA ( R0.L , 41 )
    [all...]
7641.s 10 loadsym P1, element2
13 R1 = B [P1]; // R1 should get 02
17 TESTSET(P1); // should clear CC and not change MSB of memory
21 R3 = B [P1]; // R3 should get 02
e0.s 12 P1 = re (Z); // load a pointer to ihandler interrupt 1
13 P1.H = re;
14 [ P0 + (4*3) ] = P1;
17 imm32 p1, 0xFFE02104;
18 [P1] = R0;
c_regmv_pr_pr.s 9 imm32 p1, 0x20021003;
15 imm32 p1, 0x20021003;
20 P1 = P1;
21 P2 = P1;
22 P4 = P1;
23 P5 = P1;
24 FP = P1;
25 CHECKREG p1, 0x20021003;
31 imm32 p1, 0x20021003
    [all...]
c_comp3op_pr_plus_pr_sh1.s 8 imm32 p1, 0x89ab1def;
15 P1 = P1 + ( P1 << 1 );
16 P2 = P1 + ( P2 << 1 );
17 P3 = P1 + ( P3 << 1 );
18 P4 = P1 + ( P4 << 1 );
19 P5 = P1 + ( P5 << 1 );
20 SP = P1 + ( SP << 1 );
21 FP = P1 + FP
    [all...]
c_comp3op_pr_plus_pr_sh2.s 8 imm32 p1, 0x89ab1def;
15 P1 = P1 + ( P1 << 2 );
16 P2 = P1 + ( P2 << 2 );
17 P3 = P1 + ( P3 << 2 );
18 P4 = P1 + ( P4 << 2 );
19 P5 = P1 + ( P5 << 2 );
20 SP = P1 + ( SP << 2 );
21 FP = P1 + FP
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
s1.s 10 P1 = R1;
11 LSETUP ( ls0 , ls0 ) LC0 = P1;
19 P1 = R1;
20 LSETUP ( ls1 , ls1 ) LC1 = P1;
issue126.s 8 P1 = R0;
12 P1 = ( P1 + P0 ) << 2;
brcc.s 12 p1 = p0; define
24 P1 += 8;
25 r6 = p1;
49 P1 += 8;
50 R6 = P1;
67 P1 += 0xc;
68 R6 = P1;
75 P1 += 4;
76 R6 = P1;
90 P1 += 8
    [all...]
a3.s 6 loadsym P1, middle;
8 R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 );
9 R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 );
10 R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 );
11 R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 );
12 R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 );
13 R0 = W [ P1 + -12 ] (Z); DBGA ( R0.L , 44 );
14 R0 = W [ P1 + -14 ] (Z); DBGA ( R0.L , 43 );
15 R0 = W [ P1 + -16 ] (Z); DBGA ( R0.L , 42 );
16 R0 = W [ P1 + -18 ] (Z); DBGA ( R0.L , 41 )
    [all...]
7641.s 10 loadsym P1, element2
13 R1 = B [P1]; // R1 should get 02
17 TESTSET(P1); // should clear CC and not change MSB of memory
21 R3 = B [P1]; // R3 should get 02
e0.s 12 P1 = re (Z); // load a pointer to ihandler interrupt 1
13 P1.H = re;
14 [ P0 + (4*3) ] = P1;
17 imm32 p1, 0xFFE02104;
18 [P1] = R0;
c_regmv_pr_pr.s 9 imm32 p1, 0x20021003;
15 imm32 p1, 0x20021003;
20 P1 = P1;
21 P2 = P1;
22 P4 = P1;
23 P5 = P1;
24 FP = P1;
25 CHECKREG p1, 0x20021003;
31 imm32 p1, 0x20021003
    [all...]
  /src/external/gpl3/binutils/dist/opcodes/
ia64-opc-a.c 150 {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
151 {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
152 {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
153 {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
154 {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
155 {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
156 {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
157 {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
158 {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
159 {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}
    [all...]
  /src/external/gpl3/binutils.old/dist/opcodes/
ia64-opc-a.c 150 {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
151 {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
152 {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
153 {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
154 {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
155 {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
156 {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
157 {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
158 {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
159 {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}
    [all...]
  /src/external/gpl3/gdb/dist/opcodes/
ia64-opc-a.c 150 {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
151 {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
152 {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
153 {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
154 {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
155 {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
156 {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
157 {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
158 {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
159 {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}
    [all...]
  /src/external/gpl3/gdb.old/dist/opcodes/
ia64-opc-a.c 150 {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY},
151 {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY},
152 {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY},
153 {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY},
154 {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY},
155 {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY},
156 {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY},
157 {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY},
158 {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY},
159 {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}
    [all...]
  /src/external/gpl3/binutils/dist/
setup.com 8 $ if (P1 .EQS. "CONFIGURE") .OR. (P1 .EQS. "ALL")
22 $ if (P1 .EQS. "BUILD") .OR. (P1 .EQS. "ALL")
36 $ if P1 .EQS. "MAKE"
  /src/external/gpl3/binutils.old/dist/
setup.com 8 $ if (P1 .EQS. "CONFIGURE") .OR. (P1 .EQS. "ALL")
22 $ if (P1 .EQS. "BUILD") .OR. (P1 .EQS. "ALL")
36 $ if P1 .EQS. "MAKE"

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