| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600RegisterInfo.cpp | 37 BitVector Reserved(getNumRegs());
42 reserveRegisterTuples(Reserved, R600::ZERO);
43 reserveRegisterTuples(Reserved, R600::HALF);
44 reserveRegisterTuples(Reserved, R600::ONE);
45 reserveRegisterTuples(Reserved, R600::ONE_INT);
46 reserveRegisterTuples(Reserved, R600::NEG_HALF);
47 reserveRegisterTuples(Reserved, R600::NEG_ONE);
48 reserveRegisterTuples(Reserved, R600::PV_X);
49 reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
50 reserveRegisterTuples(Reserved, R600::ALU_CONST)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 159 BitVector Reserved(getNumRegs());
163 Reserved.set(ReservedGPR32[I]);
167 Reserved.set(Mips::T6); // Reserved for control flow mask.
168 Reserved.set(Mips::T7); // Reserved for memory access mask.
169 Reserved.set(Mips::T8); // Reserved for thread pointer.
173 Reserved.set(ReservedGPR64[I]);
177 Reserved.set(Mips::GP)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 55 BitVector Reserved(getNumRegs());
57 // FIXME: G1 reserved for now for large imm generation by frame code.
58 Reserved.set(SP::G1);
62 Reserved.set(SP::G2);
63 Reserved.set(SP::G3);
64 Reserved.set(SP::G4);
66 // G5 is not reserved in 64 bit mode.
68 Reserved.set(SP::G5);
70 Reserved.set(SP::O6);
71 Reserved.set(SP::I6)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 149 BitVector Reserved(getNumRegs());
150 Reserved.set(Hexagon::R29);
151 Reserved.set(Hexagon::R30);
152 Reserved.set(Hexagon::R31);
153 Reserved.set(Hexagon::VTMP);
156 Reserved.set(Hexagon::GELR); // G0
157 Reserved.set(Hexagon::GSR); // G1
158 Reserved.set(Hexagon::GOSP); // G2
159 Reserved.set(Hexagon::G3); // G3
162 Reserved.set(Hexagon::SA0); // C
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 74 BitVector Reserved(getNumRegs());
77 // Mark 4 special registers with subregisters as reserved.
78 Reserved.set(MSP430::PCB);
79 Reserved.set(MSP430::SPB);
80 Reserved.set(MSP430::SRB);
81 Reserved.set(MSP430::CGB);
82 Reserved.set(MSP430::PC);
83 Reserved.set(MSP430::SP);
84 Reserved.set(MSP430::SR);
85 Reserved.set(MSP430::CG)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiRegisterInfo.cpp | 43 BitVector Reserved(getNumRegs());
45 Reserved.set(Lanai::R0);
46 Reserved.set(Lanai::R1);
47 Reserved.set(Lanai::PC);
48 Reserved.set(Lanai::R2);
49 Reserved.set(Lanai::SP);
50 Reserved.set(Lanai::R4);
51 Reserved.set(Lanai::FP);
52 Reserved.set(Lanai::R5);
53 Reserved.set(Lanai::RR1)
[all...] |
| /src/sys/external/bsd/acpica/dist/include/ |
| actbl3.h | 9 * All rights reserved.
149 UINT8 Reserved[3];
197 UINT8 Reserved; /* Must be 1 */
222 ACPI_SPMI_RESERVED = 5 /* 5 and above are reserved */
237 UINT64 Reserved; /* Reserved, must be zero */
253 ACPI_SRAT_TYPE_RESERVED = 8 /* 8 and greater are reserved */
285 UINT16 Reserved; /* Reserved, must be zero */
290 UINT64 Reserved2; /* Reserved, must be zero *
[all...] |
| actbl2.h | 9 * All rights reserved.
142 UINT8 Reserved;
162 #define ACPI_AEST_NODE_TYPE_RESERVED 7 /* 7 and above are reserved */
175 UINT8 Reserved;
187 #define ACPI_AEST_RESOURCE_RESERVED 3 /* 3 and above are reserved */
194 UINT32 Reserved;
203 #define ACPI_AEST_CACHE_RESERVED 3 /* 3 and above are reserved */
210 UINT32 Reserved;
274 #define ACPI_AEST_GIC_RESERVED 4 /* 4 and above are reserved */
298 UINT8 Reserved[3]
[all...] |
| actbl1.h | 9 * All rights reserved.
91 /* Reserved table signatures */
147 UINT8 Reserved;
186 UINT8 Reserved;
351 UINT32 Reserved;
365 UINT8 Reserved[3];
429 ACPI_BERT_ERROR_RESERVED = 4 /* 4 and greater are reserved */
476 UINT8 Reserved[3];
496 UINT8 Reserved[6];
507 UINT8 Reserved;
[all...] |
| /src/external/apache2/llvm/dist/clang/include/clang/Lex/ |
| HeaderMapTypes.h | 31 uint16_t Reserved; // Reserved for future use - zero for now.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.cpp | 56 BitVector Reserved(getNumRegs());
60 Reserved.set(AVR::R0);
61 Reserved.set(AVR::R1);
62 Reserved.set(AVR::R1R0);
65 Reserved.set(AVR::SPL);
66 Reserved.set(AVR::SPH);
67 Reserved.set(AVR::SP);
75 // TODO: Write a pass to enumerate functions which reserved the Y register
78 Reserved.set(AVR::R28);
79 Reserved.set(AVR::R29)
[all...] |
| /src/sys/external/bsd/acpica/dist/common/ |
| dmtbinfo1.c | 9 * All rights reserved.
99 {ACPI_DMT_UINT8, ACPI_AESTH_OFFSET (Reserved), "Reserved", 0},
105 {ACPI_DMT_UINT64, ACPI_AESTH_OFFSET (Reserved1), "Reserved", 0},
120 {ACPI_DMT_UINT8, ACPI_AEST0_OFFSET (Reserved), "Reserved", 0},
134 {ACPI_DMT_UINT32, ACPI_AEST0A_OFFSET (Reserved), "Reserved", 0},
143 {ACPI_DMT_UINT32, ACPI_AEST0B_OFFSET (Reserved), "Reserved", 0}
[all...] |
| dmtbinfo2.c | 9 * All rights reserved.
96 {ACPI_DMT_UINT24, ACPI_AGDI_OFFSET (Reserved[0]), "Reserved", 0},
127 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Reserved), "Reserved", 0},
147 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (Reserved), "Reserved", 0},
166 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Reserved", 0},
204 {ACPI_DMT_UINT16, ACPI_IORTA_OFFSET (Reserved), "Reserved", 0}
[all...] |
| dmtbinfo3.c | 9 * All rights reserved.
95 {ACPI_DMT_UINT16, ACPI_CCEL_OFFSET (Reserved), "Reserved", 0},
140 {ACPI_DMT_UINT24, ACPI_SPCR_OFFSET (Reserved[0]), "Reserved", 0},
176 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (Reserved), "Reserved", DT_NON_ZERO}, /* Value must be 1 */
180 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (Reserved1), "Reserved", 0},
188 {ACPI_DMT_UINT8, ACPI_SPMI_OFFSET (Reserved2), "Reserved", 0},
202 {ACPI_DMT_UINT64, ACPI_SRAT_OFFSET (Reserved), "Reserved", 0}
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVRegisterInfo.cpp | 78 BitVector Reserved(getNumRegs());
80 // Mark any registers requested to be reserved as such
83 markSuperRegs(Reserved, Reg);
86 // Use markSuperRegs to ensure any register aliases are also reserved
87 markSuperRegs(Reserved, RISCV::X0); // zero
88 markSuperRegs(Reserved, RISCV::X2); // sp
89 markSuperRegs(Reserved, RISCV::X3); // gp
90 markSuperRegs(Reserved, RISCV::X4); // tp
92 markSuperRegs(Reserved, RISCV::X8); // fp
96 markSuperRegs(Reserved, RISCVABI::getBPReg()); // b
[all...] |
| /src/sys/external/bsd/gnu-efi/dist/inc/ |
| pci22.h | 58 UINT32 Reserved[2];
87 UINT32 Reserved;
122 UINT8 Reserved[4];
130 UINT32 Reserved: 7;
157 UINT8 Reserved[0x16];
168 UINT8 Reserved[0x0A];
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFRegisterInfo.cpp | 38 BitVector Reserved(getNumRegs());
39 markSuperRegs(Reserved, BPF::W10); // [W|R]10 is read only frame pointer
40 markSuperRegs(Reserved, BPF::W11); // [W|R]11 is pseudo stack pointer
41 return Reserved;
|
| /src/sys/dev/ic/ |
| mpt_mpilib.h | 208 /* Note: The major versions of 0xe0 through 0xff are reserved */
337 * 0x80 -> 0x8F reserved for private message use per product
462 U8 Reserved;
473 U8 Reserved;
484 U8 Reserved;
495 U8 Reserved;
506 U8 Reserved;
653 U8 Reserved[2]; /* function specific */
669 U8 Reserved[2]; /* function specific */
919 * and removed a one byte reserved field
[all...] |
| /src/sys/external/bsd/gnu-efi/dist/inc/ia64/ |
| salproc.h | 69 // Reserved
138 UINT8 Reserved[7];
155 UINT8 Reserved[7];
168 UINT8 Reserved;
185 UINT8 Reserved[14];
192 UINT8 Reserved[5];
205 UINT8 Reserved[3];
213 UINT8 Reserved[6];
229 UINT8 Reserved;
|
| /src/crypto/external/apache2/openssl/dist/providers/ |
| stores.inc | 2 * Copyright 2020 The OpenSSL Project Authors. All Rights Reserved.
|
| /src/crypto/external/bsd/openssl/dist/providers/ |
| stores.inc | 2 * Copyright 2020 The OpenSSL Project Authors. All Rights Reserved.
|
| /src/crypto/external/bsd/openssl.old/dist/fuzz/ |
| rand.inc | 2 * Copyright 2016 The OpenSSL Project Authors. All Rights Reserved.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCRegisterInfo.cpp | 140 BitVector Reserved(getNumRegs());
142 Reserved.set(ARC::ILINK);
143 Reserved.set(ARC::SP);
144 Reserved.set(ARC::GP);
145 Reserved.set(ARC::R25);
146 Reserved.set(ARC::BLINK);
147 Reserved.set(ARC::FP);
148 return Reserved;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 530 BitVector Reserved(getNumRegs());
533 // Set the floating point control register as reserved.
534 Reserved.set(X86::FPCW);
536 // Set the floating point status register as reserved.
537 Reserved.set(X86::FPSW);
539 // Set the SIMD floating point control register as reserved.
540 Reserved.set(X86::MXCSR);
542 // Set the stack-pointer register and its aliases as reserved.
544 Reserved.set(SubReg);
546 // Set the Shadow Stack Pointer as reserved
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| smu8.h | 45 uint32_t Reserved[20];
|
