| /src/external/bsd/jemalloc/include/jemalloc/internal/ |
| size_classes.h | 13 * SIZE_CLASSES: Complete table of SC(index, lg_grp, lg_delta, ndelta, psz,
60 SC( 0, 3, 3, 0, no, yes, 1, 3) \
61 SC( 1, 3, 3, 1, no, yes, 1, 3) \
62 SC( 2, 3, 3, 2, no, yes, 3, 3) \
63 SC( 3, 3, 3, 3, no, yes, 1, 3) \
65 SC( 4, 5, 3, 1, no, yes, 5, 3) \
66 SC( 5, 5, 3, 2, no, yes, 3, 3) \
67 SC( 6, 5, 3, 3, no, yes, 7, 3) \
68 SC( 7, 5, 3, 4, no, yes, 1, 3) \
70 SC( 8, 6, 4, 1, no, yes, 5, 4)
[all...] |
| /src/external/bsd/jemalloc.old/include/jemalloc/internal/ |
| size_classes.h | 13 * SIZE_CLASSES: Complete table of SC(index, lg_grp, lg_delta, ndelta, psz,
60 SC( 0, 3, 3, 0, no, yes, 1, 3) \
61 SC( 1, 3, 3, 1, no, yes, 1, 3) \
62 SC( 2, 3, 3, 2, no, yes, 3, 3) \
63 SC( 3, 3, 3, 3, no, yes, 1, 3) \
65 SC( 4, 5, 3, 1, no, yes, 5, 3) \
66 SC( 5, 5, 3, 2, no, yes, 3, 3) \
67 SC( 6, 5, 3, 3, no, yes, 7, 3) \
68 SC( 7, 5, 3, 4, no, yes, 1, 3) \
70 SC( 8, 6, 4, 1, no, yes, 5, 4)
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/llvm-xray/ |
| llvm-xray.cpp | 30 for (auto *SC : cl::getRegisteredSubcommands()) {
31 if (*SC) {
34 if (SC == &*cl::TopLevelSubCommand) {
38 if (auto C = dispatch(SC)) {
|
| xray-registry.cpp | 24 CommandRegistration::CommandRegistration(cl::SubCommand *SC,
26 assert(Commands->count(SC) == 0 &&
29 (*Commands)[SC] = Command;
32 HandlerType dispatch(cl::SubCommand *SC) {
33 auto It = Commands->find(SC);
|
| xray-registry.h | 22 // and associates it with |SC|. This requires that a command has not been
23 // registered to a given |SC|.
31 CommandRegistration(cl::SubCommand *SC, std::function<Error()> Command);
34 // Requires that |SC| is not null and has an associated function to it.
35 std::function<Error()> dispatch(cl::SubCommand *SC);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZHazardRecognizer.cpp | 47 const MCSchedClassDesc *SC = getSchedClass(SU);
48 if (!SC->isValid())
51 assert((SC->NumMicroOps != 2 || (SC->BeginGroup && !SC->EndGroup)) &&
53 assert((SC->NumMicroOps < 3 || (SC->BeginGroup && SC->EndGroup)) &&
55 assert((SC->NumMicroOps < 3 || (SC->NumMicroOps % 3 == 0)) &
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 103 const MCSchedClassDesc *SC = nullptr) const;
106 const MCSchedClassDesc *SC = nullptr) const;
110 const MCSchedClassDesc *SC = nullptr) const;
134 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const {
136 return STI->getWriteProcResBegin(SC);
138 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const {
139 return STI->getWriteProcResEnd(SC);
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-pdbutil/ |
| FormatUtil.cpp | 193 using SC = COFF::SectionCharacteristics;
199 PUSH_CHARACTERISTIC_FLAG(SC, IMAGE_SCN_TYPE_NOLOAD, C, Style, "noload");
200 PUSH_CHARACTERISTIC_FLAG(SC, IMAGE_SCN_TYPE_NO_PAD, C, Style, "no padding");
201 PUSH_CHARACTERISTIC_FLAG(SC, IMAGE_SCN_CNT_CODE, C, Style, "code");
202 PUSH_CHARACTERISTIC_FLAG(SC, IMAGE_SCN_CNT_INITIALIZED_DATA, C, Style,
204 PUSH_CHARACTERISTIC_FLAG(SC, IMAGE_SCN_CNT_UNINITIALIZED_DATA, C, Style,
206 PUSH_CHARACTERISTIC_FLAG(SC, IMAGE_SCN_LNK_OTHER, C, Style, "other");
207 PUSH_CHARACTERISTIC_FLAG(SC, IMAGE_SCN_LNK_INFO, C, Style, "info");
208 PUSH_CHARACTERISTIC_FLAG(SC, IMAGE_SCN_LNK_REMOVE, C, Style, "remove");
209 PUSH_CHARACTERISTIC_FLAG(SC, IMAGE_SCN_LNK_COMDAT, C, Style, "comdat")
[all...] |
| InputFile.cpp | 144 if (!SC.hasChecksums() || !SC.hasStrings())
145 SC.initialize(SS);
150 if (SC.hasChecksums() && SC.hasStrings())
170 if (!SC.hasStrings()) {
173 SC.setStrings(StringTable->getStringTable());
178 SC.resetChecksums();
187 SC.initialize(Subsections);
192 if (!SC.hasChecksums()
[all...] |
| /src/sys/arch/sgimips/dev/ |
| scnvar.h | 77 #define SCN_OP_BIS(SC,VAL) ((SC)->sc_duart->base[DU_OPSET] = (VAL))
78 #define SCN_OP_BIC(SC,VAL) ((SC)->sc_duart->base[DU_OPCLR] = (VAL))
80 #define SCN_DCD(SC) (((SC)->sc_duart->base[DU_IP] & (SC)->sc_ip_dcd) == 0)
91 struct scn_softc *sc; member in struct:duart::chan
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| MCSubtargetInfo.h | 167 const MCSchedClassDesc *SC) const {
168 return &WriteProcResTable[SC->WriteProcResIdx];
171 const MCSchedClassDesc *SC) const {
172 return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
175 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
177 assert(DefIdx < SC->NumWriteLatencyEntries &&
180 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
183 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
188 for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx]
[all...] |
| MCSymbolXCOFF.h | 37 void setStorageClass(XCOFF::StorageClass SC) {
38 StorageClass = SC;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/ObjectYAML/ |
| CodeViewYAMLDebugSections.h | 112 fromCodeViewSubection(const codeview::StringsAndChecksumsRef &SC,
123 const codeview::StringsAndChecksums &SC);
126 fromDebugS(ArrayRef<uint8_t> Data, const codeview::StringsAndChecksumsRef &SC);
129 codeview::StringsAndChecksums &SC);
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| rl78-decode.opc | 124 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
222 ID(add); DR(A); SC(IMMU(1)); Fzac;
234 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
254 ID(addc); DR(A); SC(IMMU(1)); Fzac;
266 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
277 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
286 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
306 ID(and); DR(A); SC(IMMU(1)); Fz;
318 ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
444 ID(mov); DM(None, IMMU(2)); DB(bit); SC(0)
[all...] |
| msp430-decode.opc | 86 #define SC(c) OP (1, MSP430_Operand_Immediate, 0, c)
203 SC (0);
222 SC (1);
234 SC (4);
237 SC (2);
254 SC (x);
258 SC (8);
261 SC (-1);
432 PC+X *as* the address. So we use SC to use the address, not the
434 ID (MSO_jmp); SC (pc + raddr + msp430->n_bytes)
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| rl78-decode.opc | 124 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
222 ID(add); DR(A); SC(IMMU(1)); Fzac;
234 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
254 ID(addc); DR(A); SC(IMMU(1)); Fzac;
266 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
277 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
286 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
306 ID(and); DR(A); SC(IMMU(1)); Fz;
318 ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
444 ID(mov); DM(None, IMMU(2)); DB(bit); SC(0)
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| rl78-decode.opc | 124 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
222 ID(add); DR(A); SC(IMMU(1)); Fzac;
234 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
254 ID(addc); DR(A); SC(IMMU(1)); Fzac;
266 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
277 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
286 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
306 ID(and); DR(A); SC(IMMU(1)); Fz;
318 ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
444 ID(mov); DM(None, IMMU(2)); DB(bit); SC(0)
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| rl78-decode.opc | 124 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
222 ID(add); DR(A); SC(IMMU(1)); Fzac;
234 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
254 ID(addc); DR(A); SC(IMMU(1)); Fzac;
266 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
277 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
286 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
306 ID(and); DR(A); SC(IMMU(1)); Fz;
318 ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
444 ID(mov); DM(None, IMMU(2)); DB(bit); SC(0)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 86 const MCSchedClassDesc *SC) const {
88 if (!SC)
89 SC = resolveSchedClass(MI);
90 if (SC->isValid())
91 return SC->BeginGroup;
97 const MCSchedClassDesc *SC) const {
99 if (!SC)
100 SC = resolveSchedClass(MI);
101 if (SC->isValid())
102 return SC->EndGroup
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| VarBypassDetector.cpp | 117 if (const SwitchCase *SC = dyn_cast<SwitchCase>(SubStmt))
118 Next = SC->getSubStmt();
144 for (const SwitchCase *SC = SS->getSwitchCaseList(); SC;
145 SC = SC->getNextSwitchCase()) {
146 Detect(from, ToScopes[SC]);
|
| /src/lib/libc/arch/sparc/gen/ |
| divrem.m4 | 92 define(SC, `%g5')
170 ! The number of bits in the result here is N*ITER+SC, where SC <= N.
176 mov 1, SC
181 ! Now compute SC.
184 inc SC
193 dec SC
205 ! dec SC
215 deccc SC
235 deccc SC
[all...] |
| /src/sys/lib/libkern/arch/sparc/ |
| divrem.m4 | 92 define(SC, `%g5')
170 ! The number of bits in the result here is N*ITER+SC, where SC <= N.
176 mov 1, SC
181 ! Now compute SC.
184 inc SC
193 dec SC
205 ! dec SC
215 deccc SC
235 deccc SC
[all...] |
| /src/sys/lib/libkern/arch/sparc64/ |
| divrem.m4 | 96 define(SC, `%g5')
171 ! The number of bits in the result here is N*ITER+SC, where SC <= N.
177 mov 1, SC
182 ! Now compute SC.
185 inc SC
194 dec SC
206 ! dec SC
216 deccc SC
236 deccc SC
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/ObjectYAML/ |
| CodeViewYAMLDebugSections.cpp | 94 const codeview::StringsAndChecksums &SC) const = 0;
112 const codeview::StringsAndChecksums &SC) const override;
126 const codeview::StringsAndChecksums &SC) const override;
142 const codeview::StringsAndChecksums &SC) const override;
158 const codeview::StringsAndChecksums &SC) const override;
172 const codeview::StringsAndChecksums &SC) const override;
186 const codeview::StringsAndChecksums &SC) const override;
200 const codeview::StringsAndChecksums &SC) const override;
214 const codeview::StringsAndChecksums &SC) const override;
229 const codeview::StringsAndChecksums &SC) const override
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| ScalarEvolutionExpressions.h | 567 template<typename SC, typename RetVal=void>
572 return ((SC*)this)->visitConstant((const SCEVConstant*)S);
574 return ((SC *)this)->visitPtrToIntExpr((const SCEVPtrToIntExpr *)S);
576 return ((SC*)this)->visitTruncateExpr((const SCEVTruncateExpr*)S);
578 return ((SC*)this)->visitZeroExtendExpr((const SCEVZeroExtendExpr*)S);
580 return ((SC*)this)->visitSignExtendExpr((const SCEVSignExtendExpr*)S);
582 return ((SC*)this)->visitAddExpr((const SCEVAddExpr*)S);
584 return ((SC*)this)->visitMulExpr((const SCEVMulExpr*)S);
586 return ((SC*)this)->visitUDivExpr((const SCEVUDivExpr*)S);
588 return ((SC*)this)->visitAddRecExpr((const SCEVAddRecExpr*)S)
[all...] |
