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  /src/sys/dev/microcode/aic7xxx/
aic7xxx.seq 1088 mov SCB_RESIDUAL_DATACNT[3], SHADDR;
1166 * Reload HADDR from SHADDR and setup the
1170 bmov HADDR, SHADDR, 4;
1175 mvi SHADDR call bcopy_4;
1730 * we can only ack the message after SHADDR has been saved. On these
1731 * chips, SHADDR increments with every bus transaction, even PIO.
1758 * and the SCB_DATAPTR becomes the current SHADDR.
1763 bmov SCB_DATAPTR, SHADDR, 4;
1770 mvi SHADDR call bcopy_4;
aic7xxx.reg 416 * manner as STCNT is counted down. SHADDR should always be used
420 register SHADDR {
aic7xxx_reg.h 187 ahc_print_register(NULL, 0, "SHADDR", 0x14, regvalue, cur_col, wrap)
1228 #define SHADDR 0x14
aic79xx.seq 1157 * The SCB_DATAPTR becomes the current SHADDR.
1161 bmov SCB_DATAPTR, SHADDR, 8;
aic79xx.reg 2438 register SHADDR {
aic79xx_reg.h 859 ahd_print_register(NULL, 0, "SHADDR", 0x60, regvalue, cur_col, wrap)
3004 #define SHADDR 0x60
  /src/sys/dev/ic/
aic7xxx.c 3615 data_addr = (ahc_inb(ahc, SHADDR + 3) << 24)
3616 | (ahc_inb(ahc, SHADDR + 2) << 16)
3617 | (ahc_inb(ahc, SHADDR + 1) << 8)
3618 | (ahc_inb(ahc, SHADDR));
aic79xx.c 693 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
4805 data_addr = ahd_inq(ahd, SHADDR);
8821 ahd_inl(ahd, SHADDR+4),
8822 ahd_inl(ahd, SHADDR),

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