| /src/sys/arch/arm/nxp/ |
| imx6_ccmvar.h | 195 #define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \
203 .mask = (CCM_ANALOG_##_reg##_##_mask), \
210 #define CLK_DIV(_name, _parent, _reg, _mask) { \
219 .mask = (CCM_##_reg##_##_mask), \
224 #define CLK_DIV_BUSY(_name, _parent, _reg, _mask, _busy_reg, _busy_mask) { \
233 .mask = (CCM_##_reg##_##_mask), \
240 #define CLK_DIV_TABLE(_name, _parent, _reg, _mask, _tbl) { \
249 .mask = (CCM_ANALOG_##_reg##_##_mask), \
255 #define CLK_MUX(_name, _parents, _base, _reg, _mask) { \
263 .mask = (_base##_##_reg##_##_mask), \
[all...] |
| imx_ccm.h | 87 #define IMX_GATE(_id, _name, _pname, _reg, _mask) \
88 IMX_GATE_INDEX(_id, 0, _name, _pname, _reg, _mask)
89 #define IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, _mask) \
98 .u.gate.mask = (_mask), \
268 #define IMX_DIV(_id, _name, _parent, _reg, _mask, _flags) \
269 IMX_DIV_INDEX(_id, 0, _name, _parent, _reg, _mask, _flags)
270 #define IMX_DIV_INDEX(_id, _regidx, _name, _parent, _reg, _mask, _flags) \
279 .u.div.mask = (_mask), \
|
| imx7d_ccm.c | 101 #define ANATOP_MUX(_id, _name, _parents, _reg, _mask) \
102 IMX_MUX_INDEX(_id, REGIDX_ANATOP, _name, _parents, _reg, _mask)
103 #define ANATOP_GATE(_id, _name, _parent, _reg, _mask) \
104 IMX_GATE_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _mask)
|
| /src/external/bsd/wpa/dist/src/common/ |
| dragonfly.h | 28 struct crypto_bignum *_mask,
|
| dragonfly.c | 196 struct crypto_bignum *_mask,
205 dragonfly_get_rand_2_to_r_1(_mask, order) &&
206 crypto_bignum_add(_rand, _mask, scalar) == 0 &&
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| generic_regs.h | 35 .type ## _mask = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## _MASK,\
|
| ddc_regs.h | 38 .type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\
61 .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
78 .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\
|
| hpd_regs.h | 43 .type ## _mask = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\
|
| amdgpu_hw_gpio.c | 40 gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask
|
| /src/external/lgpl3/mpfr/dist/src/ |
| mpfr-gmp.h | 481 mp_limb_t _q0, _t1, _t0, _mask; \
494 _mask = - (mp_limb_t) ((r1) >= _q0); \
495 (q) += _mask; \
496 add_ssaaaa ((r1), (r0), (r1), (r0), _mask & (d1), _mask & (d0)); \
516 mp_limb_t _v, _p, _t1, _t0, _mask; \
523 _mask = -(mp_limb_t) (_p >= (d1)); \
525 _v += _mask; \
526 _p -= _mask & (d1); \
549 mp_limb_t _qh, _ql, _r, _mask; \
[all...] |
| mpfr-impl.h | 1822 mp_limb_t _mask; \
1830 _mask = MPFR_LIMB_ONE << (_sh - 1); \
1831 _rb = _sp[0] & _mask; \
1832 _sb = _sp[0] & (_mask - 1); \
1841 _ulp = 2 * _mask; \
|
| /src/sys/external/mit/xen-include-public/dist/xen/include/public/io/ |
| ring.h | 384 static inline RING_IDX name##_mask(RING_IDX idx, RING_IDX ring_size) \
393 return buf + name##_mask(idx, ring_size); \
411 *masked_cons = name##_mask(*masked_cons + size, ring_size); \
429 *masked_prod = name##_mask(*masked_prod + size, ring_size); \
441 prod = name##_mask(prod, ring_size); \
442 cons = name##_mask(cons, ring_size); \
|
| /src/sys/arch/powerpc/marvell/ |
| pic_discovery.c | 64 } _mask; member in struct:discovery_pic_ops
65 #define enable_mask _mask.mask64
66 #define enable_mask_high _mask.mask32[1]
67 #define enable_mask_low _mask.mask32[0]
|
| /src/external/lgpl3/gmp/dist/mpn/generic/ |
| div_qr_2.c | 119 mp_limb_t _mask; \
137 _mask = -(mp_limb_t) ((r1 >= _q1) & ((r1 > _q1) | (r0 >= _q0))); /* (r1,r0) >= (q1,q0) */ \
138 add_ssaaaa (r1, r0, r1, r0, d1 & _mask, d0 & _mask); \
139 sub_ddmmss (_q3, _q2, _q3, _q2, CNST_LIMB(0), -_mask); \
|
| /src/sys/arch/arm/ti/ |
| ti_prcm.h | 146 #define TI_PRCM_HWMOD_MASK(_name, _reg, _mask, _parent, _enable, _flags) \
150 .u.hwmod.mask = (_mask), \
|
| /src/external/bsd/wpa/dist/src/eap_common/ |
| eap_pwd_common.h | 74 struct crypto_bignum *_mask,
|
| eap_pwd_common.c | 494 struct crypto_bignum *_mask,
498 _rand, _mask, scalar);
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru.h | 391 #define RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, _flags) \
400 .u.mux.mask = (_mask), \
405 #define RK_MUX(_id, _name, _parents, _reg, _mask) \
406 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, 0)
407 #define RK_MUXGRF(_id, _name, _parents, _reg, _mask) \
408 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, RK_MUX_GRF)
|
| /src/sys/arch/arm/amlogic/ |
| meson_clk.h | 237 #define MESON_CLK_PLL_REG(_reg, _mask) \
238 { .reg = (_reg), .mask = (_mask) }
|
| /src/external/lgpl3/gmp/dist/ |
| gmp-impl.h | 3070 mp_limb_t _v, _p, _t1, _t0, _mask; \
3077 _mask = -(mp_limb_t) (_p >= (d1)); \
3079 _v += _mask; \
3080 _p -= _mask & (d1); \
3120 mp_limb_t _qh, _ql, _r, _mask; \
3126 _mask = -(mp_limb_t) (_r > _ql); /* both > and >= are OK */ \
3127 _qh += _mask; \
3128 _r += _mask & (d); \
3134 _mask = -(mp_limb_t) (_r > _ql); /* both > and >= are OK */ \
3135 _qh += _mask; \
[all...] |
| /src/external/gpl3/gcc.old/dist/libgcc/config/tilepro/ |
| atomic.h | 190 The _mask, _addend, and _expr arguments are ignored on tilegx. */
191 #define __arch_atomic_update(mem, value, op, _mask, _addend, _expr) \
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu.h | 326 #define SUNXI_CCU_PHASE(_id, _name, _parent, _reg, _mask) \
332 .u.phase.mask = (_mask), \
|
| /src/sys/arch/riscv/starfive/ |
| jh7110_pinctrl.c | 224 #define JH7110_FS(_reg, _mask, _max) \
228 .jfs_mask = (_mask), \
|
| /src/sys/external/isc/atheros_hal/dist/ |
| ah_internal.h | 339 #define ath_hal_setInterrupts(_ah, _mask) \
340 (_ah)->ah_setInterrupts(_ah, _mask)
|
| /src/external/bsd/file/dist/src/ |
| file.h | 376 uint64_t _mask; /* for use with numeric and date types */ member in union:magic::__anon24
382 #define num_mask _u._mask
|
