| /src/sys/dev/fdt/ |
| syscon.h | 47 #define syscon_read_4(_syscon, _reg) \
48 (_syscon)->read_4((_syscon)->priv, (_reg))
50 #define syscon_write_4(_syscon, _reg, _val) \
51 (_syscon)->write_4((_syscon)->priv, (_reg), (_val))
|
| fdt_regulator.c | 40 #define REGULATOR_TO_RC(_reg) \
41 container_of((_reg), struct fdtbus_regulator_controller, rc_reg)
|
| /src/sys/external/isc/atheros_hal/ic/ |
| ah_osdep.h | 93 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
94 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
112 #define OS_REG_WRITE(_ah, _reg, _val) do { \
113 if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
115 (_reg), (_val)); \
118 (_reg), (_val)); \
120 #define OS_REG_READ(_ah, _reg) \
[all...] |
| /src/sys/arch/arm/nxp/ |
| imx6_ccmvar.h | 183 #define CLK_PFD(_name, _parent, _reg, _index) { \
189 .reg = (CCM_ANALOG_##_reg), \
195 #define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \
202 .reg = (CCM_ANALOG_##_reg), \
203 .mask = (CCM_ANALOG_##_reg##_##_mask), \
204 .powerdown = (CCM_ANALOG_##_reg##_##_powerdown), \
210 #define CLK_DIV(_name, _parent, _reg, _mask) { \
218 .reg = (CCM_##_reg), \
219 .mask = (CCM_##_reg##_##_mask), \
224 #define CLK_DIV_BUSY(_name, _parent, _reg, _mask, _busy_reg, _busy_mask) {
[all...] |
| imx_ccm.h | 87 #define IMX_GATE(_id, _name, _pname, _reg, _mask) \
88 IMX_GATE_INDEX(_id, 0, _name, _pname, _reg, _mask)
89 #define IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, _mask) \
97 .u.gate.reg = (_reg), \
102 #define IMX_ROOT_GATE(_id, _name, _pname, _reg) \
103 IMX_ROOT_GATE_INDEX(_id, 0, _name, _pname, _reg)
104 #define IMX_ROOT_GATE_INDEX(_id, _regidx, _name, _pname, _reg) \
105 IMX_GATE_INDEX(_id, _regidx, _name, _pname, _reg, __BITS(1,0))
124 #define IMX_COMPOSITE(_id, _name, _parents, _reg, _flags) \
125 IMX_COMPOSITE_INDEX(_id, 0, _name, _parents, _reg, _flags
[all...] |
| imx7d_ccm.c | 101 #define ANATOP_MUX(_id, _name, _parents, _reg, _mask) \
102 IMX_MUX_INDEX(_id, REGIDX_ANATOP, _name, _parents, _reg, _mask)
103 #define ANATOP_GATE(_id, _name, _parent, _reg, _mask) \
104 IMX_GATE_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _mask)
105 #define ANATOP_PLL(_id, _name, _parent, _reg, _div_mask, _flags) \
106 IMX_PLL_INDEX(_id, REGIDX_ANATOP, _name, _parent, _reg, _div_mask, _flags)
|
| /src/sys/arch/arm/at91/ |
| at91rm9200reg.h | 198 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOA_BASE + (_reg)))
199 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOA_BASE + (_reg))) = (_val);} while (0)
200 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOB_BASE + (_reg)))
201 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91RM9200_PIOB_BASE + (_reg))) = (_val);} while (0)
202 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91RM9200_PIOC_BASE + (_reg)))
[all...] |
| at91sam9260reg.h | 213 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91SAM9260_PIOA_BASE + (_reg)))
214 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOA_BASE + (_reg))) = (_val);} while (0)
215 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91SAM9260_PIOB_BASE + (_reg)))
216 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9260_PIOB_BASE + (_reg))) = (_val);} while (0)
217 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91SAM9260_PIOC_BASE + (_reg)))
[all...] |
| at91sam9261reg.h | 211 #define PIOA_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg)))
212 #define PIOA_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOA_BASE + (_reg))) = (_val);} while (0)
213 #define PIOB_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg)))
214 #define PIOB_WRITE(_reg, _val) do {*((volatile uint32_t *)(AT91SAM9261_PIOB_BASE + (_reg))) = (_val);} while (0)
215 #define PIOC_READ(_reg) *((volatile uint32_t *)(AT91SAM9261_PIOC_BASE + (_reg)))
[all...] |
| /src/sys/external/isc/atheros_hal/dist/ar5312/ |
| ar5312reg.h | 31 #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val);
32 #define REG_READ(_reg) *((volatile uint32_t *)(_reg))
|
| /src/sys/arch/alpha/tlsb/ |
| tlsbreg.h | 68 #define TLSB_NODE_REG_ADDR(_node, _reg) \
69 KV((long)TLSB_NODE_ADDR((_node)) + (_reg))
72 #define TLSB_GET_NODEREG(_node, _reg) \
73 *(volatile uint32_t *)(TLSB_NODE_REG_ADDR((_node), (_reg)))
74 #define TLSB_PUT_NODEREG(_node, _reg, _val) \
75 *(volatile uint32_t *)(TLSB_NODE_REG_ADDR((_node), (_reg))) = (_val)
83 #define TLSB_BCAST_REG_ADDR(_reg) KV((long)(TLSB_BCASE_BASE + (_reg)))
86 #define TLSB_GET_BCASTREG(_reg) \
87 *(volatile uint32_t *)(TLSB_BCAST_REG_ADDR + (_reg))
[all...] |
| /src/sys/arch/arm/amlogic/ |
| meson_clk.h | 48 #define MESON_CLK_RESET(_id, _reg, _bit) \
50 .reg = (_reg), \
105 #define MESON_CLK_GATE_FLAGS(_id, _name, _pname, _reg, _bit, _flags) \
111 .u.gate.reg = (_reg), \
118 #define MESON_CLK_GATE(_id, _name, _pname, _reg, _bit) \
119 MESON_CLK_GATE_FLAGS(_id, _name, _pname, _reg, _bit, 0)
142 #define MESON_CLK_DIV(_id, _name, _parent, _reg, _div, _flags) \
146 .u.div.reg = (_reg), \
199 #define MESON_CLK_MUX_RATE(_id, _name, _parents, _reg, _sel, \
207 .u.mux.reg = (_reg), \
[all...] |
| /src/sys/arch/arm/ti/ |
| omap4_prcm.c | 130 #define OMAP4_PRCM_HWMOD_CM1_ABE(_name, _reg, _parent) \
131 TI_PRCM_HWMOD((_name), CM1_ABE + (_reg), (_parent), omap4_prcm_hwmod_enable)
132 #define OMAP4_PRCM_HWMOD_CM2_L3INIT(_name, _reg, _parent) \
133 TI_PRCM_HWMOD((_name), CM2_L3INIT + (_reg), (_parent), omap4_prcm_hwmod_enable)
134 #define OMAP4_PRCM_HWMOD_CM2_L3INIT_AUTO(_name, _reg, _parent) \
135 TI_PRCM_HWMOD((_name), CM2_L3INIT + (_reg), (_parent), omap4_prcm_hwmod_enable_auto)
136 #define OMAP4_PRCM_HWMOD_CM2_L4PER(_name, _reg, _parent) \
137 TI_PRCM_HWMOD((_name), CM2_L4PER + (_reg), (_parent), omap4_prcm_hwmod_enable)
138 #define OMAP4_PRCM_HWMOD_CM2_L4PER_AUTO(_name, _reg, _parent) \
139 TI_PRCM_HWMOD((_name), CM2_L4PER + (_reg), (_parent), omap4_prcm_hwmod_enable_auto
[all...] |
| ti_prcm.h | 143 #define TI_PRCM_HWMOD(_name, _reg, _parent, _enable) \
144 TI_PRCM_HWMOD_MASK(_name, _reg, 0, _parent, _enable, 0)
146 #define TI_PRCM_HWMOD_MASK(_name, _reg, _mask, _parent, _enable, _flags) \
149 .u.hwmod.reg = (_reg), \
|
| am3_prcm.c | 129 #define AM3_PRCM_HWMOD_PER(_name, _reg, _parent) \
130 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable)
131 #define AM3_PRCM_HWMOD_PER_DISP(_name, _reg, _parent) \
132 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable_display)
133 #define AM3_PRCM_HWMOD_WKUP(_name, _reg, _parent) \
134 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_WKUP + (_reg), (_parent), am3_prcm_hwmod_enable)
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu.h | 47 #define SUNXI_CCU_RESET(_id, _reg, _bit) \
49 .reg = (_reg), \
81 #define SUNXI_CCU_GATE(_id, _name, _pname, _reg, _bit) \
87 .u.gate.reg = (_reg), \
129 #define SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \
134 .u.nkmp.reg = (_reg), \
150 #define SUNXI_CCU_NKMP(_id, _name, _parent, _reg, _n, _k, _m, \
152 SUNXI_CCU_NKMP_TABLE(_id, _name, _parent, _reg, _n, _k, _m, \
182 #define SUNXI_CCU_NM(_id, _name, _parents, _reg, _n, _m, _sel, \
187 .u.nm.reg = (_reg), \
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| reg.h | 82 #define REG_50080_TO_PIPE(_reg) ({ \
83 typeof(_reg) (reg) = (_reg); \
89 #define REG_50080_TO_PLANE(_reg) ({ \
90 typeof(_reg) (reg) = (_reg); \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| generic_regs.h | 34 .type ## _reg = REG(DC_GPIO_GENERIC_## type),\
|
| ddc_regs.h | 37 .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\
60 .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\
77 .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\
|
| hpd_regs.h | 42 .type ## _reg = REG(DC_GPIO_HPD_## type),\
|
| /src/external/bsd/pcc/dist/pcc/mip/ |
| node.h | 68 int _reg; member in union:node::__anon7944
71 #define n_reg n_3._reg
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru.h | 190 #define RK_ARM(_id, _name, _parents, _reg, _mux_mask, _mux_main, _mux_alt, _div_mask, _rates) \
198 .u.arm.mux_reg = (_reg), \
202 .u.arm.divs[0].reg = (_reg), \
355 #define RK_GATE(_id, _name, _pname, _reg, _bit) \
362 .u.gate.reg = (_reg), \
391 #define RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, _flags) \
399 .u.mux.reg = (_reg), \
405 #define RK_MUX(_id, _name, _parents, _reg, _mask) \
406 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, 0)
407 #define RK_MUXGRF(_id, _name, _parents, _reg, _mask)
[all...] |
| /src/sys/dev/marvell/ |
| if_mvxpevar.h | 335 uint32_t _reg = MVXPE_READ(sc, MVXPE_PRXS(q)); \
338 q, _reg, MVXPE_PRXS_GET_ODC(_reg), \
339 MVXPE_PRXS_GET_NODC(_reg)); \
|
| /src/sys/arch/arm/samsung/ |
| exynos5410_clock.c | 189 #define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \
197 .reg = (_reg), \
203 #define CLK_MUXA(_name, _alias, _reg, _bits, _p) \
204 CLK_MUXF(_name, _alias, _reg, _bits, 0, _p)
206 #define CLK_MUX(_name, _reg, _bits, _p) \
207 CLK_MUXF(_name, NULL, _reg, _bits, 0, _p)
209 #define CLK_DIVF(_name, _parent, _reg, _bits, _f) { \
215 .reg = (_reg), \
221 #define CLK_DIV(_name, _parent, _reg, _bits) \
222 CLK_DIVF(_name, _parent, _reg, _bits, 0
[all...] |
| exynos5422_clock.c | 292 #define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \
300 .reg = (_reg), \
306 #define CLK_MUXA(_name, _alias, _reg, _bits, _p) \
307 CLK_MUXF(_name, _alias, _reg, _bits, 0, _p)
309 #define CLK_MUX(_name, _reg, _bits, _p) \
310 CLK_MUXF(_name, NULL, _reg, _bits, 0, _p)
312 #define CLK_DIV(_name, _parent, _reg, _bits) { \
317 .reg = (_reg), \
323 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \
329 .reg = (_reg), \
[all...] |
