1 /* $NetBSD: if_ure.c,v 1.64 2026/04/18 00:44:32 gutteridge Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.64 2026/04/18 00:44:32 gutteridge Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/cprng.h> 42 43 #include <net/route.h> 44 45 #include <dev/usb/usbnet.h> 46 47 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 48 #ifdef INET6 49 #include <netinet/in.h> 50 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 51 #endif 52 53 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 54 #include <dev/usb/if_urereg.h> 55 #include <dev/usb/if_urevar.h> 56 57 #define URE_PRINTF(un, fmt, args...) \ 58 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 59 60 #define URE_DEBUG 61 #ifdef URE_DEBUG 62 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 63 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 64 int uredebug = 0; 65 #else 66 #define DPRINTF(x) 67 #define DPRINTFN(n, x) 68 #endif 69 70 #define ETHER_IS_ZERO(addr) \ 71 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 72 73 static const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 75 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 }, 76 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_UE300 }, 77 }; 78 79 #define URE_TX_BUFSZ (16 * 1024) 80 #define URE_RX_BUFSZ_16K (16 * 1024) 81 #define URE_RX_BUFSZ_32K (32 * 1024) 82 83 static void ure_reset(struct usbnet *); 84 static uint32_t ure_txcsum(struct mbuf *); 85 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 86 static void ure_rtl8152_init(struct usbnet *); 87 static void ure_rtl8153_init(struct usbnet *); 88 static void ure_disable_teredo(struct usbnet *); 89 static void ure_init_fifo(struct usbnet *); 90 91 static void ure_uno_stop(struct ifnet *, int); 92 static void ure_uno_mcast(struct ifnet *); 93 static int ure_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *); 94 static int ure_uno_mii_write_reg(struct usbnet *, int, int, uint16_t); 95 static void ure_uno_miibus_statchg(struct ifnet *); 96 static unsigned ure_uno_tx_prepare(struct usbnet *, struct mbuf *, 97 struct usbnet_chain *); 98 static void ure_uno_rx_loop(struct usbnet *, struct usbnet_chain *, 99 uint32_t); 100 static int ure_uno_init(struct ifnet *); 101 102 static int ure_match(device_t, cfdata_t, void *); 103 static void ure_attach(device_t, device_t, void *); 104 105 CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 106 usbnet_detach, usbnet_activate); 107 108 static const struct usbnet_ops ure_ops = { 109 .uno_stop = ure_uno_stop, 110 .uno_mcast = ure_uno_mcast, 111 .uno_read_reg = ure_uno_mii_read_reg, 112 .uno_write_reg = ure_uno_mii_write_reg, 113 .uno_statchg = ure_uno_miibus_statchg, 114 .uno_tx_prepare = ure_uno_tx_prepare, 115 .uno_rx_loop = ure_uno_rx_loop, 116 .uno_init = ure_uno_init, 117 }; 118 119 static int 120 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 121 void *buf, int len) 122 { 123 usb_device_request_t req; 124 usbd_status err; 125 126 if (usbnet_isdying(un)) 127 return 0; 128 129 if (rw == URE_CTL_WRITE) 130 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 131 else 132 req.bmRequestType = UT_READ_VENDOR_DEVICE; 133 req.bRequest = UR_SET_ADDRESS; 134 USETW(req.wValue, val); 135 USETW(req.wIndex, index); 136 USETW(req.wLength, len); 137 138 DPRINTFN(5, ("ure_ctl: rw %d, val %04hu, index %04hu, len %d\n", 139 rw, val, index, len)); 140 err = usbd_do_request(un->un_udev, &req, buf); 141 if (err) { 142 DPRINTF(("ure_ctl: error %d\n", err)); 143 if (rw == URE_CTL_READ) 144 memset(buf, 0, len); 145 return -1; 146 } 147 148 return 0; 149 } 150 151 static int 152 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 153 void *buf, int len) 154 { 155 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 156 } 157 158 static int 159 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 160 void *buf, int len) 161 { 162 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 163 } 164 165 static uint8_t 166 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 167 { 168 uint32_t val; 169 uint8_t temp[4]; 170 uint8_t shift; 171 172 shift = (reg & 3) << 3; 173 reg &= ~3; 174 175 ure_read_mem(un, reg, index, &temp, 4); 176 val = UGETDW(temp); 177 val >>= shift; 178 179 return val & 0xff; 180 } 181 182 static uint16_t 183 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 184 { 185 uint32_t val; 186 uint8_t temp[4]; 187 uint8_t shift; 188 189 shift = (reg & 2) << 3; 190 reg &= ~3; 191 192 ure_read_mem(un, reg, index, &temp, 4); 193 val = UGETDW(temp); 194 val >>= shift; 195 196 return val & 0xffff; 197 } 198 199 static uint32_t 200 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 201 { 202 uint8_t temp[4]; 203 204 ure_read_mem(un, reg, index, &temp, 4); 205 return UGETDW(temp); 206 } 207 208 static int 209 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 210 { 211 uint16_t byen; 212 uint8_t temp[4]; 213 uint8_t shift; 214 215 byen = URE_BYTE_EN_BYTE; 216 shift = reg & 3; 217 val &= 0xff; 218 219 if (reg & 3) { 220 byen <<= shift; 221 val <<= (shift << 3); 222 reg &= ~3; 223 } 224 225 USETDW(temp, val); 226 return ure_write_mem(un, reg, index | byen, &temp, 4); 227 } 228 229 static int 230 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 231 { 232 uint16_t byen; 233 uint8_t temp[4]; 234 uint8_t shift; 235 236 byen = URE_BYTE_EN_WORD; 237 shift = reg & 2; 238 val &= 0xffff; 239 240 if (reg & 2) { 241 byen <<= shift; 242 val <<= (shift << 3); 243 reg &= ~3; 244 } 245 246 USETDW(temp, val); 247 return ure_write_mem(un, reg, index | byen, &temp, 4); 248 } 249 250 static int 251 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 252 { 253 uint8_t temp[4]; 254 255 USETDW(temp, val); 256 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 257 } 258 259 static uint16_t 260 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 261 { 262 uint16_t reg; 263 264 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 265 reg = (addr & 0x0fff) | 0xb000; 266 267 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 268 } 269 270 static void 271 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 272 { 273 uint16_t reg; 274 275 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 276 reg = (addr & 0x0fff) | 0xb000; 277 278 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 279 } 280 281 static int 282 ure_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 283 { 284 285 if (un->un_phyno != phy) { 286 *val = 0; 287 return EINVAL; 288 } 289 290 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 291 if (reg == RTK_GMEDIASTAT) { 292 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 293 return USBD_NORMAL_COMPLETION; 294 } 295 296 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 297 298 return 0; 299 } 300 301 static int 302 ure_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 303 { 304 305 if (un->un_phyno != phy) 306 return EINVAL; 307 308 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 309 310 return 0; 311 } 312 313 static void 314 ure_uno_miibus_statchg(struct ifnet *ifp) 315 { 316 struct usbnet * const un = ifp->if_softc; 317 struct mii_data * const mii = usbnet_mii(un); 318 319 if (usbnet_isdying(un)) 320 return; 321 322 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 323 (IFM_ACTIVE | IFM_AVALID)) { 324 switch (IFM_SUBTYPE(mii->mii_media_active)) { 325 case IFM_10_T: 326 case IFM_100_TX: 327 usbnet_set_link(un, true); 328 break; 329 case IFM_1000_T: 330 if ((un->un_flags & URE_FLAG_8152) != 0) 331 break; 332 usbnet_set_link(un, true); 333 break; 334 default: 335 break; 336 } 337 } 338 } 339 340 static void 341 ure_uno_mcast(struct ifnet *ifp) 342 { 343 struct usbnet *un = ifp->if_softc; 344 struct ethercom *ec = usbnet_ec(un); 345 struct ether_multi *enm; 346 struct ether_multistep step; 347 uint32_t mchash[2] = { 0, 0 }; 348 uint32_t h = 0, rxmode; 349 350 if (usbnet_isdying(un)) 351 return; 352 353 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 354 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 355 /* continue to accept my own DA and bcast frames */ 356 357 ETHER_LOCK(ec); 358 if (usbnet_ispromisc(un)) { 359 ec->ec_flags |= ETHER_F_ALLMULTI; 360 ETHER_UNLOCK(ec); 361 /* run promisc. mode */ 362 rxmode |= URE_RCR_AM; /* ??? */ 363 rxmode |= URE_RCR_AAP; 364 mchash[0] = mchash[1] = 0xffffffff; 365 goto update; 366 } 367 ec->ec_flags &= ~ETHER_F_ALLMULTI; 368 ETHER_FIRST_MULTI(step, ec, enm); 369 while (enm != NULL) { 370 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 371 ec->ec_flags |= ETHER_F_ALLMULTI; 372 ETHER_UNLOCK(ec); 373 /* accept all mcast frames */ 374 rxmode |= URE_RCR_AM; 375 mchash[0] = mchash[1] = ~0U; /* necessary ?? */ 376 goto update; 377 } 378 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 379 mchash[h >> 31] |= 1U << ((h >> 26) & 0x1f); 380 ETHER_NEXT_MULTI(step, enm); 381 } 382 ETHER_UNLOCK(ec); 383 if (h != 0) { 384 rxmode |= URE_RCR_AM; /* activate mcast hash filter */ 385 h = bswap32(mchash[0]); 386 mchash[0] = bswap32(mchash[1]); 387 mchash[1] = h; 388 } 389 update: 390 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, mchash[0]); 391 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, mchash[1]); 392 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 393 } 394 395 static void 396 ure_reset(struct usbnet *un) 397 { 398 int i; 399 400 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 401 402 for (i = 0; i < URE_TIMEOUT; i++) { 403 if (usbnet_isdying(un)) 404 return; 405 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 406 URE_CR_RST)) 407 break; 408 usbd_delay_ms(un->un_udev, 10); 409 } 410 if (i == URE_TIMEOUT) 411 URE_PRINTF(un, "reset never completed\n"); 412 } 413 414 static int 415 ure_uno_init(struct ifnet *ifp) 416 { 417 struct usbnet * const un = ifp->if_softc; 418 uint8_t eaddr[8]; 419 420 /* Set MAC address. */ 421 memset(eaddr, 0, sizeof(eaddr)); 422 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 423 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 424 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 425 eaddr, 8); 426 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 427 428 /* Reset the packet filter. */ 429 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 430 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 431 ~URE_FMC_FCR_MCU_EN); 432 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 433 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 434 URE_FMC_FCR_MCU_EN); 435 436 /* Enable transmit and receive. */ 437 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 438 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 439 URE_CR_TE); 440 441 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 442 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 443 ~URE_RXDY_GATED_EN); 444 445 return 0; 446 } 447 448 static void 449 ure_uno_stop(struct ifnet *ifp, int disable __unused) 450 { 451 struct usbnet * const un = ifp->if_softc; 452 453 ure_reset(un); 454 } 455 456 static void 457 ure_rtl8152_init(struct usbnet *un) 458 { 459 uint32_t pwrctrl; 460 461 /* Disable ALDPS. */ 462 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 463 URE_DIS_SDSAVE); 464 usbd_delay_ms(un->un_udev, 20); 465 466 if (un->un_flags & URE_FLAG_VER_4C00) { 467 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 468 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 469 ~URE_LED_MODE_MASK); 470 } 471 472 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 473 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 474 ~URE_POWER_CUT); 475 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 476 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 477 ~URE_RESUME_INDICATE); 478 479 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 480 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 481 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 482 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 483 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 484 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 485 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 486 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 487 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 488 URE_SPDWN_LINKCHG_MSK); 489 490 /* Enable Rx aggregation. */ 491 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 492 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 493 ~URE_RX_AGG_DISABLE); 494 495 /* Disable ALDPS. */ 496 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 497 URE_DIS_SDSAVE); 498 usbd_delay_ms(un->un_udev, 20); 499 500 ure_init_fifo(un); 501 502 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 503 URE_TX_AGG_MAX_THRESHOLD); 504 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 505 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 506 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 507 } 508 509 static void 510 ure_rtl8153_init(struct usbnet *un) 511 { 512 uint16_t val; 513 uint8_t u1u2[8]; 514 int i; 515 516 /* Disable ALDPS. */ 517 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 518 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 519 usbd_delay_ms(un->un_udev, 20); 520 521 memset(u1u2, 0x00, sizeof(u1u2)); 522 ure_write_mem(un, URE_USB_TOLERANCE, 523 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 524 525 for (i = 0; i < URE_TIMEOUT; i++) { 526 if (usbnet_isdying(un)) 527 return; 528 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 529 URE_AUTOLOAD_DONE) 530 break; 531 usbd_delay_ms(un->un_udev, 10); 532 } 533 if (i == URE_TIMEOUT) 534 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 535 536 for (i = 0; i < URE_TIMEOUT; i++) { 537 if (usbnet_isdying(un)) 538 return; 539 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 540 URE_PHY_STAT_MASK; 541 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 542 break; 543 usbd_delay_ms(un->un_udev, 10); 544 } 545 if (i == URE_TIMEOUT) 546 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 547 548 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 549 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 550 ~URE_U2P3_ENABLE); 551 552 if (un->un_flags & URE_FLAG_VER_5C10) { 553 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 554 val &= ~URE_PWD_DN_SCALE_MASK; 555 val |= URE_PWD_DN_SCALE(96); 556 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 557 558 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 559 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 560 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 561 } else if (un->un_flags & URE_FLAG_VER_5C20) { 562 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 563 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 564 ~URE_ECM_ALDPS); 565 } 566 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 567 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 568 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 569 0) 570 val &= ~URE_DYNAMIC_BURST; 571 else 572 val |= URE_DYNAMIC_BURST; 573 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 574 } 575 576 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 577 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 578 URE_EP4_FULL_FC); 579 580 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 581 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 582 ~URE_TIMER11_EN); 583 584 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 585 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 586 ~URE_LED_MODE_MASK); 587 588 if ((un->un_flags & URE_FLAG_VER_5C10) && 589 un->un_udev->ud_speed < USB_SPEED_SUPER) 590 val = URE_LPM_TIMER_500MS; 591 else 592 val = URE_LPM_TIMER_500US; 593 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 594 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 595 596 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 597 val &= ~URE_SEN_VAL_MASK; 598 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 599 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 600 601 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 602 603 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 604 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 605 ~(URE_PWR_EN | URE_PHASE2_EN)); 606 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 607 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 608 ~URE_PCUT_STATUS); 609 610 memset(u1u2, 0xff, sizeof(u1u2)); 611 ure_write_mem(un, URE_USB_TOLERANCE, 612 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 613 614 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 615 URE_ALDPS_SPDWN_RATIO); 616 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 617 URE_EEE_SPDWN_RATIO); 618 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 619 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 620 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 621 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 622 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 623 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 624 URE_EEE_SPDWN_EN); 625 626 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 627 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 628 val |= URE_U2P3_ENABLE; 629 else 630 val &= ~URE_U2P3_ENABLE; 631 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 632 633 memset(u1u2, 0x00, sizeof(u1u2)); 634 ure_write_mem(un, URE_USB_TOLERANCE, 635 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 636 637 /* Disable ALDPS. */ 638 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 639 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 640 usbd_delay_ms(un->un_udev, 20); 641 642 ure_init_fifo(un); 643 644 /* Enable Rx aggregation. */ 645 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 646 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 647 ~URE_RX_AGG_DISABLE); 648 649 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 650 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 651 val |= URE_U2P3_ENABLE; 652 else 653 val &= ~URE_U2P3_ENABLE; 654 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 655 656 memset(u1u2, 0xff, sizeof(u1u2)); 657 ure_write_mem(un, URE_USB_TOLERANCE, 658 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 659 } 660 661 static void 662 ure_disable_teredo(struct usbnet *un) 663 { 664 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 665 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 666 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 667 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 668 URE_WDT6_SET_MODE); 669 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 670 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 671 } 672 673 static void 674 ure_init_fifo(struct usbnet *un) 675 { 676 uint32_t rxmode, rx_fifo1, rx_fifo2; 677 int i; 678 679 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 680 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 681 URE_RXDY_GATED_EN); 682 683 ure_disable_teredo(un); 684 685 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 686 rxmode &= ~URE_RCR_ACPT_ALL; 687 rxmode |= URE_RCR_APM | URE_RCR_AB; /* accept my own DA and bcast */ 688 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 689 690 if (!(un->un_flags & URE_FLAG_8152)) { 691 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 692 URE_FLAG_VER_5C20)) 693 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 694 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 695 if (un->un_flags & URE_FLAG_VER_5C00) 696 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 697 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 698 ~URE_CTAP_SHORT_EN); 699 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 700 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 701 URE_EEE_CLKDIV_EN); 702 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 703 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 704 URE_EN_10M_BGOFF); 705 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 706 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 707 URE_EN_10M_PLLOFF); 708 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 709 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 710 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 711 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 712 URE_PFM_PWM_SWITCH); 713 714 /* Enable LPF corner auto tune. */ 715 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 716 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 717 718 /* Adjust 10M amplitude. */ 719 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 720 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 721 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 722 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 723 } 724 725 ure_reset(un); 726 727 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 728 729 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 730 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 731 ~URE_NOW_IS_OOB); 732 733 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 734 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 735 ~URE_MCU_BORW_EN); 736 for (i = 0; i < URE_TIMEOUT; i++) { 737 if (usbnet_isdying(un)) 738 return; 739 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 740 URE_LINK_LIST_READY) 741 break; 742 usbd_delay_ms(un->un_udev, 10); 743 } 744 if (i == URE_TIMEOUT) 745 URE_PRINTF(un, "timeout waiting for OOB control\n"); 746 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 747 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 748 URE_RE_INIT_LL); 749 for (i = 0; i < URE_TIMEOUT; i++) { 750 if (usbnet_isdying(un)) 751 return; 752 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 753 URE_LINK_LIST_READY) 754 break; 755 usbd_delay_ms(un->un_udev, 10); 756 } 757 if (i == URE_TIMEOUT) 758 URE_PRINTF(un, "timeout waiting for OOB control\n"); 759 760 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 761 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 762 ~URE_CPCR_RX_VLAN); 763 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 764 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 765 URE_TCR0_AUTO_FIFO); 766 767 /* Configure Rx FIFO threshold and coalescing. */ 768 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 769 URE_RXFIFO_THR1_NORMAL); 770 if (un->un_udev->ud_speed <= USB_SPEED_FULL) { 771 rx_fifo1 = URE_RXFIFO_THR2_FULL; 772 rx_fifo2 = URE_RXFIFO_THR3_FULL; 773 } else { 774 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 775 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 776 } 777 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 778 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 779 780 /* Configure Tx FIFO threshold. */ 781 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 782 URE_TXFIFO_THR_NORMAL); 783 } 784 785 static int 786 ure_match(device_t parent, cfdata_t match, void *aux) 787 { 788 struct usb_attach_arg *uaa = aux; 789 790 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 791 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 792 } 793 794 static void 795 ure_attach(device_t parent, device_t self, void *aux) 796 { 797 USBNET_MII_DECL_DEFAULT(unm); 798 struct usbnet * const un = device_private(self); 799 struct usb_attach_arg *uaa = aux; 800 struct usbd_device *dev = uaa->uaa_device; 801 usb_interface_descriptor_t *id; 802 usb_endpoint_descriptor_t *ed; 803 int error, i; 804 uint16_t ver; 805 uint8_t eaddr[8]; /* 2byte padded */ 806 char *devinfop; 807 uint32_t maclo, machi; 808 809 aprint_naive("\n"); 810 aprint_normal("\n"); 811 devinfop = usbd_devinfo_alloc(dev, 0); 812 aprint_normal_dev(self, "%s\n", devinfop); 813 usbd_devinfo_free(devinfop); 814 815 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 816 un->un_flags |= URE_FLAG_8152; 817 818 un->un_dev = self; 819 un->un_udev = dev; 820 un->un_sc = un; 821 un->un_ops = &ure_ops; 822 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 823 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 824 un->un_rx_list_cnt = URE_RX_LIST_CNT; 825 un->un_tx_list_cnt = URE_TX_LIST_CNT; 826 un->un_tx_bufsz = URE_TX_BUFSZ; 827 if (un->un_udev->ud_speed < USB_SPEED_SUPER || 828 (un->un_flags & URE_FLAG_8152) != 0) { 829 un->un_rx_bufsz = URE_RX_BUFSZ_16K; 830 } else { 831 un->un_rx_bufsz = URE_RX_BUFSZ_32K; 832 } 833 834 #define URE_CONFIG_NO 1 /* XXX */ 835 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 836 if (error) { 837 aprint_error_dev(self, "failed to set configuration: %s\n", 838 usbd_errstr(error)); 839 return; /* XXX */ 840 } 841 842 #define URE_IFACE_IDX 0 /* XXX */ 843 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 844 if (error) { 845 aprint_error_dev(self, "failed to get interface handle: %s\n", 846 usbd_errstr(error)); 847 return; /* XXX */ 848 } 849 850 id = usbd_get_interface_descriptor(un->un_iface); 851 for (i = 0; i < id->bNumEndpoints; i++) { 852 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 853 if (ed == NULL) { 854 aprint_error_dev(self, "couldn't get ep %d\n", i); 855 return; /* XXX */ 856 } 857 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 858 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 859 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 860 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 861 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 862 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 863 } 864 } 865 866 /* Set these up now for ure_ctl(). */ 867 usbnet_attach(un); 868 869 un->un_phyno = 0; 870 871 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 872 switch (ver) { 873 case 0x4c00: 874 un->un_flags |= URE_FLAG_VER_4C00; 875 break; 876 case 0x4c10: 877 un->un_flags |= URE_FLAG_VER_4C10; 878 break; 879 case 0x5c00: 880 un->un_flags |= URE_FLAG_VER_5C00; 881 break; 882 case 0x5c10: 883 un->un_flags |= URE_FLAG_VER_5C10; 884 break; 885 case 0x5c20: 886 un->un_flags |= URE_FLAG_VER_5C20; 887 break; 888 case 0x5c30: 889 un->un_flags |= URE_FLAG_VER_5C30; 890 break; 891 default: 892 /* fake addr? or just fail? */ 893 break; 894 } 895 aprint_normal_dev(self, "RTL%d %sver %04x\n", 896 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 897 (un->un_flags != 0) ? "" : "unknown ", 898 ver); 899 900 if (un->un_flags & URE_FLAG_8152) 901 ure_rtl8152_init(un); 902 else 903 ure_rtl8153_init(un); 904 905 if ((un->un_flags & URE_FLAG_VER_4C00) || 906 (un->un_flags & URE_FLAG_VER_4C10)) 907 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 908 sizeof(eaddr)); 909 else 910 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 911 sizeof(eaddr)); 912 /* 913 * Some chips don't provide a viable MAC address, e.g., what's present 914 * on the NanoPi R1 and R2S. 915 */ 916 if (ETHER_IS_ZERO(eaddr)) { 917 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 918 machi = cprng_strong32() & 0xffff; 919 eaddr[0] = maclo & 0xff; 920 eaddr[1] = (maclo >> 8) & 0xff; 921 eaddr[2] = (maclo >> 16) & 0xff; 922 eaddr[3] = (maclo >> 24) & 0xff; 923 eaddr[4] = machi & 0xff; 924 eaddr[5] = (machi >> 8) & 0xff; 925 } 926 memcpy(un->un_eaddr, eaddr, sizeof(un->un_eaddr)); 927 928 struct ifnet *ifp = usbnet_ifp(un); 929 930 /* 931 * We don't support TSOv4 and v6 for now, that are required to 932 * be handled in software for some cases. 933 */ 934 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 935 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | 936 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 937 938 if (!(un->un_flags & URE_FLAG_VER_4C00)) 939 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 940 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 941 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 942 struct ethercom *ec = usbnet_ec(un); 943 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 944 #ifdef notyet 945 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 946 #endif 947 948 if (!(un->un_flags & URE_FLAG_8152)) 949 unm.un_mii_flags = MIIF_DOPAUSE; 950 951 unm.un_mii_phyloc = un->un_phyno; 952 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 953 0, &unm); 954 } 955 956 static void 957 ure_uno_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 958 { 959 struct ifnet *ifp = usbnet_ifp(un); 960 uint8_t *buf = c->unc_buf; 961 uint16_t pkt_len = 0; 962 uint16_t pkt_count = 0; 963 struct ure_rxpkt rxhdr; 964 965 do { 966 if (total_len < sizeof(rxhdr)) { 967 DPRINTF(("too few bytes left for a packet header\n")); 968 if_statinc(ifp, if_ierrors); 969 return; 970 } 971 972 buf += roundup(pkt_len, 8); 973 974 memcpy(&rxhdr, buf, sizeof(rxhdr)); 975 total_len -= sizeof(rxhdr); 976 977 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 978 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 979 if (pkt_len > total_len) { 980 DPRINTF(("not enough bytes left for next packet\n")); 981 if_statinc(ifp, if_ierrors); 982 return; 983 } 984 985 total_len -= roundup(pkt_len, 8); 986 buf += sizeof(rxhdr); 987 988 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 989 ure_rxcsum(ifp, &rxhdr), 0, 0); 990 991 pkt_count++; 992 993 } while (total_len > 0); 994 995 if (pkt_count) 996 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 997 } 998 999 static int 1000 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1001 { 1002 int enabled = ifp->if_csum_flags_rx, flags = 0; 1003 uint32_t csum, misc; 1004 1005 if (enabled == 0) 1006 return 0; 1007 1008 csum = le32toh(rp->ure_csum); 1009 misc = le32toh(rp->ure_misc); 1010 1011 if (csum & URE_RXPKT_IPV4_CS) { 1012 flags |= M_CSUM_IPv4; 1013 if (csum & URE_RXPKT_TCP_CS) 1014 flags |= M_CSUM_TCPv4; 1015 if (csum & URE_RXPKT_UDP_CS) 1016 flags |= M_CSUM_UDPv4; 1017 } else if (csum & URE_RXPKT_IPV6_CS) { 1018 flags = 0; 1019 if (csum & URE_RXPKT_TCP_CS) 1020 flags |= M_CSUM_TCPv6; 1021 if (csum & URE_RXPKT_UDP_CS) 1022 flags |= M_CSUM_UDPv6; 1023 } 1024 1025 flags &= enabled; 1026 if (__predict_false((flags & M_CSUM_IPv4) && 1027 (misc & URE_RXPKT_IP_F))) 1028 flags |= M_CSUM_IPv4_BAD; 1029 if (__predict_false( 1030 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1031 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1032 )) 1033 flags |= M_CSUM_TCP_UDP_BAD; 1034 1035 return flags; 1036 } 1037 1038 static unsigned 1039 ure_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1040 { 1041 struct ure_txpkt txhdr; 1042 uint32_t frm_len = 0; 1043 uint8_t *buf = c->unc_buf; 1044 1045 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1046 return 0; 1047 1048 /* header */ 1049 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1050 URE_TXPKT_TX_LS); 1051 txhdr.ure_csum = htole32(ure_txcsum(m)); 1052 memcpy(buf, &txhdr, sizeof(txhdr)); 1053 buf += sizeof(txhdr); 1054 frm_len = sizeof(txhdr); 1055 1056 /* packet */ 1057 m_copydata(m, 0, m->m_pkthdr.len, buf); 1058 frm_len += m->m_pkthdr.len; 1059 1060 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1061 1062 return frm_len; 1063 } 1064 1065 /* 1066 * We need to calculate L4 checksum in software, if the offset of 1067 * L4 header is larger than 0x7ff = 2047. 1068 */ 1069 static uint32_t 1070 ure_txcsum(struct mbuf *m) 1071 { 1072 struct ether_header *eh; 1073 int flags = m->m_pkthdr.csum_flags; 1074 uint32_t data = m->m_pkthdr.csum_data; 1075 uint32_t reg = 0; 1076 int l3off, l4off; 1077 uint16_t type; 1078 1079 if (flags == 0) 1080 return 0; 1081 1082 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1083 eh = mtod(m, struct ether_header *); 1084 type = eh->ether_type; 1085 } else 1086 m_copydata(m, offsetof(struct ether_header, ether_type), 1087 sizeof(type), &type); 1088 switch (type = htons(type)) { 1089 case ETHERTYPE_IP: 1090 case ETHERTYPE_IPV6: 1091 l3off = ETHER_HDR_LEN; 1092 break; 1093 case ETHERTYPE_VLAN: 1094 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1095 break; 1096 default: 1097 return 0; 1098 } 1099 1100 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1101 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1102 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1103 in_undefer_cksum(m, l3off, flags); 1104 return 0; 1105 } 1106 reg |= URE_TXPKT_IPV4_CS; 1107 if (flags & M_CSUM_TCPv4) 1108 reg |= URE_TXPKT_TCP_CS; 1109 else 1110 reg |= URE_TXPKT_UDP_CS; 1111 reg |= l4off << URE_L4_OFFSET_SHIFT; 1112 } 1113 #ifdef INET6 1114 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1115 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1116 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1117 in6_undefer_cksum(m, l3off, flags); 1118 return 0; 1119 } 1120 reg |= URE_TXPKT_IPV6_CS; 1121 if (flags & M_CSUM_TCPv6) 1122 reg |= URE_TXPKT_TCP_CS; 1123 else 1124 reg |= URE_TXPKT_UDP_CS; 1125 reg |= l4off << URE_L4_OFFSET_SHIFT; 1126 } 1127 #endif 1128 else if (flags & M_CSUM_IPv4) 1129 reg |= URE_TXPKT_IPV4_CS; 1130 1131 return reg; 1132 } 1133 1134 #ifdef _MODULE 1135 #include "ioconf.c" 1136 #endif 1137 1138 USBNET_MODULE(ure) 1139
Indexes created Sun Oct 25 00:26:45 UTC 2026