| /src/external/gpl3/gdb/dist/sim/ppc/ |
| gen-semantics.c | 70 insn *instruction,
76 instruction->file_entry->fields[insn_name],
82 instruction->file_entry->fields[insn_name],
109 insn *instruction,
113 print_itrace(file, instruction->file_entry, 0/*put_value_in_cache*/);
115 /* validate the instruction, if a cache this has already been done */
117 print_idecode_validate(file, instruction, opcodes);
120 instruction has been verified */
126 instruction->file_entry->fields[insn_name],
136 if (instruction->file_entry->annex != NULL)
[all...] |
| gen-semantics.h | 24 operations required to model a single target processor instruction.
30 No instruction cache exists. The semantic function
36 function that cracks an instruction entering it into a
42 The function that cracks the instruction and enters
52 As a consequence of decoding an instruction, the
54 certain of the variable fields in an instruction
77 insn *instruction,
|
| gen-itable.c | 40 insn *instruction,
45 instruction->file_entry->fields[insn_name],
55 /* output an enumerated type for each instruction */
64 /* output the table that contains the actual instruction info */
85 insn *instruction,
88 char **fields = instruction->file_entry->fields;
91 instruction->file_entry->fields[insn_name],
100 lf_printf(file, " \"%s\",\n", filter_filename (instruction->file_entry->file_name));
101 lf_printf(file, " %d,\n", instruction->file_entry->line_nr);
109 /* output the table that contains the actual instruction info *
[all...] |
| gen-idecode.h | 31 /* Output code to do any final checks on the decoded instruction.
38 insn *instruction,
|
| gen-icache.c | 65 insn *instruction,
77 instruction->file_entry->fields[insn_name],
87 insn *instruction,
184 instruction->file_entry->fields[insn_form],
192 lf_printf(file, "EXTRACTED32(instruction, %d, %d)",
213 insn *instruction,
221 /* extract instruction fields */
223 instruction->file_entry->fields[insn_format]);
252 for (cur_field = instruction->fields->first;
277 instruction,
410 insn *instruction; local
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/ppc/ |
| gen-semantics.c | 70 insn *instruction,
76 instruction->file_entry->fields[insn_name],
82 instruction->file_entry->fields[insn_name],
109 insn *instruction,
113 print_itrace(file, instruction->file_entry, 0/*put_value_in_cache*/);
115 /* validate the instruction, if a cache this has already been done */
117 print_idecode_validate(file, instruction, opcodes);
120 instruction has been verified */
126 instruction->file_entry->fields[insn_name],
136 if (instruction->file_entry->annex != NULL)
[all...] |
| gen-semantics.h | 24 operations required to model a single target processor instruction.
30 No instruction cache exists. The semantic function
36 function that cracks an instruction entering it into a
42 The function that cracks the instruction and enters
52 As a consequence of decoding an instruction, the
54 certain of the variable fields in an instruction
77 insn *instruction,
|
| gen-itable.c | 40 insn *instruction,
45 instruction->file_entry->fields[insn_name],
55 /* output an enumerated type for each instruction */
64 /* output the table that contains the actual instruction info */
85 insn *instruction,
88 char **fields = instruction->file_entry->fields;
91 instruction->file_entry->fields[insn_name],
100 lf_printf(file, " \"%s\",\n", filter_filename (instruction->file_entry->file_name));
101 lf_printf(file, " %d,\n", instruction->file_entry->line_nr);
109 /* output the table that contains the actual instruction info *
[all...] |
| gen-idecode.h | 31 /* Output code to do any final checks on the decoded instruction.
38 insn *instruction,
|
| gen-icache.c | 65 insn *instruction,
77 instruction->file_entry->fields[insn_name],
87 insn *instruction,
184 instruction->file_entry->fields[insn_form],
192 lf_printf(file, "EXTRACTED32(instruction, %d, %d)",
213 insn *instruction,
221 /* extract instruction fields */
223 instruction->file_entry->fields[insn_format]);
252 for (cur_field = instruction->fields->first;
277 instruction,
410 insn *instruction; local
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| tic4x-dis.c | 63 /* Determine the PC offset for a C[34]x instruction.
355 unsigned long instruction,
363 /* Print instruction name. */
370 if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
374 if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
398 EXTRU (instruction, 15, 0)))
403 tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
407 tic4x_print_direct (info, EXTRU (instruction, 15, 0));
411 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
419 tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0)
739 (*info->fprintf_func) (info->stream, "%08lx", instruction); local
751 (*info->fprintf_func) (info->stream, "%08lx", instruction); local
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| tic4x-dis.c | 63 /* Determine the PC offset for a C[34]x instruction.
355 unsigned long instruction,
363 /* Print instruction name. */
370 if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
374 if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
398 EXTRU (instruction, 15, 0)))
403 tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
407 tic4x_print_direct (info, EXTRU (instruction, 15, 0));
411 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
419 tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0)
739 (*info->fprintf_func) (info->stream, "%08lx", instruction); local
751 (*info->fprintf_func) (info->stream, "%08lx", instruction); local
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| tic4x-dis.c | 63 /* Determine the PC offset for a C[34]x instruction.
355 unsigned long instruction,
363 /* Print instruction name. */
370 if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
374 if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
398 EXTRU (instruction, 15, 0)))
403 tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
407 tic4x_print_direct (info, EXTRU (instruction, 15, 0));
411 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
419 tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0)
739 (*info->fprintf_func) (info->stream, "%08lx", instruction); local
751 (*info->fprintf_func) (info->stream, "%08lx", instruction); local
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| tic4x-dis.c | 63 /* Determine the PC offset for a C[34]x instruction.
355 unsigned long instruction,
363 /* Print instruction name. */
370 if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
374 if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
398 EXTRU (instruction, 15, 0)))
403 tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
407 tic4x_print_direct (info, EXTRU (instruction, 15, 0));
411 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
419 tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0)
739 (*info->fprintf_func) (info->stream, "%08lx", instruction); local
751 (*info->fprintf_func) (info->stream, "%08lx", instruction); local
[all...] |
| /src/external/gpl3/gdb/dist/sim/igen/ |
| gen-semantics.c | 148 const insn_entry *instruction,
152 /* validate the instruction, if a cache this has already been done */
155 print_idecode_validate (file, instruction, opcodes);
158 print_itrace (file, instruction, 0 /*put_value_in_cache */ );
160 /* generate the instruction profile call - this is delayed until
161 after the instruction has been verified. The count macro
175 instruction has been verified */
184 instruction->name,
185 instruction->format_name,
193 /* determine the new instruction address *
[all...] |
| gen-idecode.h | 41 /* Output code to do any final checks on the decoded instruction.
48 const insn_entry *instruction,
|
| gen-itable.c | 50 const insn_entry *instruction,
55 lf_print__line_ref (file, instruction->line);
58 instruction->name,
59 instruction->format_name,
63 len = strlen (instruction->format_name);
66 len = strlen (instruction->name);
69 len = strlen (filter_filename (instruction->line->file_name));
137 /* output an enumerated type for each instruction */
163 /* output the table that contains the actual instruction info */
253 const insn_entry *instruction,
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/igen/ |
| gen-semantics.c | 148 const insn_entry *instruction,
152 /* validate the instruction, if a cache this has already been done */
155 print_idecode_validate (file, instruction, opcodes);
158 print_itrace (file, instruction, 0 /*put_value_in_cache */ );
160 /* generate the instruction profile call - this is delayed until
161 after the instruction has been verified. The count macro
175 instruction has been verified */
184 instruction->name,
185 instruction->format_name,
193 /* determine the new instruction address *
[all...] |
| gen-idecode.h | 41 /* Output code to do any final checks on the decoded instruction.
48 const insn_entry *instruction,
|
| gen-itable.c | 50 const insn_entry *instruction,
55 lf_print__line_ref (file, instruction->line);
58 instruction->name,
59 instruction->format_name,
63 len = strlen (instruction->format_name);
66 len = strlen (instruction->name);
69 len = strlen (filter_filename (instruction->line->file_name));
137 /* output an enumerated type for each instruction */
163 /* output the table that contains the actual instruction info */
253 const insn_entry *instruction,
[all...] |
| /src/external/gpl3/gdb/dist/gdb/arch/ |
| arm.h | 25 #define IS_PAC(instruction) (instruction == 0xf3af801d)
26 #define IS_PACBTI(instruction) (instruction == 0xf3af800d)
27 #define IS_BTI(instruction) (instruction == 0xf3af800f)
28 #define IS_PACG(instruction) ((instruction & 0xfff0f0f0) == 0xfb60f000)
29 #define IS_AUT(instruction) (instruction == 0xf3af802d
[all...] |
| /src/external/gpl3/gdb.old/dist/gdb/arch/ |
| arm.h | 25 #define IS_PAC(instruction) (instruction == 0xf3af801d)
26 #define IS_PACBTI(instruction) (instruction == 0xf3af800d)
27 #define IS_BTI(instruction) (instruction == 0xf3af800f)
28 #define IS_PACG(instruction) ((instruction & 0xfff0f0f0) == 0xfb60f000)
29 #define IS_AUT(instruction) (instruction == 0xf3af802d
[all...] |
| /src/external/public-domain/xz/dist/src/liblzma/simple/ |
| ia64.c | 41 uint64_t instruction = 0; local
44 instruction += (uint64_t)(
48 uint64_t inst_norm = instruction >> bit_res;
73 instruction &= (1 << bit_res) - 1;
74 instruction |= (inst_norm << bit_res);
78 instruction
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-arm.c | 436 instruction. (For backward compatibility, those instructions
439 - The IT instruction may appear, and if it does is validated
452 conditional affix except in the scope of an IT instruction. */
500 MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
502 MVE_UNPREDICABLE_INSN, /* MVE instruction that is non-predicable. */
512 unsigned long instruction; member in struct:arm_it
517 unconditional versions of the instruction, or -1u if nothing is
521 /* This does not indicate an actual NEON instruction, only that
524 /* Set to the opcode if the instruction needs relaxation
22321 unsigned long instruction = 0xbf00; local
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-arm.c | 436 instruction. (For backward compatibility, those instructions
439 - The IT instruction may appear, and if it does is validated
452 conditional affix except in the scope of an IT instruction. */
500 MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
502 MVE_UNPREDICABLE_INSN, /* MVE instruction that is non-predicable. */
512 unsigned long instruction; member in struct:arm_it
517 unconditional versions of the instruction, or -1u if nothing is
521 /* This does not indicate an actual NEON instruction, only that
524 /* Set to the opcode if the instruction needs relaxation
22324 unsigned long instruction = 0xbf00; local
[all...] |
