| /src/sys/dev/pci/ |
| ppbreg.h | 36 * Routine to translate between secondary bus interrupt pin/device number and
37 * primary bus interrupt pin number.
39 #define PPB_INTERRUPT_SWIZZLE(pin, device) \
40 ((((pin) + (device) - 1) % 4) + 1)
|
| /src/sys/arch/mips/alchemy/dev/ |
| augpiovar.h | 47 #define AUGPIO_READ(pin) augpio_read(NULL, (pin))
48 #define AUGPIO_WRITE(pin,val) augpio_write(NULL, (pin), (val))
49 #define AUGPIO_CTL(pin,flags) augpio_ctl(NULL, (pin), (flags))
50 #define AUGPIO_GETCTL(pin) augpio_getctl(NULL, (pin))
52 #define AUGPIO2_READ(pin) augpio2_read(NULL, (pin))
[all...] |
| augpio.c | 96 int pin; local
136 for (pin = 0; pin < sc->sc_npins; pin++) {
137 gpio_pin_t *pp = &sc->sc_pins[pin];
139 pp->pin_num = pin;
141 pp->pin_flags = sc->sc_getctl(sc, pin);
142 pp->pin_state = sc->sc_gc.gp_pin_read(sc, pin);
155 augpio_read(void *arg, int pin)
158 pin = 1 << pin
[all...] |
| /src/sys/arch/evbppc/stand/wii/ |
| gpio.c | 42 gpio_set(int pin)
44 out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) | __BIT(pin));
48 gpio_clear(int pin)
50 out32(HW_GPIOB_OUT, in32(HW_GPIOB_OUT) & ~__BIT(pin));
54 gpio_get(int pin)
56 return (in32(HW_GPIOB_IN) >> pin) & 1;
60 gpio_enable_int(int pin)
62 out32(HW_GPIO_INTLVL, in32(HW_GPIO_INTLVL) | __BIT(pin));
66 gpio_disable_int(int pin)
68 out32(HW_GPIO_INTLVL, in32(HW_GPIO_INTLVL) & ~__BIT(pin));
[all...] |
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/pinctrl/ |
| apple.h | 11 #define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16))
|
| pinctrl-cv18xx.h | 15 #define PINMUX2(pin, mux, mux2) \
16 (((pin) & 0xffff) | (((mux) & 0xff) << 16) | (((mux2) & 0xff) << 24))
18 #define PINMUX(pin, mux) \
19 PINMUX2(pin, mux, PIN_MUX_INVALD)
|
| rzg2l-pinctrl.h | 17 * Create the pin index from its bank and position numbers and store in
22 /* Convert a port and pin label to its global pin index */
23 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
|
| rzv2m-pinctrl.h | 17 * Create the pin index from its bank and position numbers and store in
22 /* Convert a port and pin label to its global pin index */
23 #define RZV2M_GPIO(port, pin) ((port) * RZV2M_PINS_PER_PORT + (pin))
|
| /src/sys/dev/acpi/ |
| qcomgpioreg.h | 23 #define _TLMM_GPIO_PIN_OFFSET(pin, reg) ((pin) * 0x1000 + (reg))
25 #define TLMM_GPIO_CTL(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0x0)
30 #define TLMM_GPIO_IN_OUT(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0x4)
34 #define TLMM_GPIO_INTR_CFG(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0x8)
46 #define TLMM_GPIO_INTR_STATUS(pin) _TLMM_GPIO_PIN_OFFSET(pin, 0xc
[all...] |
| /src/sys/arch/evbsh3/ap_ms104_sh4/ |
| ap_ms104_sh4.c | 88 gpio_intr_establish(int pin, int (*ih_func)(void *), void *ih_arg)
93 KASSERT(pin >= 0 && pin <= 15);
94 KASSERT(gpio_intr_func_table[pin].ih_func == NULL);
95 KASSERT((_reg_read_4(SH4_PCTRA) & (1 << (pin * 2))) == 0); /*input*/
100 gpio_intr_func_table[pin].ih_irq = pin;
101 gpio_intr_func_table[pin].ih_func = ih_func;
102 gpio_intr_func_table[pin].ih_arg = ih_arg;
106 reg |= 1 << pin;
118 int pin = ih->ih_irq; local
146 int pin; local
[all...] |
| /src/sys/arch/arm/imx/ |
| imx23_pinctrl.c | 89 * Supported capabilities for each GPIO pin.
95 /* PIN 0 */
97 /* PIN 1 */
99 /* PIN 2 */
101 /* PIN 3 */
103 /* PIN 4 */
105 /* PIN 5 */
107 /* PIN 6 */
109 /* PIN 7 */
111 /* PIN 8 *
389 struct imx23_pinctrl_fdt_pin *pin; local
420 struct imx23_pinctrl_fdt_pin *pin = priv; local
431 struct imx23_pinctrl_fdt_pin *pin = priv; local
446 struct imx23_pinctrl_fdt_pin *pin = priv; local
[all...] |
| /src/sys/arch/arm/xilinx/ |
| zynq_gpio.c | 48 #define MASK_DATA_REG(pin) (0x000 + 0x4 * ((pin) / 16))
49 #define DATA_RO_REG(pin) (0x060 + 0x4 * ((pin) / 32))
50 #define DATA_RO_BIT(pin) __BIT((pin) % 32)
51 #define DIRM_REG(pin) (0x204 + 0x40 * ((pin) / 32))
52 #define DIRM_BIT(pin) __BIT((pin) % 32
125 const uint8_t pin = be32toh(gpio[1]) & 0xff; local
151 struct zynq_gpio_pin *pin = priv; local
164 struct zynq_gpio_pin *pin = priv; local
180 struct zynq_gpio_pin *pin = priv; local
244 u_int pin; local
[all...] |
| /src/sys/dev/ic/ |
| pl061.c | 51 u_int pin; local
61 for (pin = 0; pin < 8; pin++) {
62 sc->sc_pins[pin].pin_num = pin;
64 if ((cnf & __BIT(pin)) != 0)
66 sc->sc_pins[pin].pin_caps =
69 sc->sc_pins[pin].pin_state =
70 plgpio_pin_read(sc, pin);
[all...] |
| /src/sys/arch/mips/adm5120/dev/ |
| admgpio.c | 60 admgpio_pin_ctl(void *cookie, int pin, int flags)
67 mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_OE);
77 admgpio_pin_read(void *cookie, int pin)
82 KASSERT(pin >= 0 && pin < 8);
84 if (sc->sc_pins[pin].pin_flags == GPIO_PIN_INPUT)
85 mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_IV);
87 mask = __SHIFTIN(1 << pin, ADM5120_GPIO0_OV);
95 admgpio_pin_write(void *cookie, int pin, int value)
100 KASSERT(pin >= 0 && pin < 8)
112 int pin; local
[all...] |
| /src/external/bsd/wpa/dist/wpa_supplicant/examples/ |
| wps-ap-cli | 16 echo "Enter a PIN from a station to be enrolled to the network."
17 printf "Enrollee PIN: "
18 read pin
19 cpin=`$CLI wps_check_pin "$pin" | tail -1`
22 printf "Do you want to use this PIN (y/n)? "
26 cpin=`echo "$pin" | sed "s/[^1234567890]//g"`
34 echo "Invalid PIN: $pin"
37 echo "Enabling Enrollee PIN: $cpin"
51 echo "2: Enter Enrollee PIN"
[all...] |
| /src/sys/dev/ppbus/ |
| ppbus_gpio.c | 81 gpio_pin_t *pin; local
84 for (pin = &sc->sc_gpio_pins[0], i = 0; i < PPBUS_NPINS; pin++, i++) {
85 pin->pin_num = i;
88 pin->pin_caps = GPIO_PIN_INPUT;
89 pin->pin_flags = GPIO_PIN_INPUT;
90 pin->pin_state = gpio_ppbus_pin_read(sc, i);
92 pin->pin_caps = GPIO_PIN_OUTPUT;
93 pin->pin_flags = GPIO_PIN_OUTPUT;
94 pin->pin_state = GPIO_PIN_LOW
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| hw_gpio.h | 54 struct hw_gpio_pin *pin,
57 const struct hw_gpio_pin *pin,
60 const struct hw_gpio_pin *pin,
63 struct hw_gpio_pin *pin,
66 struct hw_gpio_pin *pin,
69 struct hw_gpio_pin *pin);
115 struct hw_gpio *pin,
121 struct hw_gpio_pin *pin,
125 const struct hw_gpio_pin *pin,
129 struct hw_gpio *pin,
[all...] |
| amdgpu_hw_gpio.c | 69 struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr); local
71 store_registers(pin);
73 ptr->opened = (dal_hw_gpio_config_mode(pin, mode) == GPIO_RESULT_OK);
130 struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr); local
132 return dal_hw_gpio_config_mode(pin, mode);
138 struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr); local
140 restore_registers(pin);
154 /* turn off output enable, act as input pin;
155 * program the pin as GPIO, mask out signal driven by HW */
160 /* turn on output enable, act as output pin;
[all...] |
| /src/sys/arch/arm/marvell/ |
| mvsocgppvar.h | 33 mvsocgpp_intr_establish(int pin, int ipl, int type,
37 return intr_establish(gpp_irqbase + pin, ipl, type, func, arg);
|
| /src/sys/arch/arm/rockchip/ |
| rk_gpio.c | 69 #define GPIOV2_SWPORT_DR_REG(pin) \
70 (GPIOV2_SWPORT_DR_BASE + GPIOV2_REG_OFFSET(pin))
72 #define GPIOV2_SWPORT_DDR_REG(pin) \
73 (GPIOV2_SWPORT_DDR_BASE + GPIOV2_REG_OFFSET(pin))
75 #define GPIOV2_REG_OFFSET(pin) (((pin) >> 4) << 2)
76 #define GPIOV2_DATA_MASK(pin) (__BIT((pin) & 0xF))
77 #define GPIOV2_WRITE_MASK(pin) (__BIT(((pin) & 0xF) | 0x10)
133 const uint8_t pin = be32toh(gpio[1]) & 0xff; local
154 struct rk_gpio_pin *pin = priv; local
167 struct rk_gpio_pin *pin = priv; local
183 struct rk_gpio_pin *pin = priv; local
416 const uint32_t pin = be32toh(specifier[0]); local
460 const u_int pin = be32toh(specifier[0]); local
581 u_int pin; local
[all...] |
| /src/sys/dev/fdt/ |
| gpioleds.c | 52 struct fdtbus_gpio_pin *pin = priv; local
54 return fdtbus_gpio_read(pin);
60 struct fdtbus_gpio_pin *pin = priv; local
62 fdtbus_gpio_write(pin, state);
83 struct fdtbus_gpio_pin *pin; local
97 /* Get the output pin */
98 pin = fdtbus_gpio_acquire(child, "gpios", GPIO_PIN_OUTPUT);
99 if (pin == NULL)
103 if (led_attach(label, pin, gpioleds_get, gpioleds_set) == NULL)
111 gpioleds_set(pin, LED_STATE_ON)
[all...] |
| /src/sys/arch/arm/apple/ |
| apple_pinctrl.c | 64 #define GPIO_PIN(pin) ((pin) * 4)
78 #define GPIO_IRQ(grp, pin) (0x800 + (grp) * 64 + ((pin) >> 5) * 4)
110 apple_gpio_pin_ctl(void *cookie, int pin, int flags)
114 KASSERT(pin < sc->sc_npins);
116 uint32_t reg = PINCTRL_READ(sc, GPIO_PIN(pin));
128 PINCTRL_WRITE(sc, GPIO_PIN(pin), reg);
135 struct apple_gpio_pin *pin; local
147 pin = kmem_alloc(sizeof(*pin), KM_SLEEP)
161 struct apple_gpio_pin *pin = priv; local
171 struct apple_gpio_pin *pin = priv; local
187 struct apple_gpio_pin *pin = priv; local
[all...] |
| /src/sys/arch/arm/ti/ |
| ti_gpio.c | 151 ti_gpio_ctl(struct ti_gpio_softc *sc, u_int pin, int flags)
159 oe |= __BIT(pin);
161 oe &= ~__BIT(pin);
164 sc->sc_pinout[pin] = (flags & GPIO_PIN_OUTPUT) != 0;
180 const uint8_t pin = be32toh(gpio[1]) & 0xff; local
183 if (pin >= __arraycount(sc->sc_pins))
187 error = ti_gpio_ctl(sc, pin, flags);
195 gpin->pin_nr = pin;
206 struct ti_gpio_pin *pin = priv; local
209 ti_gpio_ctl(pin->pin_sc, pin->pin_nr, GPIO_PIN_INPUT)
219 struct ti_gpio_pin *pin = priv; local
243 struct ti_gpio_pin *pin = priv; local
267 const u_int pin = intr->intr_pin; local
293 const u_int pin = be32toh(specifier[0]); local
377 const u_int pin = be32toh(specifier[0]); local
539 u_int pin; local
578 const u_int pin = bit - 1; local
[all...] |
| /src/sys/dev/gpio/ |
| gpiolock.c | 81 aprint_debug("%s: invalid pin mask 0x%02x\n", cf->cf_name,
94 int pin, caps; local
108 for (pin = 0; pin < sc->sc_npins; pin++) {
109 caps = gpio_pin_caps(sc->sc_gpio, &sc->sc_map, pin);
111 aprint_error(": data pin is unable to read input\n");
114 aprint_normal(" [%d]", sc->sc_map.pm_map[pin]);
116 gpio_pin_ctl(sc->sc_gpio, &sc->sc_map, pin, sc->sc_data);
169 int pos, pin; local
[all...] |
| gpio.c | 148 int pin; local
150 for (pin = 0; pin < sc->sc_npins; pin++) {
151 gpiobus_pin_ctl(sc->sc_gc, pin, sc->sc_pins[pin].pin_flags);
152 gpiobus_pin_write(sc->sc_gc, pin, sc->sc_pins[pin].pin_state);
213 gpio_pin_defname(struct gpio_softc *sc, int pin)
215 KASSERT(pin >= 0)
235 int pin; local
358 int npins, pin, i; local
380 int npins, pin, i; local
405 int pin, i; local
749 int error, pin, value, flags; local
1034 int error, pin, value, flags; local
[all...] |
