| /src/tests/sbin/ifconfig/ |
| t_tap.sh | 30 taps="/tmp/taps"
41 seq 65535 65000 > $taps # Try to avoid stalling automated runs.
55 done < $taps
60 if [ -f $taps ]; then
71 done < $taps
73 rm $taps
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp_dscl.c | 238 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
240 if (taps == 8)
242 else if (taps == 7)
244 else if (taps == 6)
246 else if (taps == 5)
248 else if (taps == 4)
250 else if (taps == 3)
252 else if (taps == 2)
254 else if (taps == 1)
265 uint32_t taps,
[all...] |
| amdgpu_dcn10_dpp.c | 173 /* Set default taps if none are provided */
175 scl_data->taps.h_taps = 4;
177 scl_data->taps.h_taps = in_taps->h_taps;
179 scl_data->taps.v_taps = 4;
181 scl_data->taps.v_taps = in_taps->v_taps;
183 scl_data->taps.v_taps_c = 2;
185 scl_data->taps.v_taps_c = in_taps->v_taps_c;
187 scl_data->taps.h_taps_c = 2;
190 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
192 scl_data->taps.h_taps_c = in_taps->h_taps_c
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dwb_scl.c | 654 static const uint16_t *wbscl_get_filter_coeffs_16p(int taps, struct fixed31_32 ratio)
656 if (taps == 12)
658 else if (taps == 11)
660 else if (taps == 10)
662 else if (taps == 9)
664 else if (taps == 8)
666 else if (taps == 7)
668 else if (taps == 6)
670 else if (taps == 5)
672 else if (taps == 4
[all...] |
| amdgpu_dcn20_dpp.c | 408 /* Set default taps if none are provided */
411 scl_data->taps.h_taps = 8;
413 scl_data->taps.h_taps = 4;
415 scl_data->taps.h_taps = in_taps->h_taps;
418 scl_data->taps.v_taps = 8;
420 scl_data->taps.v_taps = 4;
422 scl_data->taps.v_taps = in_taps->v_taps;
425 scl_data->taps.v_taps_c = 4;
427 scl_data->taps.v_taps_c = 2;
429 scl_data->taps.v_taps_c = in_taps->v_taps_c
[all...] |
| amdgpu_dcn20_resource.c | 2157 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2158 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2159 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2160 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_transform.c | 127 if (data->taps.h_taps + data->taps.v_taps <= 2) {
137 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,
138 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
187 int taps,
193 int taps_pairs = (taps + 1) / 2;
220 if (taps % 2 && pair == taps_pairs - 1)
272 dc_fixpt_from_int(data->taps.h_taps + 1)),
281 dc_fixpt_from_int(data->taps.v_taps + 1)),
309 static const uint16_t *get_filter_coeffs_16p(int taps, struct fixed31_32 ratio
876 uint32_t taps; local in function:decide_taps
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_transform_v.c | 158 * Purpose: setup scaling mode : bypass, RGb, YCbCr and nummber of taps
172 set_reg_field_value(value, data->taps.h_taps - 1,
174 set_reg_field_value(value, data->taps.v_taps - 1,
176 set_reg_field_value(value, data->taps.h_taps_c - 1,
178 set_reg_field_value(value, data->taps.v_taps_c - 1,
183 if (data->taps.h_taps + data->taps.v_taps > 2) {
192 if (data->taps.h_taps_c + data->taps.v_taps_c > 2) {
292 int taps,
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_resource.c | 760 int taps,
782 if (int_part < taps) {
783 int int_adj = *vp_offset >= (taps - int_part) ?
784 (taps - int_part) : *vp_offset;
788 } else if (int_part > taps) {
789 *vp_offset += int_part - taps;
790 *vp_size -= int_part - taps;
791 int_part = taps;
821 if (int_part < taps) {
822 int int_adj = end_offset >= (taps - int_part)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/ |
| transform.h | 175 struct scaling_taps taps; member in struct:scaler_data
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_mode_vba.c | 377 scaler_taps_st *taps = &pipes[j].pipe.scale_taps; local in function:fetch_pipe_params
421 mode_lib->vba.htaps[mode_lib->vba.NumberOfActivePlanes] = taps->htaps;
422 mode_lib->vba.vtaps[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps;
423 mode_lib->vba.HTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->htaps_c;
424 mode_lib->vba.VTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps_c;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 389 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps;
395 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
396 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
397 input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c;
986 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
987 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
988 v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
989 v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
|
| amdgpu_dce_calcs.c | 493 /*maximum horizontal and vertical scale ratio is 4, and should not exceed the number of taps*/
494 /*for downscaling with the pre-downscaler, the horizontal scale ratio must be more than the ceiling of one quarter of the number of taps*/
496 /*the number of lines in the line buffer has to exceed the number of vertical taps*/
778 /*vertical scale ratio and the number of vertical taps increased by one. add one more for possible odd line*/
785 /*line buffer prefetching is done when the number of lines in the line buffer exceeds the number of taps plus*/
1658 /*the scaling limits factor is the product of the horizontal scale ratio, and the ratio of the vertical taps divided by the scaler efficiency clamped to at least 1.*/
2807 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
2808 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
2862 data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
2863 data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 787 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; local in function:dml20_rq_dlg_get_dlg_params
976 htaps_l = taps->htaps;
977 htaps_c = taps->htaps_c;
|
| amdgpu_display_rq_dlg_calc_20v2.c | 787 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; local in function:dml20v2_rq_dlg_get_dlg_params
977 htaps_l = taps->htaps;
978 htaps_c = taps->htaps_c;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 833 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; local in function:dml_rq_dlg_get_dlg_params
1028 htaps_l = taps->htaps;
1029 htaps_c = taps->htaps_c;
|
