| /src/sys/arch/amiga/stand/bootblock/elf2bb/ |
| elf2bb.h | 67 #define RELFLAG_SELFLOADING 0x10
|
| /src/sys/dev/ic/ |
| ne2000reg.h | 20 #define NE2000_ASIC_OFFSET 0x10
22 #define NE2000_NIC_NPORTS 0x10
23 #define NE2000_ASIC_NPORTS 0x10
|
| dl10019reg.h | 48 #define DL0_19_GPIO_MII_DIROUT 0x10 /* MII direction MAC->PHY */
49 #define DL0_GPIO_MII_DATAIN 0x10 /* MII data PHY->MAC */
|
| lptreg.h | 62 #define LPS_SELECT 0x10 /* printer selected */
72 #define LPC_IENABLE 0x10 /* printer out of paper */
|
| /src/sys/arch/next68k/dev/ |
| bmapreg.h | 30 #define BMAP_DDIR_UTPENABLE_MASK 0x80|0x10
38 #define BMAP_DATA_UTPENABLED_MASK 0x10
39 #define BMAP_DATA_UTPENABLE 0x80|0x10
|
| /src/sys/arch/hpcmips/tx/ |
| tx39reg.h | 40 #define TMPR3912 0x10
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| imx6dl-skov-revc-lt6.dts | 76 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
77 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
78 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
79 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
80 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
81 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
82 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
83 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
84 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
85 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all...] |
| imx6q-skov-revc-lt6.dts | 98 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
99 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
100 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
101 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
102 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
103 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
104 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
105 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
106 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
107 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all...] |
| imx6ul-tx6ul-mainboard.dts | 203 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
204 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
205 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
206 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
207 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
208 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
209 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
210 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
211 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
212 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
[all...] |
| /src/sys/arch/ia64/include/ |
| sapicreg.h | 37 #define SAPIC_IO_WINDOW 0x10
46 #define SAPIC_RTE_BASE 0x10
|
| /src/sys/arch/luna68k/stand/boot/ |
| preset.h | 86 #define PS_COFF 0x10 /* 5: boot COFF format kernel */
|
| /src/sys/dev/podulebus/ |
| oakreg.h | 10 #define OAK_PDMA_STATUS 0x10
|
| /src/sys/arch/hp300/dev/ |
| sti_diovar.h | 33 #define STI_DIO_SIZE 0x10 /* expected total device size
|
| /src/sys/dev/wsfont/ |
| sony8x16.h | 77 0x10, /* ...*.... */
78 0x10, /* ...*.... */
89 0x10, /* ...*.... */
90 0x10, /* ...*.... */
205 0x10, /* ...*.... */
206 0x10, /* ...*.... */
207 0x10, /* ...*.... */
208 0x10, /* ...*.... */
210 0x10, /* ...*.... */
211 0x10, /* ...*.... *
[all...] |
| /src/sys/arch/mips/alchemy/dev/ |
| augpioreg.h | 50 #define AUGPIO_PINSTATERD 0x10
51 #define AUGPIO_PININPUTEN 0x10
58 #define AUGPIO2_INTEN 0x10
|
| /src/sys/arch/hp300/hp300/ |
| leds.h | 46 #define LED_PULSE 0x10 /* heartbeat */
|
| /src/sys/arch/x68k/dev/ |
| mb86601reg.h | 46 #define PSNS_SEL 0x10
|
| /src/sys/dev/pckbport/ |
| elantechreg.h | 34 #define ELANTECH_REG_READ 0x10
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/rsmu/ |
| rsmu_0_0_2_sh_mask.h | 28 #define RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_INSTANCE__SHIFT 0x10
|
| /src/sys/arch/news68k/dev/ |
| ms_hbreg.h | 39 #define MSSTAT_BUF 0x10 /* mouse buffer full */
|
| /src/sys/external/bsd/gnu-efi/dist/lib/ia64/ |
| setjmp.S | 25 add r10 = 0x10*20, in0
27 stf.spill.nta [in0] = f2, 0x10
31 stf.spill.nta [in0] = f3, 0x10
35 stf.spill.nta [in0] = f4, 0x10
39 stf.spill.nta [in0] = f5, 0x10
43 stf.spill.nta [in0] = f16, 0x10
47 stf.spill.nta [in0] = f17, 0x10
51 stf.spill.nta [in0] = f18, 0x10
55 stf.spill.nta [in0] = f19, 0x10
58 stf.spill.nta [in0] = f20, 0x10
[all...] |
| /src/sys/arch/i386/pci/ |
| gscpcibreg.h | 24 #define GSCGPIO_BASE 0x10
31 #define GSCGPIO_GPDO1 0x10
|
| /src/sys/dev/pci/ |
| if_pcnreg.h | 62 #define PCN16_RDP 0x10
72 #define PCN32_RDP 0x10
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/clk/ |
| clk_10_0_2_sh_mask.h | 31 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
37 #define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT 0x10
42 #define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT 0x10
47 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10
58 #define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT 0x10
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_piocnv50.c | 43 nvkm_mask(device, 0x610200 + (ctrl * 0x10), 0x00000001, 0x00000000);
45 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000))
49 nvkm_rd32(device, 0x610200 + (ctrl * 0x10)));
62 nvkm_wr32(device, 0x610200 + (ctrl * 0x10), 0x00002000);
64 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000))
68 nvkm_rd32(device, 0x610200 + (ctrl * 0x10)));
72 nvkm_wr32(device, 0x610200 + (ctrl * 0x10), 0x00000001);
74 u32 tmp = nvkm_rd32(device, 0x610200 + (ctrl * 0x10));
79 nvkm_rd32(device, 0x610200 + (ctrl * 0x10)));
|
