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  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imx6ull-pinfunc-snvs.h 15 #define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0
16 #define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0
17 #define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0
18 #define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0
19 #define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0
20 #define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0
21 #define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0
22 #define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0
23 #define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0
24 #define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x
    [all...]
imx51-ts4800.dts 261 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
262 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
263 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
264 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
265 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
266 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
267 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
268 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
269 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
270 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
    [all...]
imx53-tx53-x03x.dts 289 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
290 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
291 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
292 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
293 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
294 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
295 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
296 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
297 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
298 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
    [all...]
imx6sll-pinfunc.h 20 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
26 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
33 #define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0
39 #define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0
45 #define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0
50 #define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0
55 #define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0
61 #define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0
67 #define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0
73 #define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x
    [all...]
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/interrupt-controller/
mvebu-icu.h 16 #define ICU_GRP_REI 0x5
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/pmu/
exynos_ppmu.h 19 #define PPMU_RO_DATA_CNT 0x5
24 #define PPMU_V2_WO_DATA_CNT 0x5
  /src/external/lgpl3/gmp/dist/mpn/arm64/
bdiv_dbm1c.asm 48 ldr x5, [up], #8
55 L(fi3): mul x12, x5, bd
56 umulh x13, x5, bd
57 ldr x5, [up], #8
60 L(fi0): mul x10, x5, bd
61 umulh x11, x5, bd
62 ldr x5, [up], #8
66 mul x12, x5, bd
67 umulh x13, x5, bd
69 ldr x5, [up], #
    [all...]
rsh1aors_n.asm 66 L(bx1): ldr x5, [up],#8
70 L(b01): ADDSUB x13, x5, x9
73 ldp x4, x5, [up],#48
76 ADDSUBC x15, x5, x9
77 ldp x4, x5, [up,#-32]
81 ADDSUBC x13, x5, x9
93 L(b11): ADDSUB x15, x5, x9
96 ldp x4, x5, [up],#32
99 ADDSUBC x13, x5, x9
101 ldp x4, x5, [up,#-16
    [all...]
  /src/sys/arch/pmax/pmax/
pmaxtype.h 45 #define DS_ISIS 0x5 /* DECsystem 5800 */
  /src/sys/dev/isa/
tsdioreg.h 36 #define TSDIO_PADR 0x5
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/sound/
adi,adau1977.h 12 #define ADAU1977_MICBIAS_7V5 0x5
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/soc/
qcom,apr.h 12 #define APR_DOMAIN_APPS 0x5
18 #define APR_SVC_VSM 0x5
  /src/external/gpl3/gdb/dist/sim/testsuite/aarch64/
fstur.s 51 sub x5, x0, #255
54 ldur s2, [x5, #255]
63 add x5, x0, #256
66 ldur s2, [x5, #-256]
78 sub x5, x0, #255
81 ldur d2, [x5, #255]
90 add x5, x0, #256
93 ldur d2, [x5, #-256]
105 sub x5, x0, #255
108 ldur q2, [x5, #255
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/testsuite/aarch64/
fstur.s 51 sub x5, x0, #255
54 ldur s2, [x5, #255]
63 add x5, x0, #256
66 ldur s2, [x5, #-256]
78 sub x5, x0, #255
81 ldur d2, [x5, #255]
90 add x5, x0, #256
93 ldur d2, [x5, #-256]
105 sub x5, x0, #255
108 ldur q2, [x5, #255
    [all...]
  /src/lib/libc/arch/aarch64/sys/
__syscall.S 64 mov x4, x5
65 mov x5, x6
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/MCTargetDesc/
ARCInfo.h 30 LO = 0x5,
51 BRHS = 0x5
  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
se_loop_kill_dcr.S 346 P4 = 0x5 (Z);
354 EXCPT 0x5;
359 EXCPT 0x5;
365 EXCPT 0x5;
372 EXCPT 0x5;
380 EXCPT 0x5;
389 EXCPT 0x5;
394 EXCPT 0x5;
400 EXCPT 0x5;
407 EXCPT 0x5;
    [all...]
se_loop_kill_dcr_01.S 346 P4 = 0x5 (Z);
354 EXCPT 0x5;
359 EXCPT 0x5;
365 EXCPT 0x5;
372 EXCPT 0x5;
380 EXCPT 0x5;
389 EXCPT 0x5;
394 EXCPT 0x5;
400 EXCPT 0x5;
407 EXCPT 0x5;
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
se_loop_kill_dcr.S 346 P4 = 0x5 (Z);
354 EXCPT 0x5;
359 EXCPT 0x5;
365 EXCPT 0x5;
372 EXCPT 0x5;
380 EXCPT 0x5;
389 EXCPT 0x5;
394 EXCPT 0x5;
400 EXCPT 0x5;
407 EXCPT 0x5;
    [all...]
se_loop_kill_dcr_01.S 346 P4 = 0x5 (Z);
354 EXCPT 0x5;
359 EXCPT 0x5;
365 EXCPT 0x5;
372 EXCPT 0x5;
380 EXCPT 0x5;
389 EXCPT 0x5;
394 EXCPT 0x5;
400 EXCPT 0x5;
407 EXCPT 0x5;
    [all...]
  /src/sys/dev/i2c/
mpl115areg.h 42 #define MPL115A_A0_LSB 0x5
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/iio/addac/
adi,ad74413r.h 13 #define CH_FUNC_CURRENT_INPUT_LOOP_POWER 0x5
  /src/external/apache2/llvm/dist/clang/lib/Headers/
arm64intr.h 28 _ARM64_BARRIER_NSHLD = 0x5,
  /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_core/hsalsa20/ref2/
core_hsalsa20_ref2.c 22 uint32_t x0, x1, x2, x3, x4, x5, x6, x7, x8, local
28 x5 = U32C(0x3320646e);
33 x5 = LOAD32_LE(c + 4);
55 x9 ^= ROTL32(x5 + x1, 7);
56 x13 ^= ROTL32(x9 + x5, 9);
58 x5 ^= ROTL32(x1 + x13, 18);
71 x6 ^= ROTL32(x5 + x4, 7);
72 x7 ^= ROTL32(x6 + x5, 9);
74 x5 ^= ROTL32(x4 + x7, 18);
86 STORE32_LE(out + 4, x5);
    [all...]
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mp-pinfunc.h 26 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0
31 #define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0
35 #define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0
39 #define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READY 0x028 0x288 0x554 0x5 0x0
43 #define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0
48 #define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0
55 #define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0
61 #define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0
69 #define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1
72 #define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x
    [all...]

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