1 /* $NetBSD: rk_gmac.c,v 1.24 2026/06/22 20:26:34 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.24 2026/06/22 20:26:34 jakllsch Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 #include <sys/rndsource.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/miivar.h> 46 47 #include <dev/ic/dwc_gmac_var.h> 48 #include <dev/ic/dwc_gmac_reg.h> 49 #include <dev/fdt/dwc_gmac_fdt_subr.h> 50 51 #include <dev/fdt/fdtvar.h> 52 #include <dev/fdt/syscon.h> 53 54 #define RK_GMAC_TXDLY_DEFAULT 0x30 55 #define RK_GMAC_RXDLY_DEFAULT 0x10 56 57 enum rk_gmac_type { 58 GMAC_RK3288 = 1, 59 GMAC_RK3328, 60 GMAC_RK3399 61 }; 62 63 static const struct device_compatible_entry compat_data[] = { 64 { .compat = "rockchip,rk3288-gmac", .value = GMAC_RK3288 }, 65 { .compat = "rockchip,rk3328-gmac", .value = GMAC_RK3328 }, 66 { .compat = "rockchip,rk3399-gmac", .value = GMAC_RK3399 }, 67 DEVICE_COMPAT_EOL 68 }; 69 70 struct rk_gmac_softc { 71 struct dwc_gmac_softc sc_base; 72 struct syscon *sc_syscon; 73 enum rk_gmac_type sc_type; 74 }; 75 76 /* 77 * RK3288 specific 78 */ 79 80 #define RK3288_GRF_SOC_CON1 0x0248 81 #define RK3288_GRF_SOC_CON1_RMII_MODE __BIT(14) 82 #define RK3288_GRF_SOC_CON1_GMAC_CLK_SEL __BITS(13,12) 83 #define RK3288_GRF_SOC_CON1_GMAC_CLK_SEL_125M 0 84 #define RK3288_GRF_SOC_CON1_GMAC_CLK_SEL_2_5M 2 85 #define RK3288_GRF_SOC_CON1_GMAC_CLK_SEL_25M 3 86 #define RK3288_GRF_SOC_CON1_RMII_CLK_SEL __BIT(11) 87 #define RK3288_GRF_SOC_CON1_RMII_CLK_SEL_25M 1 88 #define RK3288_GRF_SOC_CON1_RMII_CLK_SEL_2_5M 0 89 #define RK3288_GRF_SOC_CON1_GMAC_SPEED __BIT(10) 90 #define RK3288_GRF_SOC_CON1_GMAC_SPEED_10M 0 91 #define RK3288_GRF_SOC_CON1_GMAC_SPEED_100M 1 92 #define RK3288_GRF_SOC_CON1_GMAC_FLOWCTRL __BIT(9) 93 #define RK3288_GRF_SOC_CON1_GMAC_PHY_INTF_SEL __BITS(8,6) 94 #define RK3288_GRF_SOC_CON1_GMAC_PHY_INTF_SEL_RGMII 1 95 #define RK3288_GRF_SOC_CON1_GMAC_PHY_INTF_SEL_RMII 4 96 97 #define RK3288_GRF_SOC_CON3 0x0250 98 #define RK3288_GRF_SOC_CON3_RXCLK_DLY_ENA_GMAC __BIT(15) 99 #define RK3288_GRF_SOC_CON3_TXCLK_DLY_ENA_GMAC __BIT(14) 100 #define RK3288_GRF_SOC_CON3_CLK_RX_DL_CFG_GMAC __BITS(13,7) 101 #define RK3288_GRF_SOC_CON3_CLK_TX_DL_CFG_GMAC __BITS(6,0) 102 103 static void 104 rk3288_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay, bool set_delay) 105 { 106 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 107 uint32_t write_mask, write_val; 108 109 syscon_lock(rk_sc->sc_syscon); 110 111 write_mask = (RK3288_GRF_SOC_CON1_RMII_MODE | 112 RK3288_GRF_SOC_CON1_GMAC_PHY_INTF_SEL) << 16; 113 write_val = __SHIFTIN(RK3288_GRF_SOC_CON1_GMAC_PHY_INTF_SEL_RGMII, 114 RK3288_GRF_SOC_CON1_GMAC_PHY_INTF_SEL); 115 syscon_write_4(rk_sc->sc_syscon, RK3288_GRF_SOC_CON1, 116 write_mask | write_val); 117 118 if (set_delay) { 119 write_mask = (RK3288_GRF_SOC_CON3_RXCLK_DLY_ENA_GMAC | 120 RK3288_GRF_SOC_CON3_TXCLK_DLY_ENA_GMAC | 121 RK3288_GRF_SOC_CON3_CLK_RX_DL_CFG_GMAC | 122 RK3288_GRF_SOC_CON3_CLK_TX_DL_CFG_GMAC) << 16; 123 write_val = 0; 124 if (tx_delay) { 125 write_mask |= RK3288_GRF_SOC_CON3_TXCLK_DLY_ENA_GMAC | 126 __SHIFTIN(tx_delay, 127 RK3288_GRF_SOC_CON3_CLK_TX_DL_CFG_GMAC); 128 } 129 if (rx_delay) { 130 write_mask |= RK3288_GRF_SOC_CON3_RXCLK_DLY_ENA_GMAC | 131 __SHIFTIN(rx_delay, 132 RK3288_GRF_SOC_CON3_CLK_RX_DL_CFG_GMAC); 133 } 134 syscon_write_4(rk_sc->sc_syscon, RK3288_GRF_SOC_CON3, 135 write_mask | write_val); 136 } 137 138 syscon_unlock(rk_sc->sc_syscon); 139 } 140 141 static void 142 rk3288_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 143 { 144 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 145 uint32_t write_mask, write_val; 146 147 syscon_lock(rk_sc->sc_syscon); 148 149 write_mask = (RK3288_GRF_SOC_CON1_GMAC_CLK_SEL) << 16; 150 switch (speed) { 151 case IFM_10_T: 152 write_val = RK3288_GRF_SOC_CON1_GMAC_CLK_SEL_2_5M; 153 break; 154 case IFM_100_TX: 155 write_val = RK3288_GRF_SOC_CON1_GMAC_CLK_SEL_25M; 156 break; 157 case IFM_1000_T: 158 default: 159 write_val = RK3288_GRF_SOC_CON1_GMAC_CLK_SEL_125M; 160 break; 161 } 162 syscon_write_4(rk_sc->sc_syscon, RK3288_GRF_SOC_CON1, 163 write_mask | write_val); 164 165 syscon_unlock(rk_sc->sc_syscon); 166 } 167 168 /* 169 * RK3328 specific 170 */ 171 172 #define RK3328_GRF_MAC_CON0 0x0900 173 #define RK3328_GRF_MAC_CON0_RXDLY __BITS(13,7) 174 #define RK3328_GRF_MAC_CON0_TXDLY __BITS(6,0) 175 176 #define RK3328_GRF_MAC_CON1 0x0904 177 #define RK3328_GRF_MAC_CON1_CLKSEL __BITS(12,11) 178 #define RK3328_GRF_MAC_CON1_CLKSEL_125M 0 179 #define RK3328_GRF_MAC_CON1_CLKSEL_2_5M 2 180 #define RK3328_GRF_MAC_CON1_CLKSEL_25M 3 181 #define RK3328_GRF_MAC_CON1_MODE __BIT(9) 182 #define RK3328_GRF_MAC_CON1_SEL __BITS(6,4) 183 #define RK3328_GRF_MAC_CON1_SEL_RGMII 1 184 #define RK3328_GRF_MAC_CON1_RXDLY_EN __BIT(1) 185 #define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0) 186 187 static void 188 rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay, bool set_delay) 189 { 190 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 191 uint32_t write_mask, write_val; 192 193 syscon_lock(rk_sc->sc_syscon); 194 195 write_mask = (RK3328_GRF_MAC_CON1_MODE | RK3328_GRF_MAC_CON1_SEL) << 16; 196 write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII, 197 RK3328_GRF_MAC_CON1_SEL); 198 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 199 write_mask | write_val); 200 201 if (set_delay) { 202 write_mask = ( 203 RK3328_GRF_MAC_CON0_TXDLY | 204 RK3328_GRF_MAC_CON0_RXDLY) << 16; 205 write_val = 206 __SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) | 207 __SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY); 208 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON0, 209 write_mask | write_val); 210 211 write_mask = ( 212 RK3328_GRF_MAC_CON1_RXDLY_EN | 213 RK3328_GRF_MAC_CON1_TXDLY_EN) << 16; 214 write_val = 215 RK3328_GRF_MAC_CON1_RXDLY_EN | 216 RK3328_GRF_MAC_CON1_TXDLY_EN; 217 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 218 write_mask | write_val); 219 } 220 221 syscon_unlock(rk_sc->sc_syscon); 222 } 223 224 static void 225 rk3328_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 226 { 227 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 228 #if 0 229 u_int clksel; 230 231 switch (speed) { 232 case IFM_10_T: 233 clksel = RK3328_GRF_MAC_CON1_CLKSEL_2_5M; 234 break; 235 case IFM_100_TX: 236 clksel = RK3328_GRF_MAC_CON1_CLKSEL_25M; 237 break; 238 default: 239 clksel = RK3328_GRF_MAC_CON1_CLKSEL_125M; 240 break; 241 } 242 #endif 243 244 syscon_lock(rk_sc->sc_syscon); 245 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 246 (RK3328_GRF_MAC_CON1_CLKSEL << 16) | 247 __SHIFTIN(RK3328_GRF_MAC_CON1_CLKSEL_125M, RK3328_GRF_MAC_CON1_CLKSEL)); 248 syscon_unlock(rk_sc->sc_syscon); 249 } 250 251 /* 252 * RK3399 specific 253 */ 254 255 #define RK3399_GRF_SOC_CON5 0x0c214 256 #define RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL __BITS(11,9) 257 #define RK3399_GRF_SOC_CON5_GMAC_FLOWCTRL __BIT(8) 258 #define RK3399_GRF_SOC_CON5_GMAC_SPEED __BIT(7) 259 #define RK3399_GRF_SOC_CON5_RMII_MODE __BIT(6) 260 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL __BITS(5,4) 261 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_125M 0 262 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_25M 3 263 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_2_5M 2 264 #define RK3399_GRF_SOC_CON5_RMII_CLK_SEL __BIT(3) 265 #define RK3399_GRF_SOC_CON6 0x0c218 266 #define RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA __BIT(15) 267 #define RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG __BITS(14,8) 268 #define RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA __BIT(7) 269 #define RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG __BITS(6,0) 270 271 static void 272 rk3399_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, 273 u_int rx_delay, bool set_delay) 274 { 275 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 276 uint32_t write_mask, write_val; 277 278 syscon_lock(rk_sc->sc_syscon); 279 280 write_mask = ( 281 RK3399_GRF_SOC_CON5_RMII_MODE | 282 RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL) << 16; 283 write_val = __SHIFTIN(1, RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL); 284 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, 285 write_mask | write_val); 286 if (set_delay) { 287 write_mask = ( 288 RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA | 289 RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA | 290 RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG | 291 RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG) << 16; 292 write_val = 293 (tx_delay ? RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA : 0) | 294 (rx_delay ? RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA : 0) | 295 __SHIFTIN(rx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG) | 296 __SHIFTIN(tx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG); 297 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON6, 298 write_mask | write_val); 299 } 300 syscon_unlock(rk_sc->sc_syscon); 301 } 302 303 static void 304 rk3399_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 305 { 306 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 307 u_int clksel; 308 309 switch (speed) { 310 case IFM_10_T: 311 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_2_5M; 312 break; 313 case IFM_100_TX: 314 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_25M; 315 break; 316 default: 317 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_125M; 318 break; 319 } 320 321 const uint32_t con5_mask = 322 RK3399_GRF_SOC_CON5_GMAC_CLK_SEL << 16; 323 const uint32_t con5 = 324 __SHIFTIN(clksel, RK3399_GRF_SOC_CON5_GMAC_CLK_SEL); 325 326 syscon_lock(rk_sc->sc_syscon); 327 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, con5 | con5_mask); 328 syscon_unlock(rk_sc->sc_syscon); 329 } 330 331 static int 332 rk_gmac_reset(const int phandle) 333 { 334 struct fdtbus_gpio_pin *pin_reset; 335 const u_int *reset_delay_us; 336 bool reset_active_low; 337 int len; 338 339 if (!of_hasprop(phandle, "snps,reset-gpio")) 340 return 0; 341 342 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 343 if (pin_reset == NULL) 344 return ENOENT; 345 346 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 347 if (reset_delay_us == NULL || len != 12) 348 return ENXIO; 349 350 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 351 352 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 353 delay(be32toh(reset_delay_us[0])); 354 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 0 : 1); 355 delay(be32toh(reset_delay_us[1])); 356 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 357 delay(be32toh(reset_delay_us[2])); 358 359 return 0; 360 } 361 362 static int 363 rk_gmac_intr(void *arg) 364 { 365 return dwc_gmac_intr(arg); 366 } 367 368 static int 369 rk_gmac_setup_clocks(int phandle) 370 { 371 static const char * const clknames[] = { 372 #if 0 373 "stmmaceth", 374 "mac_clk_rx", 375 "mac_clk_tx", 376 "clk_mac_ref", 377 "clk_mac_refout", 378 "aclk_mac", 379 "pclk_mac" 380 #else 381 "stmmaceth", 382 "aclk_mac", 383 "pclk_mac", 384 "mac_clk_tx", 385 "mac_clk_rx" 386 #endif 387 }; 388 static const char * const rstnames[] = { 389 "stmmaceth" 390 }; 391 struct fdtbus_reset *rst; 392 struct clk *clk; 393 int error, n; 394 395 fdtbus_clock_assign(phandle); 396 397 for (n = 0; n < __arraycount(clknames); n++) { 398 clk = fdtbus_clock_get(phandle, clknames[n]); 399 if (clk == NULL) { 400 aprint_error(": couldn't get %s clock\n", clknames[n]); 401 return ENXIO; 402 } 403 error = clk_enable(clk); 404 if (error != 0) { 405 aprint_error(": couldn't enable %s clock: %d\n", 406 clknames[n], error); 407 return error; 408 } 409 } 410 411 for (n = 0; n < __arraycount(rstnames); n++) { 412 rst = fdtbus_reset_get(phandle, rstnames[n]); 413 if (rst == NULL) { 414 aprint_error(": couldn't get %s reset\n", rstnames[n]); 415 return ENXIO; 416 } 417 error = fdtbus_reset_deassert(rst); 418 if (error != 0) { 419 aprint_error(": couldn't de-assert %s reset: %d\n", 420 rstnames[n], error); 421 return error; 422 } 423 } 424 425 delay(5000); 426 427 return 0; 428 } 429 430 static int 431 rk_gmac_match(device_t parent, cfdata_t cf, void *aux) 432 { 433 struct fdt_attach_args * const faa = aux; 434 435 return of_compatible_match(faa->faa_phandle, compat_data); 436 } 437 438 static void 439 rk_gmac_attach(device_t parent, device_t self, void *aux) 440 { 441 struct rk_gmac_softc * const rk_sc = device_private(self); 442 struct dwc_gmac_softc * const sc = &rk_sc->sc_base; 443 struct fdt_attach_args * const faa = aux; 444 const int phandle = faa->faa_phandle; 445 const char *phy_mode; 446 char intrstr[128]; 447 bus_addr_t addr; 448 bus_size_t size; 449 u_int tx_delay, rx_delay; 450 #ifdef notyet 451 bool set_delay = true; 452 #else 453 bool set_delay = false; 454 #endif 455 456 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 457 aprint_error(": couldn't get registers\n"); 458 return; 459 } 460 461 rk_sc->sc_type = of_compatible_lookup(phandle, compat_data)->value; 462 463 rk_sc->sc_syscon = fdtbus_syscon_acquire(phandle, "rockchip,grf"); 464 if (rk_sc->sc_syscon == NULL) { 465 aprint_error(": couldn't get grf syscon\n"); 466 return; 467 } 468 469 if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0) { 470 tx_delay = RK_GMAC_TXDLY_DEFAULT; 471 set_delay = false; 472 } 473 474 if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0) { 475 rx_delay = RK_GMAC_RXDLY_DEFAULT; 476 set_delay = false; 477 } 478 479 sc->sc_dev = self; 480 sc->sc_bst = faa->faa_bst; 481 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 482 aprint_error(": couldn't map registers\n"); 483 return; 484 } 485 sc->sc_dmat = faa->faa_dmat; 486 487 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 488 aprint_error(": failed to decode interrupt\n"); 489 return; 490 } 491 492 if (rk_gmac_setup_clocks(phandle) != 0) 493 return; 494 495 if (rk_gmac_reset(phandle) != 0) 496 aprint_error_dev(self, "PHY reset failed\n"); 497 498 /* Rock64 seems to need more time for the reset to complete */ 499 delay(100000); 500 501 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 502 if (phy_mode == NULL) { 503 aprint_error(": missing 'phy-mode' property\n"); 504 return; 505 } 506 507 switch (rk_sc->sc_type) { 508 case GMAC_RK3288: 509 if (strncmp(phy_mode, "rgmii", 5) == 0) { 510 rk3288_gmac_set_mode_rgmii(sc, tx_delay, rx_delay, 511 set_delay); 512 513 sc->sc_set_speed = rk3288_gmac_set_speed_rgmii; 514 } else { 515 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 516 return; 517 } 518 break; 519 case GMAC_RK3328: 520 if (strncmp(phy_mode, "rgmii", 5) == 0) { 521 rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay, 522 set_delay); 523 524 sc->sc_set_speed = rk3328_gmac_set_speed_rgmii; 525 } else { 526 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 527 return; 528 } 529 break; 530 case GMAC_RK3399: 531 if (strncmp(phy_mode, "rgmii", 5) == 0) { 532 rk3399_gmac_set_mode_rgmii(sc, tx_delay, rx_delay, 533 set_delay); 534 535 sc->sc_set_speed = rk3399_gmac_set_speed_rgmii; 536 } else { 537 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 538 return; 539 } 540 break; 541 } 542 543 aprint_naive("\n"); 544 aprint_normal(": GMAC\n"); 545 546 dwc_gmac_preattach_fdt(phandle, sc); 547 548 if (dwc_gmac_attach(sc, MII_PHY_ANY, GMAC_MII_CLK_150_250M_DIV102) != 0) 549 return; 550 551 if (fdtbus_intr_establish_xname(phandle, 0, IPL_NET, 552 FDT_INTR_MPSAFE, rk_gmac_intr, sc, 553 device_xname(self)) == NULL) { 554 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 555 return; 556 } 557 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 558 } 559 560 CFATTACH_DECL_NEW(rk_gmac, sizeof(struct rk_gmac_softc), 561 rk_gmac_match, rk_gmac_attach, NULL, NULL); 562
Indexes created Sun Oct 25 00:26:45 UTC 2026