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  /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/
radeon_drm_surface.c 36 tileb = MIN2(surf->u.legacy.tile_split, tileb);
58 tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
151 surf_drm->bankw = surf_ws->u.legacy.bankw;
152 surf_drm->bankh = surf_ws->u.legacy.bankh;
153 surf_drm->mtilea = surf_ws->u.legacy.mtilea;
154 surf_drm->tile_split = surf_ws->u.legacy.tile_split;
157 surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->u.legacy.level[i],
160 surf_drm->tiling_index[i] = surf_ws->u.legacy.tiling_index[i];
164 surf_drm->stencil_tile_split = surf_ws->u.legacy.stencil_tile_split;
168 &surf_ws->u.legacy.stencil_level[i]
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
radeon_drm_surface.c 36 tileb = MIN2(surf->u.legacy.tile_split, tileb);
58 tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
151 surf_drm->bankw = surf_ws->u.legacy.bankw;
152 surf_drm->bankh = surf_ws->u.legacy.bankh;
153 surf_drm->mtilea = surf_ws->u.legacy.mtilea;
154 surf_drm->tile_split = surf_ws->u.legacy.tile_split;
157 surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->u.legacy.level[i],
160 surf_drm->tiling_index[i] = surf_ws->u.legacy.tiling_index[i];
164 surf_drm->stencil_tile_split = surf_ws->u.legacy.stencil_tile_split;
168 &surf_ws->u.legacy.zs.stencil_level[i]
    [all...]
radeon_drm_bo.c 904 surf->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
905 surf->u.legacy.bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
906 surf->u.legacy.tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
907 surf->u.legacy.tile_split = eg_tile_split(surf->u.legacy.tile_split);
908 surf->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
917 md->u.legacy.microtile = RADEON_LAYOUT_LINEAR;
918 md->u.legacy.macrotile = RADEON_LAYOUT_LINEAR;
920 md->u.legacy.microtile = RADEON_LAYOUT_TILED;
922 md->u.legacy.microtile = RADEON_LAYOUT_SQUARETILED
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
radeon_video.c 162 wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
177 surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
178 surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
179 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
180 surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split
    [all...]
r600_texture.c 180 *stride = rtex->surface.u.legacy.level[level].nblk_x *
182 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
183 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
186 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
190 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256 +
191 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
193 rtex->surface.u.legacy.level[level].nblk_x +
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
258 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
259 surface->u.legacy.level[0].slice_size_dw
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
radeon_video.c 162 wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
177 surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
178 surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
179 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
180 surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split
    [all...]
r600_texture.c 179 *stride = rtex->surface.u.legacy.level[level].nblk_x *
181 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
182 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
185 return rtex->surface.u.legacy.level[level].offset;
189 return rtex->surface.u.legacy.level[level].offset +
190 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
192 rtex->surface.u.legacy.level[level].nblk_x +
255 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
259 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
260 surface->u.legacy.level[0].slice_size_dw
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
radeon_video.c 151 wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
168 surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
169 surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
170 surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
171 surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split
    [all...]
radeon_vce_50.c 124 enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo
126 enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo
127 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
128 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
129 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
si_dma.c 98 unsigned dst_mode = sdst->surface.u.legacy.level[dst_level].mode;
105 unsigned index = tiled->surface.u.legacy.tiling_index[tiled_lvl];
114 assert(dst_mode != ssrc->surface.u.legacy.level[src_level].mode);
130 slice_tile_max = (tiled->surface.u.legacy.level[tiled_lvl].nblk_x *
131 tiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1;
137 height = tiled->surface.u.legacy.level[tiled_lvl].nblk_y;
138 base = tiled->surface.u.legacy.level[tiled_lvl].offset;
139 addr = linear->surface.u.legacy.level[linear_lvl].offset;
140 addr += (uint64_t)linear->surface.u.legacy.level[linear_lvl].slice_size_dw * 4 * linear_z;
146 tile_split = util_logbase2(tiled->surface.u.legacy.tile_split >> 6)
    [all...]
cik_sdma.c 81 unsigned tile_index = tex->surface.u.legacy.tiling_index[level];
82 unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index;
90 ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
111 sdst->surface.u.legacy.level[dst_level].offset;
113 ssrc->surface.u.legacy.level[src_level].offset;
114 unsigned dst_mode = sdst->surface.u.legacy.level[dst_level].mode;
115 unsigned src_mode = ssrc->surface.u.legacy.level[src_level].mode;
116 unsigned dst_tile_index = sdst->surface.u.legacy.tiling_index[dst_level];
117 unsigned src_tile_index = ssrc->surface.u.legacy.tiling_index[src_level];
126 unsigned dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x
    [all...]
si_texture.c 203 *stride = tex->surface.u.legacy.level[level].nblk_x *
205 assert((uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
206 *layer_stride = (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4;
209 return tex->surface.u.legacy.level[level].offset;
213 return tex->surface.u.legacy.level[level].offset +
214 box->z * (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4 +
216 tex->surface.u.legacy.level[level].nblk_x +
327 surface->u.legacy.level[0].nblk_x = pitch;
328 surface->u.legacy.level[0].slice_size_dw =
329 ((uint64_t)pitch * surface->u.legacy.level[0].nblk_y * bpe) / 4
    [all...]
si_clear.c 253 assert(tex->surface.u.legacy.level[level].dcc_fast_clear_size);
260 dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
261 clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
282 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
323 tex->surface.u.legacy.tiling_index[0] = 10;
326 tex->surface.u.legacy.tiling_index[0] = 14;
329 tex->surface.u.legacy.tiling_index[0] = 28;
340 tex->surface.u.legacy.tiling_index[0] = 10;
343 tex->surface.u.legacy.tiling_index[0] = 11;
346 tex->surface.u.legacy.tiling_index[0] = 12
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/jitter/
jit_pch.hpp 65 using FunctionPassManager = llvm::legacy::FunctionPassManager;
66 using PassManager = llvm::legacy::PassManager;
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/jitter/
jit_pch.hpp 60 using FunctionPassManager = llvm::legacy::FunctionPassManager;
61 using PassManager = llvm::legacy::PassManager;
  /xsrc/external/mit/MesaLib.old/dist/src/amd/common/
ac_surface.c 330 AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
332 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
346 surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
367 surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
369 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
453 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
466 tileb = MIN2(surf->u.legacy.tile_split, tileb);
513 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
518 surf->u.legacy.bankw = csio->pTileInfo->bankWidth
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
si_sdma_copy_image.c 56 unsigned tile_index = tex->surface.u.legacy.tiling_index[0];
57 unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index;
65 ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
229 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.legacy.level[0].offset_256B * 256;
230 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.legacy.level[0].offset_256B * 256;
231 unsigned dst_mode = sdst->surface.u.legacy.level[0].mode;
232 unsigned src_mode = ssrc->surface.u.legacy.level[0].mode;
233 unsigned dst_tile_index = sdst->surface.u.legacy.tiling_index[0];
234 unsigned src_tile_index = ssrc->surface.u.legacy.tiling_index[0];
241 unsigned dst_pitch = sdst->surface.u.legacy.level[0].nblk_x
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/amd/common/
ac_surface.c 619 AddrSurfInfoIn->basePitch = surf->u.legacy.zs.stencil_level[0].nblk_x;
621 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
633 surf_level = is_stencil ? &surf->u.legacy.zs.stencil_level[level] : &surf->u.legacy.level[level];
634 dcc_level = &surf->u.legacy.color.dcc_level[level];
657 surf->u.legacy.zs.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
659 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
784 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
797 tileb = MIN2(surf->u.legacy.tile_split, tileb);
847 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
radv_amdgpu_bo.c 664 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
666 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
671 tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config);
672 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw));
673 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->u.legacy.bankh));
674 if (md->u.legacy.tile_split)
675 tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, radv_eg_tile_split_rev(md->u.legacy.tile_split));
676 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea));
677 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks)-1);
679 if (md->u.legacy.scanout
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
radv_image.c 282 return plane->surface.u.legacy.stencil_tiling_index[level];
284 return plane->surface.u.legacy.tiling_index[level];
716 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
730 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
748 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
750 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
752 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
radeon_vce_50.c 121 (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo
123 (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo
124 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
125 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
126 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
radeon_vce_40_2_2.c 85 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
86 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
87 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw
311 (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo
313 (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo
314 RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
315 RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
316 RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
radv_image.c 120 return info->bo_metadata->u.legacy.scanout;
433 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
434 surface->u.legacy.bankw = md->u.legacy.bankw;
435 surface->u.legacy.bankh = md->u.legacy.bankh;
436 surface->u.legacy.tile_split = md->u.legacy.tile_split;
437 surface->u.legacy.mtilea = md->u.legacy.mtilea
    [all...]
  /xsrc/external/mit/MesaLib/dist/.gitlab-ci/
crosvm-runner.sh 27 /usr/sbin/iptables-legacy -t nat -A POSTROUTING -o eth0 -j MASQUERADE
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
radv_amdgpu_bo.c 926 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
928 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
933 tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config);
934 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw));
935 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->u.legacy.bankh));
936 if (md->u.legacy.tile_split)
938 AMDGPU_TILING_SET(TILE_SPLIT, radv_eg_tile_split_rev(md->u.legacy.tile_split));
939 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea));
940 tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks) - 1);
942 if (md->u.legacy.scanout
    [all...]

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