1 /* $NetBSD: bus_dma.c,v 1.61 2026/09/28 20:41:01 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #define _POWERPC_BUS_DMA_PRIVATE 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.61 2026/09/28 20:41:01 rkujawa Exp $"); 37 38 #ifdef _KERNEL_OPT 39 #include "opt_ppcarch.h" 40 #endif 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/kmem.h> 47 #include <sys/proc.h> 48 #include <sys/mbuf.h> 49 #include <sys/bus.h> 50 #include <sys/intr.h> 51 52 #include <uvm/uvm.h> 53 #include <uvm/uvm_physseg.h> 54 55 #if defined(PPC_BOOKE) 56 #define EIEIO __asm volatile("mbar\t0" ::: "memory") 57 #define SYNC __asm volatile("msync" ::: "memory") 58 #elif defined(PPC_IBM4XX) && !defined(PPC_IBM440) 59 /* eieio is implemented as sync */ 60 #define EIEIO __asm volatile("eieio" ::: "memory") 61 #define SYNC /* nothing */ 62 #else 63 #define EIEIO __asm volatile("eieio" ::: "memory") 64 #define SYNC __asm volatile("sync" ::: "memory") 65 #endif 66 67 int _bus_dmamap_load_buffer (bus_dma_tag_t, bus_dmamap_t, void *, 68 bus_size_t, struct vmspace *, int, paddr_t *, int *, int); 69 70 static inline void 71 dcbst(paddr_t pa, long len, int dcache_line_size) 72 { 73 paddr_t epa; 74 for (epa = pa + len; pa < epa; pa += dcache_line_size) 75 __asm volatile("dcbst 0,%0" :: "r"(pa) : "memory"); 76 } 77 78 static inline void 79 dcbi(paddr_t pa, long len, int dcache_line_size) 80 { 81 paddr_t epa; 82 for (epa = pa + len; pa < epa; pa += dcache_line_size) 83 __asm volatile("dcbi 0,%0" :: "r"(pa) : "memory"); 84 } 85 86 static inline void 87 dcbf(paddr_t pa, long len, int dcache_line_size) 88 { 89 paddr_t epa; 90 for (epa = pa + len; pa < epa; pa += dcache_line_size) 91 __asm volatile("dcbf 0,%0" :: "r"(pa) : "memory"); 92 } 93 94 /* 95 * Common function for DMA map creation. May be called by bus-specific 96 * DMA map creation functions. 97 */ 98 int 99 _bus_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp) 100 { 101 struct powerpc_bus_dmamap *map; 102 void *mapstore; 103 size_t mapsize; 104 105 /* 106 * Allocate and initialize the DMA map. The end of the map 107 * is a variable-sized array of segments, so we allocate enough 108 * room for them in one shot. 109 * 110 * Note we don't preserve the WAITOK or NOWAIT flags. Preservation 111 * of ALLOCNOW notifies others that we've reserved these resources, 112 * and they are not to be freed. 113 * 114 * The bus_dmamap_t includes one bus_dma_segment_t, hence 115 * the (nsegments - 1). 116 */ 117 mapsize = sizeof(*map) + sizeof(bus_dma_segment_t [nsegments - 1]); 118 if ((mapstore = kmem_intr_alloc(mapsize, 119 (flags & BUS_DMA_NOWAIT) ? KM_NOSLEEP : KM_SLEEP)) == NULL) 120 return (ENOMEM); 121 122 memset(mapstore, 0, mapsize); 123 map = (struct powerpc_bus_dmamap *)mapstore; 124 map->_dm_size = size; 125 map->_dm_segcnt = nsegments; 126 map->_dm_maxmaxsegsz = maxsegsz; 127 map->_dm_boundary = boundary; 128 map->_dm_bounce_thresh_min = t->_bounce_thresh_min; 129 map->_dm_bounce_thresh_max = t->_bounce_thresh_max; 130 map->_dm_flags = flags & ~(BUS_DMA_WAITOK|BUS_DMA_NOWAIT); 131 map->dm_maxsegsz = maxsegsz; 132 map->dm_mapsize = 0; /* no valid mappings */ 133 map->dm_nsegs = 0; 134 135 *dmamp = map; 136 return (0); 137 } 138 139 /* 140 * Common function for DMA map destruction. May be called by bus-specific 141 * DMA map destruction functions. 142 */ 143 void 144 _bus_dmamap_destroy(bus_dma_tag_t t, bus_dmamap_t map) 145 { 146 147 size_t mapsize = sizeof(*map) 148 + sizeof(bus_dma_segment_t [map->_dm_segcnt - 1]); 149 kmem_intr_free(map, mapsize); 150 } 151 152 /* 153 * Utility function to load a linear buffer. lastaddrp holds state 154 * between invocations (for multiple-buffer loads). segp contains 155 * the starting segment on entrance, and the ending segment on exit. 156 * first indicates if this is the first invocation of this function. 157 */ 158 int 159 _bus_dmamap_load_buffer(bus_dma_tag_t t, bus_dmamap_t map, void *buf, bus_size_t buflen, struct vmspace *vm, int flags, paddr_t *lastaddrp, int *segp, int first) 160 { 161 bus_size_t sgsize; 162 bus_addr_t curaddr, lastaddr, baddr, bmask; 163 vaddr_t vaddr = (vaddr_t)buf; 164 int seg; 165 166 // printf("%s(%p,%p,%p,%u,%p,%#x,%p,%p,%u)\n", __func__, 167 // t, map, buf, buflen, vm, flags, lastaddrp, segp, first); 168 169 lastaddr = *lastaddrp; 170 bmask = ~(map->_dm_boundary - 1); 171 172 for (seg = *segp; buflen > 0 ; ) { 173 /* 174 * Get the physical address for this segment. 175 */ 176 if (!VMSPACE_IS_KERNEL_P(vm)) 177 (void) pmap_extract(vm_map_pmap(&vm->vm_map), 178 vaddr, (void *)&curaddr); 179 else 180 curaddr = vtophys(vaddr); 181 182 /* 183 * If we're beyond the bounce threshold, notify 184 * the caller. 185 */ 186 if (map->_dm_bounce_thresh_min != 0 && 187 curaddr < map->_dm_bounce_thresh_min) 188 return (EINVAL); 189 if (map->_dm_bounce_thresh_max != 0 && 190 curaddr >= map->_dm_bounce_thresh_max) 191 return (EINVAL); 192 193 /* 194 * Compute the segment size, and adjust counts. 195 */ 196 sgsize = PAGE_SIZE - ((u_long)vaddr & PGOFSET); 197 if (buflen < sgsize) 198 sgsize = buflen; 199 sgsize = uimin(sgsize, map->dm_maxsegsz); 200 201 /* 202 * Make sure we don't cross any boundaries. 203 */ 204 if (map->_dm_boundary > 0) { 205 baddr = (curaddr + map->_dm_boundary) & bmask; 206 if (sgsize > (baddr - curaddr)) 207 sgsize = (baddr - curaddr); 208 } 209 210 /* 211 * Insert chunk into a segment, coalescing with 212 * the previous segment if possible. 213 */ 214 if (first) { 215 map->dm_segs[seg].ds_addr = PHYS_TO_BUS_MEM(t, curaddr); 216 map->dm_segs[seg].ds_len = sgsize; 217 first = 0; 218 } else { 219 if (curaddr == lastaddr && 220 (map->dm_segs[seg].ds_len + sgsize) <= 221 map->dm_maxsegsz && 222 (map->_dm_boundary == 0 || 223 (map->dm_segs[seg].ds_addr & bmask) == 224 (PHYS_TO_BUS_MEM(t, curaddr) & bmask))) 225 map->dm_segs[seg].ds_len += sgsize; 226 else { 227 if (++seg >= map->_dm_segcnt) 228 break; 229 map->dm_segs[seg].ds_addr = 230 PHYS_TO_BUS_MEM(t, curaddr); 231 map->dm_segs[seg].ds_len = sgsize; 232 } 233 } 234 235 lastaddr = curaddr + sgsize; 236 vaddr += sgsize; 237 buflen -= sgsize; 238 } 239 240 *segp = seg; 241 *lastaddrp = lastaddr; 242 243 /* 244 * Did we fit? 245 */ 246 if (buflen != 0) 247 return (EFBIG); /* XXX better return value here? */ 248 249 return (0); 250 } 251 252 /* 253 * Common function for loading a DMA map with a linear buffer. May 254 * be called by bus-specific DMA map load functions. 255 */ 256 int 257 _bus_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, void *buf, bus_size_t buflen, struct proc *p, int flags) 258 { 259 paddr_t lastaddr = 0; 260 int seg, error; 261 struct vmspace *vm; 262 263 /* 264 * Make sure that on error condition we return "no valid mappings". 265 */ 266 map->dm_mapsize = 0; 267 map->dm_nsegs = 0; 268 KASSERT(map->dm_maxsegsz <= map->_dm_maxmaxsegsz); 269 270 if (buflen > map->_dm_size) 271 return (EINVAL); 272 273 if (p != NULL) { 274 vm = p->p_vmspace; 275 } else { 276 vm = vmspace_kernel(); 277 } 278 279 seg = 0; 280 error = _bus_dmamap_load_buffer(t, map, buf, buflen, vm, flags, 281 &lastaddr, &seg, 1); 282 if (error == 0) { 283 map->dm_mapsize = buflen; 284 map->dm_nsegs = seg + 1; 285 } 286 return (error); 287 } 288 289 /* 290 * Like _bus_dmamap_load(), but for mbufs. 291 */ 292 int 293 _bus_dmamap_load_mbuf(bus_dma_tag_t t, bus_dmamap_t map, struct mbuf *m0, int flags) 294 { 295 paddr_t lastaddr = 0; 296 int seg, error, first; 297 struct mbuf *m; 298 299 /* 300 * Make sure that on error condition we return "no valid mappings." 301 */ 302 map->dm_mapsize = 0; 303 map->dm_nsegs = 0; 304 KASSERT(map->dm_maxsegsz <= map->_dm_maxmaxsegsz); 305 306 #ifdef DIAGNOSTIC 307 if ((m0->m_flags & M_PKTHDR) == 0) 308 panic("_bus_dmamap_load_mbuf: no packet header"); 309 #endif 310 311 if (m0->m_pkthdr.len > map->_dm_size) 312 return (EINVAL); 313 314 first = 1; 315 seg = 0; 316 error = 0; 317 for (m = m0; m != NULL && error == 0; m = m->m_next, first = 0) { 318 if (m->m_len == 0) 319 continue; 320 #ifdef POOL_VTOPHYS 321 /* XXX Could be better about coalescing. */ 322 /* XXX Doesn't check boundaries. */ 323 switch (m->m_flags & (M_EXT|M_EXT_CLUSTER)) { 324 case M_EXT|M_EXT_CLUSTER: 325 /* XXX KDASSERT */ 326 KASSERT(m->m_ext.ext_paddr != M_PADDR_INVALID); 327 lastaddr = m->m_ext.ext_paddr + 328 (m->m_data - m->m_ext.ext_buf); 329 have_addr: 330 /* 331 * If we're beyond the bounce threshold, notify 332 * the caller. 333 */ 334 if (map->_dm_bounce_thresh_min != 0 && 335 lastaddr < map->_dm_bounce_thresh_min) { 336 error = EINVAL; 337 continue; 338 } 339 if (map->_dm_bounce_thresh_max != 0 && 340 lastaddr >= map->_dm_bounce_thresh_max) { 341 error = EINVAL; 342 continue; 343 } 344 if (first == 0 && ++seg >= map->_dm_segcnt) { 345 error = EFBIG; 346 continue; 347 } 348 map->dm_segs[seg].ds_addr = 349 PHYS_TO_BUS_MEM(t, lastaddr); 350 map->dm_segs[seg].ds_len = m->m_len; 351 lastaddr += m->m_len; 352 continue; 353 354 case 0: 355 lastaddr = m->m_paddr + M_BUFOFFSET(m) + 356 (m->m_data - M_BUFADDR(m)); 357 goto have_addr; 358 359 default: 360 break; 361 } 362 #endif 363 error = _bus_dmamap_load_buffer(t, map, m->m_data, 364 m->m_len, vmspace_kernel(), flags, &lastaddr, &seg, first); 365 } 366 if (error == 0) { 367 map->dm_mapsize = m0->m_pkthdr.len; 368 map->dm_nsegs = seg + 1; 369 } 370 return (error); 371 } 372 373 /* 374 * Like _bus_dmamap_load(), but for uios. 375 */ 376 int 377 _bus_dmamap_load_uio(bus_dma_tag_t t, bus_dmamap_t map, struct uio *uio, int flags) 378 { 379 paddr_t lastaddr = 0; 380 int seg, i, error, first; 381 bus_size_t minlen, resid; 382 struct iovec *iov; 383 void *addr; 384 385 /* 386 * Make sure that on error condition we return "no valid mappings." 387 */ 388 map->dm_mapsize = 0; 389 map->dm_nsegs = 0; 390 KASSERT(map->dm_maxsegsz <= map->_dm_maxmaxsegsz); 391 392 resid = uio->uio_resid; 393 iov = uio->uio_iov; 394 395 first = 1; 396 seg = 0; 397 error = 0; 398 for (i = 0; i < uio->uio_iovcnt && resid != 0 && error == 0; i++) { 399 /* 400 * Now at the first iovec to load. Load each iovec 401 * until we have exhausted the residual count. 402 */ 403 minlen = resid < iov[i].iov_len ? resid : iov[i].iov_len; 404 addr = (void *)iov[i].iov_base; 405 406 error = _bus_dmamap_load_buffer(t, map, addr, minlen, 407 uio->uio_vmspace, flags, &lastaddr, &seg, first); 408 first = 0; 409 410 resid -= minlen; 411 } 412 if (error == 0) { 413 map->dm_mapsize = uio->uio_resid; 414 map->dm_nsegs = seg + 1; 415 } 416 return (error); 417 } 418 419 /* 420 * Like _bus_dmamap_load(), but for raw memory allocated with 421 * bus_dmamem_alloc(). 422 * 423 * XXX This is too much copypasta of _bus_dmamap_load_buffer. 424 */ 425 int 426 _bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map, 427 bus_dma_segment_t *segs, int nsegs, bus_size_t size, int flags) 428 { 429 bus_size_t sgsize, isgsize; 430 bus_size_t busaddr, curaddr, lastaddr, baddr, bmask; 431 int seg, iseg, first; 432 bus_size_t size0 = size; 433 434 if (size == 0) 435 return 0; 436 437 lastaddr = 0; 438 bmask = ~(map->_dm_boundary - 1); 439 440 first = 1; 441 iseg = 0; 442 busaddr = segs[iseg].ds_addr; 443 isgsize = segs[iseg].ds_len; 444 for (seg = 0; size > 0;) { 445 /* 446 * Get the physical address for this segment. 447 */ 448 curaddr = BUS_MEM_TO_PHYS(t, busaddr); 449 450 /* 451 * If we're beyond the bounce threshold, notify 452 * the caller. 453 */ 454 if (map->_dm_bounce_thresh_min != 0 && 455 curaddr < map->_dm_bounce_thresh_min) 456 return EINVAL; 457 if (map->_dm_bounce_thresh_max != 0 && 458 curaddr >= map->_dm_bounce_thresh_max) 459 return EINVAL; 460 461 /* 462 * Compute the segment size, and adjust counts. 463 */ 464 sgsize = PAGE_SIZE - ((u_long)curaddr & PGOFSET); 465 sgsize = MIN(sgsize, isgsize); 466 sgsize = MIN(sgsize, size); 467 sgsize = MIN(sgsize, map->dm_maxsegsz); 468 469 /* 470 * Make sure we don't cross any boundaries. 471 */ 472 if (map->_dm_boundary > 0) { 473 baddr = (curaddr + map->_dm_boundary) & bmask; 474 if (sgsize > (baddr - curaddr)) 475 sgsize = (baddr - curaddr); 476 } 477 478 /* 479 * Insert chunk into a segment, coalescing with 480 * the previous segment if possible. 481 */ 482 if (first) { 483 map->dm_segs[seg].ds_addr = 484 PHYS_TO_BUS_MEM(t, curaddr); 485 map->dm_segs[seg].ds_len = sgsize; 486 first = 0; 487 } else { 488 if (curaddr == lastaddr && 489 (map->dm_segs[seg].ds_len + sgsize) <= 490 map->dm_maxsegsz && 491 (map->_dm_boundary == 0 || 492 (map->dm_segs[seg].ds_addr & bmask) == 493 (PHYS_TO_BUS_MEM(t, curaddr) & bmask))) 494 map->dm_segs[seg].ds_len += sgsize; 495 else { 496 if (++seg >= map->_dm_segcnt) 497 break; 498 map->dm_segs[seg].ds_addr = 499 PHYS_TO_BUS_MEM(t, curaddr); 500 map->dm_segs[seg].ds_len = sgsize; 501 } 502 } 503 504 lastaddr = curaddr + sgsize; 505 busaddr += sgsize; 506 size -= sgsize; 507 if ((isgsize -= sgsize) == 0) { 508 if (++iseg == nsegs) { 509 ++seg; 510 break; 511 } 512 KASSERT(iseg < nsegs); 513 busaddr = segs[iseg].ds_addr; 514 isgsize = segs[iseg].ds_len; 515 } 516 } 517 518 if (size > 0) { 519 map->dm_nsegs = 0; 520 map->dm_mapsize = 0; 521 return EFBIG; 522 } 523 524 map->dm_nsegs = seg; 525 map->dm_mapsize = size0; 526 527 return 0; 528 } 529 530 /* 531 * Common function for unloading a DMA map. May be called by 532 * chipset-specific DMA map unload functions. 533 */ 534 void 535 _bus_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t map) 536 { 537 538 /* 539 * No resources to free; just mark the mappings as 540 * invalid. 541 */ 542 map->dm_maxsegsz = map->_dm_maxmaxsegsz; 543 map->dm_mapsize = 0; 544 map->dm_nsegs = 0; 545 } 546 547 /* 548 * Common function for DMA map synchronization. May be called 549 * by chipset-specific DMA map synchronization functions. 550 */ 551 void 552 _bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, bus_size_t len, int ops) 553 { 554 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size; 555 const bus_dma_segment_t *ds = map->dm_segs; 556 557 // printf("%s(%p,%p,%#x,%u,%#x) from %p\n", __func__, 558 // t, map, offset, len, ops, __builtin_return_address(0)); 559 560 if ((ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) != 0 && 561 (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) != 0) 562 panic("_bus_dmamap_sync: invalid ops %#x", ops); 563 564 #ifdef DIAGNOSTIC 565 if (offset + len > map->dm_mapsize) 566 panic("%s: ops %#x mapsize %u: bad offset (%u) and/or length (%u)", __func__, ops, map->dm_mapsize, offset, len); 567 #endif 568 569 /* 570 * Skip leading amount 571 */ 572 while (offset >= ds->ds_len) { 573 offset -= ds->ds_len; 574 ds++; 575 } 576 EIEIO; 577 for (; len > 0; ds++, offset = 0) { 578 bus_size_t seglen = ds->ds_len - offset; 579 bus_addr_t addr = BUS_MEM_TO_PHYS(t, ds->ds_addr) + offset; 580 if (seglen > len) 581 seglen = len; 582 len -= seglen; 583 KASSERT(ds < &map->dm_segs[map->dm_nsegs]); 584 /* 585 * Readjust things to start on cacheline boundarys 586 */ 587 offset = (addr & (dcache_line_size-1)); 588 seglen += offset; 589 addr -= offset; 590 /* 591 * Now do the appropriate thing. 592 */ 593 switch (ops) { 594 case BUS_DMASYNC_PREWRITE: 595 /* 596 * Make sure cache contents are in memory for the DMA. 597 */ 598 dcbst(addr, seglen, dcache_line_size); 599 break; 600 case BUS_DMASYNC_PREREAD: 601 /* 602 * If the region to be invalidated doesn't fall on 603 * cacheline boundary, flush that cacheline so we 604 * preserve the leading content. 605 */ 606 if (offset) { 607 dcbf(addr, 1, 1); 608 /* 609 * If we are doing <= one cache line, stop now. 610 */ 611 if (seglen <= dcache_line_size) 612 break; 613 /* 614 * Advance one cache line since we've flushed 615 * this one. 616 */ 617 addr += dcache_line_size; 618 seglen -= dcache_line_size; 619 } 620 /* 621 * If the byte after the region to be invalidated 622 * doesn't fall on cacheline boundary, flush that 623 * cacheline so we preserve the trailing content. 624 */ 625 if (seglen & (dcache_line_size-1)) { 626 dcbf(addr + seglen, 1, 1); 627 if (seglen <= dcache_line_size) 628 break; 629 /* 630 * Truncate the length to a multiple of a 631 * dcache line size. No reason to flush 632 * the last entry again. 633 */ 634 seglen &= ~(dcache_line_size - 1); 635 } 636 SYNC; /* is this needed? */ 637 EIEIO; /* is this needed? */ 638 /* FALLTHROUGH */ 639 case BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE: 640 case BUS_DMASYNC_POSTREAD: 641 /* 642 * The contents will have changed, make sure to remove 643 * them from the cache. Note: some implementation 644 * implement dcbi identically to dcbf. Thus if the 645 * cacheline has data, it will be written to memory. 646 * If the DMA is updating the same cacheline at the 647 * time, bad things can happen. 648 */ 649 dcbi(addr, seglen, dcache_line_size); 650 break; 651 case BUS_DMASYNC_POSTWRITE: 652 /* 653 * Do nothing. 654 */ 655 break; 656 case BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE: 657 /* 658 * Force it to memory and remove from cache. 659 */ 660 dcbf(addr, seglen, dcache_line_size); 661 break; 662 } 663 } 664 __asm volatile("sync"); 665 } 666 667 /* 668 * Common function for DMA-safe memory allocation. May be called 669 * by bus-specific DMA memory allocation functions. 670 */ 671 int 672 _bus_dmamem_alloc(bus_dma_tag_t t, bus_size_t size, bus_size_t alignment, bus_size_t boundary, bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags) 673 { 674 paddr_t start = 0xffffffff, end = 0; 675 uvm_physseg_t bank; 676 677 for (bank = uvm_physseg_get_first(); 678 uvm_physseg_valid_p(bank); 679 bank = uvm_physseg_get_next(bank)) { 680 if (start > ptoa(uvm_physseg_get_avail_start(bank))) 681 start = ptoa(uvm_physseg_get_avail_start(bank)); 682 if (end < ptoa(uvm_physseg_get_avail_end(bank))) 683 end = ptoa(uvm_physseg_get_avail_end(bank)); 684 } 685 686 return _bus_dmamem_alloc_range(t, size, alignment, boundary, segs, 687 nsegs, rsegs, flags, start, end - PAGE_SIZE); 688 } 689 690 /* 691 * Common function for freeing DMA-safe memory. May be called by 692 * bus-specific DMA memory free functions. 693 */ 694 void 695 _bus_dmamem_free(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs) 696 { 697 struct vm_page *m; 698 bus_addr_t addr; 699 struct pglist mlist; 700 int curseg; 701 702 /* 703 * Build a list of pages to free back to the VM system. 704 */ 705 TAILQ_INIT(&mlist); 706 for (curseg = 0; curseg < nsegs; curseg++) { 707 for (addr = BUS_MEM_TO_PHYS(t, segs[curseg].ds_addr); 708 addr < (BUS_MEM_TO_PHYS(t, segs[curseg].ds_addr) 709 + segs[curseg].ds_len); 710 addr += PAGE_SIZE) { 711 m = PHYS_TO_VM_PAGE(addr); 712 TAILQ_INSERT_TAIL(&mlist, m, pageq.queue); 713 } 714 } 715 716 uvm_pglistfree(&mlist); 717 } 718 719 /* 720 * Apparently, this code was written with the assumption that OEA PowerPC 721 * have bus snooping, and that the DMA_MAP_COHERENT can be a no-op. 722 * 723 * The 4xx, (at least some) BookE and few OEA (Wii) cores have no DMA bus 724 * snooping, so a coherent mapping has to be made cache-inhibited... 725 * 726 * Truth is, this needs a proper refactor (perhaps using tags like arm). 727 */ 728 #if defined(PPC_IBM4XX) /* || defined(PPC_BOOKE) */ 729 #define PPC_DMAMEM_UNCACHED(flags) \ 730 (((flags) & (BUS_DMA_DONTCACHE | BUS_DMA_COHERENT)) != 0) 731 #else 732 #define PPC_DMAMEM_UNCACHED(flags) (((flags) & BUS_DMA_DONTCACHE) != 0) 733 #endif 734 735 /* 736 * Common function for mapping DMA-safe memory. May be called by 737 * bus-specific DMA memory map functions. 738 */ 739 int 740 _bus_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs, size_t size, void **kvap, int flags) 741 { 742 vaddr_t va; 743 bus_addr_t addr; 744 int curseg; 745 const uvm_flag_t kmflags = 746 (flags & BUS_DMA_NOWAIT) != 0 ? UVM_KMF_NOWAIT : 0; 747 748 size = round_page(size); 749 750 #ifdef PMAP_MAP_POOLPAGE 751 /* 752 * If we are mapping a cacheable physically contiguous segment, treat 753 * it as if we are mapping a poolpage and avoid consuming any KVAs. 754 */ 755 if (nsegs == 1 && !PPC_DMAMEM_UNCACHED(flags)) { 756 KASSERT(size == segs->ds_len); 757 addr = BUS_MEM_TO_PHYS(t, segs->ds_addr); 758 if (__predict_true(addr + size < PMAP_DIRECT_MAPPED_LEN)) { 759 *kvap = (void *)PMAP_MAP_POOLPAGE(addr); 760 return 0; 761 } 762 } 763 #endif 764 765 va = uvm_km_alloc(kernel_map, size, 0, UVM_KMF_VAONLY | kmflags); 766 767 if (va == 0) 768 return (ENOMEM); 769 770 *kvap = (void *)va; 771 772 for (curseg = 0; curseg < nsegs; curseg++) { 773 for (addr = BUS_MEM_TO_PHYS(t, segs[curseg].ds_addr); 774 addr < (BUS_MEM_TO_PHYS(t, segs[curseg].ds_addr) 775 + segs[curseg].ds_len); 776 addr += PAGE_SIZE, va += PAGE_SIZE, size -= PAGE_SIZE) { 777 if (size == 0) 778 panic("_bus_dmamem_map: size botch"); 779 /* 780 * If we are mapping uncached, flush the page from 781 * cache before we map it. 782 */ 783 if (PPC_DMAMEM_UNCACHED(flags)) 784 dcbf(addr, PAGE_SIZE, 785 curcpu()->ci_ci.dcache_line_size); 786 pmap_kenter_pa(va, addr, 787 VM_PROT_READ | VM_PROT_WRITE, 788 PMAP_WIRED | 789 (PPC_DMAMEM_UNCACHED(flags) ? PMAP_NOCACHE : 0)); 790 } 791 } 792 793 return (0); 794 } 795 796 /* 797 * Common function for unmapping DMA-safe memory. May be called by 798 * bus-specific DMA memory unmapping functions. 799 */ 800 void 801 _bus_dmamem_unmap(bus_dma_tag_t t, void *kva, size_t size) 802 { 803 vaddr_t va = (vaddr_t) kva; 804 805 #ifdef DIAGNOSTIC 806 if (va & PGOFSET) 807 panic("_bus_dmamem_unmap"); 808 #endif 809 810 if (va >= VM_MIN_KERNEL_ADDRESS && va < VM_MAX_KERNEL_ADDRESS) { 811 size = round_page(size); 812 pmap_kremove(va, size); 813 uvm_km_free(kernel_map, va, size, UVM_KMF_VAONLY); 814 } 815 } 816 817 /* 818 * Common function for mmap(2)'ing DMA-safe memory. May be called by 819 * bus-specific DMA mmap(2)'ing functions. 820 */ 821 paddr_t 822 _bus_dmamem_mmap(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs, off_t off, int prot, int flags) 823 { 824 int i; 825 826 for (i = 0; i < nsegs; i++) { 827 #ifdef DIAGNOSTIC 828 if (off & PGOFSET) 829 panic("_bus_dmamem_mmap: offset unaligned"); 830 if (BUS_MEM_TO_PHYS(t, segs[i].ds_addr) & PGOFSET) 831 panic("_bus_dmamem_mmap: segment unaligned"); 832 if (segs[i].ds_len & PGOFSET) 833 panic("_bus_dmamem_mmap: segment size not multiple" 834 " of page size"); 835 #endif 836 if (off >= segs[i].ds_len) { 837 off -= segs[i].ds_len; 838 continue; 839 } 840 841 paddr_t mmapcookie = 842 BUS_MEM_TO_PHYS(t, segs[i].ds_addr) + off; 843 #if defined(PPC_IBM4XX) 844 /* 845 * This probably could be the default on OEA too, 846 * requires more testing. 847 */ 848 if (!PPC_DMAMEM_UNCACHED(flags)) 849 mmapcookie |= POWERPC_MMAP_FLAG_CACHEABLE; 850 #endif 851 return (mmapcookie); 852 } 853 854 /* Page not found. */ 855 return (-1); 856 } 857 858 /* 859 * Allocate physical memory from the given physical address range. 860 * Called by DMA-safe memory allocation methods. 861 */ 862 int 863 _bus_dmamem_alloc_range( 864 bus_dma_tag_t t, 865 bus_size_t size, 866 bus_size_t alignment, 867 bus_size_t boundary, 868 bus_dma_segment_t *segs, 869 int nsegs, 870 int *rsegs, 871 int flags, 872 paddr_t low, 873 paddr_t high) 874 { 875 paddr_t curaddr, lastaddr; 876 struct vm_page *m; 877 struct pglist mlist; 878 int curseg, error; 879 880 /* Always round the size. */ 881 size = round_page(size); 882 883 /* 884 * Allocate pages from the VM system. 885 */ 886 error = uvm_pglistalloc(size, low, high, alignment, boundary, 887 &mlist, nsegs, (flags & BUS_DMA_NOWAIT) == 0); 888 if (error) 889 return (error); 890 891 /* 892 * Compute the location, size, and number of segments actually 893 * returned by the VM code. 894 */ 895 m = mlist.tqh_first; 896 curseg = 0; 897 lastaddr = VM_PAGE_TO_PHYS(m); 898 segs[curseg].ds_addr = PHYS_TO_BUS_MEM(t, lastaddr); 899 segs[curseg].ds_len = PAGE_SIZE; 900 m = m->pageq.queue.tqe_next; 901 902 for (; m != NULL; m = m->pageq.queue.tqe_next) { 903 curaddr = VM_PAGE_TO_PHYS(m); 904 #ifdef DIAGNOSTIC 905 if (curaddr < low || curaddr >= high) { 906 printf("vm_page_alloc_memory returned non-sensical" 907 " address 0x%lx\n", curaddr); 908 panic("_bus_dmamem_alloc_range"); 909 } 910 #endif 911 if (curaddr == (lastaddr + PAGE_SIZE)) 912 segs[curseg].ds_len += PAGE_SIZE; 913 else { 914 curseg++; 915 segs[curseg].ds_addr = PHYS_TO_BUS_MEM(t, curaddr); 916 segs[curseg].ds_len = PAGE_SIZE; 917 } 918 lastaddr = curaddr; 919 } 920 921 *rsegs = curseg + 1; 922 923 return (0); 924 } 925 926 /* 927 * Generic form of PHYS_TO_BUS_MEM(). 928 */ 929 bus_addr_t 930 _bus_dma_phys_to_bus_mem_generic(bus_dma_tag_t t, bus_addr_t addr) 931 { 932 933 return (addr); 934 } 935 936 /* 937 * Generic form of BUS_MEM_TO_PHYS(). 938 */ 939 bus_addr_t 940 _bus_dma_bus_mem_to_phys_generic(bus_dma_tag_t t, bus_addr_t addr) 941 { 942 943 return (addr); 944 } 945