| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/ |
| test_insert_nops.cpp | 30 bld.mubuf(aco_opcode::buffer_load_dword, Definition(PhysReg(256), v1), Operand(PhysReg(0), s4),
31 Operand(PhysReg(256), v1), Operand::zero(), offset, true);
39 mimg->operands[0] = Operand(PhysReg(0), s8);
40 mimg->operands[1] = Operand(PhysReg(0), s4);
41 mimg->operands[2] = Operand(v1);
43 mimg->operands[3 + i] = Operand(PhysReg(256 + (nsa ? i * 2 : i)), v1);
60 bld.pseudo(aco_opcode::p_unit_test, Operand::zero());
69 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(1u));
77 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(2u))
[all...] |
| test_to_hw_instr.cpp | 54 bld.pseudo(aco_opcode::p_unit_test, Operand::zero());
57 Operand(v1_lo, v2b), Operand(v0_lo, v2b));
63 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(1u));
66 Operand(v1_lo, v2b), Operand(v0_lo, v2b));
73 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(2u));
75 Definition(v0_lo, v6b), Operand(v1_lo, v2b),
76 Operand(v0_lo, v2b), Operand(v2_lo, v2b))
[all...] |
| test_hard_clause.cpp | 31 Operand desc_op(desc);
34 Operand(PhysReg(256), v1), Operand::zero(), 0, false)
41 bld.mubuf(aco_opcode::buffer_store_dword, Operand(PhysReg(0), s4), Operand(PhysReg(256), v1),
42 Operand(PhysReg(256), v1), Operand::zero(), 0, false);
47 Operand desc_op(desc);
50 Operand(PhysReg(256), v1), Operand::zero(), V_008F0C_BUF_DATA_FORMAT_32
[all...] |
| test_optimizer_postRA.cpp | 51 auto vcmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), Operand::zero(),
52 Operand(v_in, reg_v0));
53 auto sand = bld.sop2(Builder::s_and, bld.def(bld.lm, reg_s0), bld.def(s1, scc), bld.vcc(vcmp), Operand(exec, bld.lm));
55 writeout(0, Operand(br, reg_s2));
68 auto vcmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), Operand::zero(),
69 Operand(v_in, reg_v0));
70 auto sand = bld.sop2(Builder::s_and, bld.def(bld.lm, reg_s0), bld.def(s1, scc), bld.vcc(vcmp), Operand(exec, bld.lm));
71 auto ovrwr = bld.sop1(Builder::s_mov, bld.def(bld.lm, vcc), Operand::zero());
73 writeout(1, Operand(br, reg_s2), Operand(ovrwr, vcc))
[all...] |
| test_sdwa.cpp | 80 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(4u), inputs[1]);
81 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(4u));
86 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x1234u), inputs[1]);
87 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(0x1234u));
139 //! 3rd operand must be fixed to vcc with SDWA: v1: %_ = v_cndmask_b32 %vgpr0, %vgpr1, %_ dst_sel:dword src0_sel:dword src1_sel:dword
171 Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u),
172 Operand::c32(is_signed));
176 Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u)
[all...] |
| test_optimizer.cpp | 44 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x123456u), neg_a));
100 writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x3f000000u), tmp));
105 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x40000000u), tmp));
110 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x40800000u), tmp));
115 writeout(3, bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), Operand::zero(),
116 Operand::c32(0x3f800000u), tmp));
121 tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x40000000u), tmp);
122 writeout(4, bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), Operand::zero(),
123 Operand::c32(0x3f800000u), tmp));
130 writeout(5, bld.vop2(aco_opcode::v_mul_f16, bld.def(v2b), Operand::c16(0x3800u), tmp))
[all...] |
| test_regalloc.cpp | 73 Temp lo = bld.vop1(aco_opcode::v_not_b32, bld.def(v2b), Operand::zero());
93 Operand op(inputs[0]);
107 Operand op(inputs[1]);
124 Operand op(inputs[0]);
141 Operand op(inputs[0]);
155 Temp tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), inputs[0], Operand::zero());
160 bld.pseudo(aco_opcode::p_create_vector, bld.def(v1), Operand(v3b), Operand(tmp));
173 Temp tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), inputs[0], Operand::c32(4u));
179 bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), inputs[1], Operand(v3b), Operand(tmp))
[all...] |
| test_assembler.cpp | 223 bld.sop1(aco_opcode::p_constaddr_getpc, Definition(PhysReg(0), s2), Operand::zero());
225 Operand(PhysReg(0), s1), Operand::zero());
241 add3->operands[0] = Operand::zero();
242 add3->operands[1] = Operand::zero();
243 add3->operands[2] = Operand::zero();
259 add3->operands[0] = Operand::zero();
260 add3->operands[1] = Operand::zero();
261 add3->operands[2] = Operand::zero();
|
| helpers.h | 91 void writeout(unsigned i, aco::Operand op);
92 void writeout(unsigned i, aco::Operand op0, aco::Operand op1);
|
| helpers.cpp | 245 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(i), tmp);
247 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(i));
252 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(i), res);
255 void writeout(unsigned i, Operand op)
257 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(i), op);
260 void writeout(unsigned i, Operand op0, Operand op1)
262 bld.pseudo(aco_opcode::p_unit_test, Operand::c32(i), op0, op1);
267 return bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0xbf800000u), src);
273 bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x3f800000u), src)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| aco_lower_to_hw_instr.cpp | 189 emit_vadd32(Builder& bld, Definition def, Operand src0, Operand src1)
191 Instruction* instr = bld.vadd32(def, src0, src1, false, Operand(s2), true);
201 unsigned bank_mask, bool bound_ctrl, Operand* identity = NULL)
206 Operand src0[] = {Operand(src0_reg, v1), Operand(PhysReg{src0_reg + 1}, v1)};
207 Operand src1[] = {Operand(src1_reg, v1), Operand(PhysReg{src1_reg + 1}, v1)}
[all...] |
| aco_instruction_selection.cpp | 136 emit_mbcnt(isel_context* ctx, Temp dst, Operand mask = Operand(), Operand base = Operand::zero())
143 Operand mask_lo = mask.isUndefined() ? Operand::c32(-1u) : mask;
147 Operand mask_lo = Operand::c32(-1u);
148 Operand mask_hi = Operand::c32(-1u)
[all...] |
| aco_lower_phis.cpp | 50 std::vector<Operand> outputs; /* the output per block */
53 Operand
61 Operand output = get_ssa(program, block_idx, state, true);
67 /* retrieve the Operand by checking the predecessors */
69 return Operand(program->lane_mask);
73 Operand op;
76 op = Operand::zero(program->lane_mask.bytes());
88 state->outputs[block_idx] = Operand(Temp(program->allocateTmp(program->lane_mask)));
92 std::vector<Operand> ops(pred);
97 if (std::all_of(ops.begin() + 1, ops.end(), [&](Operand same) { return same == ops[0]; })
[all...] |
| aco_insert_exec_mask.cpp | 82 std::vector<std::pair<Operand, uint8_t>>
178 for (const Operand& op : instr->operands) {
338 Operand
339 get_exec_op(Operand t)
342 return Operand(exec, t.regClass());
353 Operand exec_mask = ctx.info[idx].exec.back().first;
355 exec_mask = bld.pseudo(aco_opcode::p_parallelcopy, bld.def(bld.lm), Operand(exec, bld.lm));
392 Operand wqm = ctx.info[idx].exec.back().first;
395 Definition(exec, bld.lm), ctx.info[idx].exec[0].first, Operand(exec, bld.lm));
400 ctx.info[idx].exec.back().first = Operand(wqm)
[all...] |
| aco_reduce_assign.cpp | 75 end->operands[0] = Operand(reduceTmp);
77 end->operands[1] = Operand(vtmp);
161 instr->operands[1] = Operand(reduceTmp);
163 instr->operands[2] = Operand(vtmp);
|
| aco_optimizer.cpp | 194 Operand op16 = Operand::c16(constant);
195 Operand op32 = Operand::get_const(chip, constant, 4);
206 if (Operand::is_constant_representable(constant, 8))
210 val = Operand::c64(constant).constantValue();
602 is_operand_vgpr(Operand op)
623 alu_can_accept_constant(aco_opcode opcode, unsigned operand)
630 case aco_opcode::v_cndmask_b32: return operand != 2;
640 case aco_opcode::p_insert: return operand != 0
[all...] |
| aco_register_allocation.cpp | 199 DefInfo(ra_ctx& ctx, aco_ptr<Instruction>& instr, RegClass rc_, int operand) : rc(rc_)
206 if (rc.is_subdword() && operand >= 0) {
208 stride = get_subdword_operand_stride(ctx.program->chip_class, instr, operand, rc);
302 void fill(Operand op)
310 void clear(Operand op) { clear(op.physReg(), op.regClass()); }
721 std::vector<std::pair<Operand, Definition>>& parallelcopies,
725 for (std::pair<Operand, Definition>& copy : parallelcopies) {
757 for (std::pair<Operand, Definition>& other : parallelcopies) {
765 /* check if we moved an operand, again */
767 for (Operand& op : instr->operands)
2226 Operand& operand = instr->operands[0]; local
2250 Operand& operand = instr->operands[i]; local
2510 auto& operand = instr->operands[i]; local
[all...] |
| aco_lower_to_cssa.cpp | 51 Operand op;
55 Operand value = Operand(); /* original value: can be an SSA-def or constant value */
99 Operand op = phi->operands[i];
120 phi->operands[i] = Operand(tmp);
145 ctx.merge_node_table[def.tempId()] = {Operand(def.getTemp()), index, block.index};
232 for (const Operand& op : (*it)->operands) {
344 /* try emplace a merge_node for the copy operand */
347 /* find defining block of operand */
362 /* check if this operand has not yet been coalesced *
[all...] |
| aco_ir.h | 430 * Operand and Definition.
478 * Operand Class
479 * Initially, each Operand refers to either
485 class Operand final {
487 constexpr Operand()
493 explicit Operand(Temp r) noexcept
503 explicit Operand(Temp r, PhysReg reg) noexcept
512 static Operand c8(uint8_t v) noexcept
517 Operand op;
527 static Operand c16(uint16_t v) noexcep
[all...] |
| aco_spill.cpp | 196 for (const Operand& op : instr->operands) {
296 for (const Operand& op : instr->operands) {
350 reload->operands[0] = Operand::c32(spill_id);
407 for (const Operand& op : instr->operands) {
511 /* variable is not live at loop entry: probably a phi operand */
875 Operand spill_op = phi->operands[i];
911 spill->operands[1] = Operand::c32(spill_id);
966 spill->operands[0] = Operand(var);
967 spill->operands[1] = Operand::c32(pair.second);
994 /* if the operand was reloaded, rename *
[all...] |
| aco_assembler.cpp | 88 instr->operands[1] = Operand::zero();
247 const Operand& op_off1 = instr->operands[1];
251 /* GFX10 only supports constants in OFFSET, so put the operand in SOFFSET if it's an
262 const Operand& op_off2 = instr->operands.back();
673 /* first emit the instruction without the DPP operand */
674 Operand dpp_op = instr->operands[0];
675 instr->operands[0] = Operand(PhysReg{250}, v1);
694 /* first emit the instruction without the SDWA operand */
695 Operand sdwa_op = instr->operands[0];
696 instr->operands[0] = Operand(PhysReg{249}, v1)
[all...] |
| aco_dead_code_analysis.cpp | 64 for (const Operand& op : instr->operands) {
|
| aco_reindex_ssa.cpp | 54 for (Operand& op : instr->operands) {
|
| aco_validate.cpp | 185 const Operand& op = instr->operands[i];
188 "SDWA operand selection size must be at most operand size", instr.get());
190 "SDWA operand selection size must be 1, 2 or 4 bytes", instr.get());
196 "3rd operand must be fixed to vcc with SDWA", instr.get());
233 check((vop3.opsel & (1 << i)) == 0, "Unexpected opsel for operand", instr.get());
244 "Unexpected opsel for subdword operand", instr.get());
262 "Uninitialized Operand", instr.get());
276 Operand literal(s1);
278 Operand op = instr->operands[i]
[all...] |
| aco_insert_NOPs.cpp | 145 * operand/definition of another instruction in the clause */
271 handle_raw_hazard(State& state, int* NOPs, int min_states, Operand op)
335 for (Operand op : instr->operands) {
365 Operand op = instr->operands[i];
399 for (Operand op : instr->operands) {
442 for (Operand op : instr->operands) {
491 for (Operand op : instr->operands) {
576 for (const Operand& op : instr->operands) {
688 /* v_nop would be discarded by SQ, so use v_mov with the first operand of the permlane */
692 v_mov->operands[0] = Operand(instr->operands[0].physReg(), v1)
[all...] |
