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      1 /* $NetBSD: octeon_intc.c,v 1.7 2021/05/05 06:47:29 simonb Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2020 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: octeon_intc.c,v 1.7 2021/05/05 06:47:29 simonb Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/bus.h>
     34 #include <sys/device.h>
     35 #include <sys/intr.h>
     36 #include <sys/systm.h>
     37 #include <sys/kernel.h>
     38 #include <sys/kmem.h>
     39 
     40 #include <dev/fdt/fdtvar.h>
     41 
     42 #include <arch/mips/cavium/octeonvar.h>
     43 
     44 static int	octeon_intc_match(device_t, cfdata_t, void *);
     45 static void	octeon_intc_attach(device_t, device_t, void *);
     46 
     47 static void *	octeon_intc_establish(device_t, u_int *, int, int,
     48 		    int (*)(void *), void *, const char *);
     49 static void	octeon_intc_disestablish(device_t, void *);
     50 static bool	octeon_intc_intrstr(device_t, u_int *, char *, size_t);
     51 
     52 static struct fdtbus_interrupt_controller_func octeon_intc_funcs = {
     53 	.establish = octeon_intc_establish,
     54 	.disestablish = octeon_intc_disestablish,
     55 	.intrstr = octeon_intc_intrstr
     56 };
     57 
     58 enum octeon_intc_type {
     59 	OCTEON_INTC_CIU,
     60 };
     61 
     62 struct octeon_intc_softc {
     63 	device_t		sc_dev;
     64 	int			sc_phandle;
     65 	enum octeon_intc_type	sc_type;
     66 	const char		*sc_descr;
     67 };
     68 
     69 CFATTACH_DECL_NEW(octintc, sizeof(struct octeon_intc_softc),
     70 	octeon_intc_match, octeon_intc_attach, NULL, NULL);
     71 
     72 static const struct device_compatible_entry compat_data[] = {
     73 	{ .compat = "cavium,octeon-3860-ciu",	.value = OCTEON_INTC_CIU },
     74 	DEVICE_COMPAT_EOL
     75 };
     76 
     77 static int
     78 octeon_intc_match(device_t parent, cfdata_t cf, void *aux)
     79 {
     80 	struct fdt_attach_args * const faa = aux;
     81 
     82 	return of_compatible_match(faa->faa_phandle, compat_data);
     83 }
     84 
     85 static void
     86 octeon_intc_attach(device_t parent, device_t self, void *aux)
     87 {
     88 	struct octeon_intc_softc * const sc = device_private(self);
     89 	struct fdt_attach_args * const faa = aux;
     90 	const int phandle = faa->faa_phandle;
     91 	int error;
     92 
     93 	sc->sc_dev = self;
     94 	sc->sc_phandle = phandle;
     95 	sc->sc_type = of_compatible_lookup(phandle, compat_data)->value;
     96 
     97 	switch (sc->sc_type) {
     98 	case OCTEON_INTC_CIU:
     99 		sc->sc_descr = "CIU";
    100 		break;
    101 	}
    102 
    103 	error = fdtbus_register_interrupt_controller(self, phandle,
    104 	    &octeon_intc_funcs);
    105 	if (error != 0) {
    106 		aprint_error(": couldn't register with fdtbus: %d\n", error);
    107 		return;
    108 	}
    109 
    110 	aprint_naive("\n");
    111 	aprint_normal(": %s\n", sc->sc_descr);
    112 }
    113 
    114 static void *
    115 octeon_intc_establish(device_t dev, u_int *specifier, int ipl, int flags,
    116     int (*func)(void *), void *arg, const char *xname)
    117 {
    118 	struct octeon_intc_softc * const sc = device_private(dev);
    119 
    120 	/* 1st cell is the controller register (0 or 1) */
    121 	/* 2nd cell is the bit within the register (0..63) */
    122 
    123 	const u_int reg = be32toh(specifier[0]);
    124 	const u_int bit = be32toh(specifier[1]);
    125 	const u_int irq = (reg * 64) + bit;
    126 
    127 	if (irq >= NIRQS) {
    128 		aprint_error_dev(dev, "%s irq %d (%d, %d) out of range\n",
    129 		    sc->sc_descr, irq, reg, bit);
    130 		return NULL;
    131 	}
    132 
    133 	return octeon_intr_establish(irq, ipl, func, arg);
    134 }
    135 
    136 static void
    137 octeon_intc_disestablish(device_t dev, void *ih)
    138 {
    139 	octeon_intr_disestablish(ih);
    140 }
    141 
    142 static bool
    143 octeon_intc_intrstr(device_t dev, u_int *specifier, char *buf,
    144     size_t buflen)
    145 {
    146 	struct octeon_intc_softc * const sc = device_private(dev);
    147 
    148 	/* 1st cell is the controller register (0 or 1) */
    149 	/* 2nd cell is the bit within the register (0..63) */
    150 
    151 	const u_int reg = be32toh(specifier[0]);
    152 	const u_int bit = be32toh(specifier[1]);
    153 	const u_int irq = (reg * 64) + bit;
    154 
    155 	snprintf(buf, buflen, "%s irq %d", sc->sc_descr, irq);
    156 
    157 	return true;
    158 }
    159