1 /* $NetBSD: if_rge.c,v 1.54 2026/08/02 15:52:54 pgoyette Exp $ */ 2 /* $OpenBSD: if_rge.c,v 1.42 2026/01/26 01:45:18 kevlo Exp $ */ 3 4 /* 5 * Copyright (c) 2019, 2020, 2023-2025 6 * Kevin Lo <kevlo (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/cdefs.h> 22 __KERNEL_RCSID(0, "$NetBSD: if_rge.c,v 1.54 2026/08/02 15:52:54 pgoyette Exp $"); 23 24 #if defined(_KERNEL_OPT) 25 #include "opt_net_mpsafe.h" 26 #endif 27 28 #include <sys/types.h> 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/sockio.h> 33 #include <sys/mbuf.h> 34 #include <sys/kernel.h> 35 #include <sys/socket.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 #include <sys/callout.h> 39 #include <sys/workqueue.h> 40 #include <sys/module.h> 41 42 #include <net/if.h> 43 44 #include <net/if_dl.h> 45 #include <net/if_ether.h> 46 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <net/if_ether.h> 51 52 #include <net/bpf.h> 53 54 #include <sys/bus.h> 55 #include <machine/intr.h> 56 57 #include <dev/mii/mii.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #ifdef __NetBSD__ 64 #define letoh32 htole32 65 #define nitems(x) __arraycount(x) 66 #endif 67 68 #include <dev/pci/if_rgereg.h> 69 70 #define RGE_LOCK(sc) mutex_enter(&(sc)->sc_lock) 71 #define RGE_UNLOCK(sc) mutex_exit(&(sc)->sc_lock) 72 #define RGE_ASSERT_LOCKED(sc) KASSERT(mutex_owned(&(sc)->sc_lock)) 73 74 #ifdef RGE_DEBUG 75 #define DPRINTF(x) do { if (rge_debug > 0) printf x; } while (0) 76 int rge_debug = 0; 77 #else 78 #define DPRINTF(x) 79 #endif 80 81 static int rge_match(device_t, cfdata_t, void *); 82 static void rge_attach(device_t, device_t, void *); 83 static int rge_detach(device_t, int); 84 static int rge_intr(void *); 85 static int rge_encap(struct rge_softc *, struct rge_queues *, 86 struct mbuf *, int); 87 static int rge_ioctl(struct ifnet *, u_long, void *); 88 static void rge_start(struct ifnet *); 89 static void rge_watchdog(struct ifnet *); 90 static int rge_init(struct ifnet *); 91 static int rge_init_locked(struct rge_softc *); 92 static void rge_stop(struct ifnet *, int); 93 static void rge_stop_locked(struct rge_softc *, int); 94 static int rge_ifmedia_upd(struct ifnet *); 95 static void rge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 96 static int rge_allocmem(struct rge_softc *); 97 static int rge_deallocmem(struct rge_softc *); 98 static int rge_newbuf(struct rge_queues *, int); 99 static int rge_rx_list_init(struct rge_queues *); 100 static void rge_rx_list_fini(struct rge_queues *); 101 static void rge_tx_list_init(struct rge_queues *); 102 static int rge_rxeof(struct rge_softc *); 103 static int rge_txeof(struct rge_softc *); 104 static int rge_reset(struct rge_softc *); 105 static void rge_iff(struct rge_softc *); 106 static int rge_ifflags_cb(struct ethercom *); 107 static void rge_mac_config_mcu(struct rge_softc *, enum rge_mac_type); 108 static void rge_mac_config_ext_mcu(struct rge_softc *, enum rge_mac_type); 109 static uint64_t rge_mcu_get_bin_version(const uint16_t *, uint16_t); 110 static void rge_mcu_set_version(struct rge_softc *, uint64_t); 111 static int rge_chipinit(struct rge_softc *); 112 static void rge_set_phy_power(struct rge_softc *, int); 113 static void rge_ephy_config(struct rge_softc *); 114 static void rge_ephy_config_mac_r25(struct rge_softc *); 115 static void rge_ephy_config_mac_r25b(struct rge_softc *); 116 static void rge_ephy_config_mac_r27(struct rge_softc *); 117 static int rge_phy_config(struct rge_softc *); 118 static void rge_phy_config_mac_r27(struct rge_softc *); 119 static void rge_phy_config_mac_r26_1(struct rge_softc *); 120 static void rge_phy_config_mac_r26_2(struct rge_softc *); 121 static void rge_phy_config_mac_r25(struct rge_softc *); 122 static void rge_phy_config_mac_r25b(struct rge_softc *); 123 static void rge_phy_config_mac_r25d_1(struct rge_softc *); 124 static void rge_phy_config_mac_r25d_2(struct rge_softc *); 125 static void rge_phy_config_mcu(struct rge_softc *, uint16_t); 126 static void rge_set_macaddr(struct rge_softc *, const uint8_t *); 127 static void rge_get_macaddr(struct rge_softc *, uint8_t *); 128 static void rge_hw_init(struct rge_softc *); 129 static void rge_hw_reset(struct rge_softc *); 130 static void rge_disable_phy_ocp_pwrsave(struct rge_softc *); 131 static void rge_patch_phy_mcu(struct rge_softc *, int); 132 static void rge_add_media_types(struct rge_softc *); 133 static void rge_config_imtype(struct rge_softc *, int); 134 static void rge_disable_aspm_clkreq(struct rge_softc *); 135 static void rge_disable_hw_im(struct rge_softc *); 136 static void rge_disable_sim_im(struct rge_softc *); 137 static void rge_setup_sim_im(struct rge_softc *); 138 static void rge_setup_intr(struct rge_softc *, int); 139 static void rge_switch_mcu_ram_page(struct rge_softc *, int); 140 static int rge_exit_oob(struct rge_softc *); 141 static void rge_write_csi(struct rge_softc *, uint32_t, uint32_t); 142 static uint32_t rge_read_csi(struct rge_softc *, uint32_t); 143 static void rge_write_mac_ocp(struct rge_softc *, uint16_t, uint16_t); 144 static uint16_t rge_read_mac_ocp(struct rge_softc *, uint16_t); 145 static void rge_write_ephy(struct rge_softc *, uint16_t, uint16_t); 146 static uint16_t rge_read_ephy(struct rge_softc *, uint16_t); 147 static uint16_t rge_check_ephy_ext_add(struct rge_softc *, uint16_t); 148 static void rge_r27_write_ephy(struct rge_softc *, uint16_t, uint16_t); 149 static int rge_wait_sds(struct rge_softc *); 150 static uint16_t rge_read_sds(struct rge_softc *, uint16_t); 151 static void rge_write_sds(struct rge_softc *, uint16_t, uint16_t); 152 static void rge_reset_sds(struct rge_softc *); 153 static void rge_write_phy(struct rge_softc *, uint16_t, uint16_t, uint16_t); 154 static uint16_t rge_read_phy(struct rge_softc *, uint16_t, uint16_t); 155 static void rge_write_phy_ocp(struct rge_softc *, uint16_t, uint16_t); 156 static uint16_t rge_read_phy_ocp(struct rge_softc *, uint16_t); 157 static int rge_get_link_status(struct rge_softc *); 158 static void rge_txstart(void *); 159 static void rge_tick(void *); 160 static void rge_link_state(struct rge_softc *); 161 162 static const struct { 163 uint16_t reg; 164 uint16_t val; 165 } mac_r25_mcu[] = { 166 MAC_R25_MCU 167 }, mac_r25b_mcu[] = { 168 MAC_R25B_MCU 169 }, mac_r25d_1_mcu[] = { 170 MAC_R25D_MCU}; 171 172 CFATTACH_DECL_NEW(rge, sizeof(struct rge_softc), rge_match, rge_attach, 173 rge_detach, NULL); 174 175 static const struct device_compatible_entry compat_data[] = { 176 { .id = PCI_ID_CODE(PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_E3000) }, 177 { .id = PCI_ID_CODE(PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_E5000) }, 178 { .id = PCI_ID_CODE(PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8125) }, 179 { .id = PCI_ID_CODE(PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8126) }, 180 { .id = PCI_ID_CODE(PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8127) }, 181 182 PCI_COMPAT_EOL 183 }; 184 185 static int 186 rge_match(device_t parent, cfdata_t match, void *aux) 187 { 188 struct pci_attach_args *pa =aux; 189 190 return pci_compatible_match(pa, compat_data); 191 } 192 193 static void 194 rge_attach(device_t parent, device_t self, void *aux) 195 { 196 struct rge_softc *sc = device_private(self); 197 struct pci_attach_args *pa = aux; 198 pci_chipset_tag_t pc = pa->pa_pc; 199 char intrbuf[PCI_INTRSTR_LEN]; 200 const char *intrstr = NULL; 201 struct ifnet *ifp; 202 struct rge_queues *q; 203 pcireg_t reg; 204 uint32_t hwrev; 205 uint8_t eaddr[ETHER_ADDR_LEN]; 206 int offset; 207 pcireg_t command; 208 const char *revstr; 209 210 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NET); 211 212 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 213 214 sc->sc_dev = self; 215 216 pci_aprint_devinfo(pa, "Ethernet controller"); 217 218 /* 219 * Map control/status registers. 220 */ 221 if (pci_mapreg_map(pa, RGE_PCI_BAR2, PCI_MAPREG_TYPE_MEM | 222 PCI_MAPREG_MEM_TYPE_64BIT, 0, &sc->rge_btag, &sc->rge_bhandle, 223 NULL, &sc->rge_bsize)) { 224 if (pci_mapreg_map(pa, RGE_PCI_BAR1, PCI_MAPREG_TYPE_MEM | 225 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->rge_btag, 226 &sc->rge_bhandle, NULL, &sc->rge_bsize)) { 227 if (pci_mapreg_map(pa, RGE_PCI_BAR0, PCI_MAPREG_TYPE_IO, 228 0, &sc->rge_btag, &sc->rge_bhandle, NULL, 229 &sc->rge_bsize)) { 230 aprint_error(": can't map mem or i/o space\n"); 231 return; 232 } 233 } 234 } 235 236 q = malloc(sizeof(struct rge_queues), M_DEVBUF, M_NOWAIT | M_ZERO); 237 if (q == NULL) { 238 aprint_error(": unable to allocate queue memory\n"); 239 return; 240 } 241 q->q_sc = sc; 242 q->q_index = 0; 243 244 sc->sc_queues = q; 245 sc->sc_nqueues = 1; 246 247 /* 248 * Allocate interrupt. 249 */ 250 int counts[PCI_INTR_TYPE_SIZE] = { 251 [PCI_INTR_TYPE_INTX] = 1, 252 [PCI_INTR_TYPE_MSI] = 1, 253 [PCI_INTR_TYPE_MSIX] = 1, 254 }; 255 int max_type = PCI_INTR_TYPE_MSIX; 256 257 if (pci_intr_alloc(pa, &sc->sc_intrs, counts, max_type) != 0) { 258 aprint_error(": couldn't map interrupt\n"); 259 return; 260 } 261 switch (pci_intr_type(pc, sc->sc_intrs[0])) { 262 case PCI_INTR_TYPE_MSIX: 263 case PCI_INTR_TYPE_MSI: 264 sc->rge_flags |= RGE_FLAG_MSI; 265 break; 266 default: 267 break; 268 } 269 intrstr = pci_intr_string(pc, sc->sc_intrs[0], 270 intrbuf, sizeof(intrbuf)); 271 sc->sc_ihs[0] = pci_intr_establish_xname(pc, sc->sc_intrs[0], 272 IPL_NET, rge_intr, sc, device_xname(sc->sc_dev)); 273 274 if (sc->sc_ihs[0] == NULL) { 275 aprint_error_dev(sc->sc_dev, ": couldn't establish interrupt"); 276 if (intrstr != NULL) 277 aprint_error(" at %s\n", intrstr); 278 aprint_error("\n"); 279 return; 280 } 281 pci_intr_setattr(pc, &sc->sc_intrs[0], PCI_INTR_MPSAFE, true); 282 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 283 284 if (pci_dma64_available(pa)) 285 sc->sc_dmat = pa->pa_dmat64; 286 else 287 sc->sc_dmat = pa->pa_dmat; 288 289 sc->sc_pc = pa->pa_pc; 290 sc->sc_tag = pa->pa_tag; 291 292 /* Determine hardware revision */ 293 hwrev = RGE_READ_4(sc, RGE_TXCFG) & RGE_TXCFG_HWREV; 294 revstr = NULL; 295 switch (hwrev) { 296 case 0x60900000: 297 sc->rge_type = MAC_R25; 298 break; 299 case 0x64100000: 300 sc->rge_type = MAC_R25B; 301 revstr = "B"; 302 break; 303 case 0x64900000: 304 sc->rge_type = MAC_R26_1; 305 break; 306 case 0x64a00000: 307 sc->rge_type = MAC_R26_2; 308 break; 309 case 0x68800000: 310 sc->rge_type = MAC_R25D_1; 311 revstr = "D"; 312 break; 313 case 0x68900000: 314 sc->rge_type = MAC_R25D_2; 315 revstr = "D"; 316 break; 317 case 0x6c900000: 318 sc->rge_type = MAC_R27; 319 break; 320 default: 321 aprint_error(": unknown version 0x%08x\n", hwrev); 322 return; 323 } 324 325 if (revstr != NULL) 326 aprint_normal_dev(sc->sc_dev, "HW rev. %s\n", revstr); 327 rge_config_imtype(sc, RGE_IMTYPE_SIM); 328 329 /* 330 * PCI Express check. 331 */ 332 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 333 &offset, NULL)) { 334 /* Disable PCIe ASPM and ECPM. */ 335 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 336 offset + PCIE_LCSR); 337 reg &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1 | 338 PCIE_LCSR_ENCLKPM); 339 pci_conf_write(pa->pa_pc, pa->pa_tag, offset + PCIE_LCSR, 340 reg); 341 } 342 343 rge_exit_oob(sc); 344 rge_hw_init(sc); 345 346 rge_get_macaddr(sc, eaddr); 347 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 348 ether_sprintf(eaddr)); 349 350 memcpy(sc->sc_enaddr, eaddr, ETHER_ADDR_LEN); 351 352 rge_set_phy_power(sc, 1); 353 rge_phy_config(sc); 354 355 if (rge_allocmem(sc)) 356 return; 357 358 ifp = &sc->sc_ec.ec_if; 359 ifp->if_softc = sc; 360 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 361 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 362 ifp->if_extflags = IFEF_MPSAFE; 363 ifp->if_ioctl = rge_ioctl; 364 ifp->if_stop = rge_stop; 365 ifp->if_start = rge_start; 366 ifp->if_init = rge_init; 367 ifp->if_watchdog = rge_watchdog; 368 IFQ_SET_MAXLEN(&ifp->if_snd, RGE_TX_LIST_CNT - 1); 369 370 ifp->if_capabilities = IFCAP_CSUM_IPv4_Rx | 371 IFCAP_CSUM_IPv4_Tx |IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_TCPv4_Tx| 372 IFCAP_CSUM_UDPv4_Rx | IFCAP_CSUM_UDPv4_Tx; 373 374 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 375 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 376 377 callout_init(&sc->sc_timeout, CALLOUT_MPSAFE); 378 callout_setfunc(&sc->sc_timeout, rge_tick, sc); 379 380 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 381 command |= PCI_COMMAND_MASTER_ENABLE; 382 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 383 384 /* Initialize ifmedia structures. */ 385 sc->sc_ec.ec_ifmedia = &sc->sc_media; 386 ifmedia_init(&sc->sc_media, IFM_IMASK, rge_ifmedia_upd, 387 rge_ifmedia_sts); 388 rge_add_media_types(sc); 389 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 390 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 391 sc->sc_media.ifm_media = sc->sc_media.ifm_cur->ifm_media; 392 393 if_attach(ifp); 394 if_deferred_start_init(ifp, NULL); 395 ether_ifattach(ifp, eaddr); 396 ether_set_ifflags_cb(&sc->sc_ec, rge_ifflags_cb); 397 398 if (pmf_device_register(self, NULL, NULL)) 399 pmf_class_network_register(self, ifp); 400 else 401 aprint_error_dev(self, "couldn't establish power handler\n"); 402 } 403 404 static int 405 rge_detach(device_t self, int flags) 406 { 407 struct rge_softc *sc = device_private(self); 408 struct ifnet *ifp = &sc->sc_ec.ec_if; 409 pci_chipset_tag_t pc = sc->sc_pc; 410 411 rge_stop(ifp, 1); 412 413 pmf_device_deregister(self); 414 415 ether_ifdetach(ifp); 416 417 if_detach(ifp); 418 419 ifmedia_fini(&sc->sc_media); 420 421 if (sc->sc_ihs[0] != NULL) { 422 pci_intr_disestablish(sc->sc_pc, sc->sc_ihs[0]); 423 sc->sc_ihs[0] = NULL; 424 } 425 426 pci_intr_release(pc, sc->sc_intrs, 1); 427 428 rge_deallocmem(sc); 429 430 free(sc->sc_queues, M_DEVBUF); 431 432 mutex_destroy(&sc->sc_lock); 433 434 return 0; 435 } 436 static int 437 rge_intr(void *arg) 438 { 439 struct rge_softc *sc = arg; 440 struct ifnet *ifp = &sc->sc_ec.ec_if; 441 uint32_t status; 442 int claimed = 0, rx, tx; 443 444 RGE_LOCK(sc); 445 446 if (!(ifp->if_flags & IFF_RUNNING)) 447 goto done; 448 449 /* Disable interrupts. */ 450 RGE_WRITE_4(sc, RGE_IMR, 0); 451 452 if (!(sc->rge_flags & RGE_FLAG_MSI)) { 453 if ((RGE_READ_4(sc, RGE_ISR) & sc->rge_intrs) == 0) 454 goto done; 455 } 456 457 status = RGE_READ_4(sc, RGE_ISR); 458 if (status) 459 RGE_WRITE_4(sc, RGE_ISR, status); 460 461 if (status & RGE_ISR_PCS_TIMEOUT) 462 claimed = 1; 463 464 rx = tx = 0; 465 if (status & sc->rge_intrs) { 466 if (status & 467 (sc->rge_rx_ack | RGE_ISR_RX_ERR | RGE_ISR_RX_FIFO_OFLOW)) { 468 rx |= rge_rxeof(sc); 469 claimed = 1; 470 } 471 472 if (status & (sc->rge_tx_ack | RGE_ISR_TX_ERR)) { 473 tx |= rge_txeof(sc); 474 claimed = 1; 475 } 476 477 if (status & RGE_ISR_SYSTEM_ERR) { 478 rge_init_locked(sc); 479 claimed = 1; 480 } 481 } 482 483 if (sc->rge_timerintr) { 484 if ((tx | rx) == 0) { 485 /* 486 * Nothing needs to be processed, fallback 487 * to use TX/RX interrupts. 488 */ 489 rge_setup_intr(sc, RGE_IMTYPE_NONE); 490 491 /* 492 * Recollect, mainly to avoid the possible 493 * race introduced by changing interrupt 494 * masks. 495 */ 496 rge_rxeof(sc); 497 rge_txeof(sc); 498 } else 499 RGE_WRITE_4(sc, RGE_TIMERCNT, 1); 500 } else if (tx | rx) { 501 /* 502 * Assume that using simulated interrupt moderation 503 * (hardware timer based) could reduce the interrupt 504 * rate. 505 */ 506 rge_setup_intr(sc, RGE_IMTYPE_SIM); 507 } 508 509 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs); 510 511 done: 512 RGE_UNLOCK(sc); 513 return (claimed); 514 } 515 516 static inline void 517 rge_tx_list_sync(struct rge_softc *sc, struct rge_queues *q, 518 unsigned int idx, unsigned int len, int ops) 519 { 520 bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, 521 idx * sizeof(struct rge_tx_desc), len * sizeof(struct rge_tx_desc), 522 ops); 523 } 524 525 static int 526 rge_encap(struct rge_softc *sc, struct rge_queues *q,struct mbuf *m, int idx) 527 { 528 struct rge_tx_desc *d = NULL; 529 struct rge_txq *txq; 530 bus_dmamap_t txmap; 531 uint32_t cmdsts, cflags = 0; 532 int cur, error, i; 533 534 txq = &q->q_tx.rge_txq[idx]; 535 txmap = txq->txq_dmamap; 536 537 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m, BUS_DMA_NOWAIT); 538 switch (error) { 539 case 0: 540 break; 541 case EFBIG: /* mbuf chain is too fragmented */ 542 if (m_defrag(m, M_DONTWAIT) == 0 && 543 bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m, 544 BUS_DMA_NOWAIT) == 0) 545 break; 546 547 /* FALLTHROUGH */ 548 default: 549 return (0); 550 } 551 552 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 553 BUS_DMASYNC_PREWRITE); 554 555 /* 556 * Set RGE_TDEXTSTS_IPCSUM if any checksum offloading is requested. 557 * Otherwise, RGE_TDEXTSTS_TCPCSUM / RGE_TDEXTSTS_UDPCSUM does not 558 * take affect. 559 */ 560 if ((m->m_pkthdr.csum_flags & 561 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) != 0) { 562 cflags |= RGE_TDEXTSTS_IPCSUM; 563 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 564 cflags |= RGE_TDEXTSTS_TCPCSUM; 565 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 566 cflags |= RGE_TDEXTSTS_UDPCSUM; 567 } 568 569 /* Set up hardware VLAN tagging. */ 570 if (vlan_has_tag(m)) 571 cflags |= bswap16(vlan_get_tag(m)) | RGE_TDEXTSTS_VTAG; 572 573 cur = idx; 574 for (i = 1; i < txmap->dm_nsegs; i++) { 575 cur = RGE_NEXT_TX_DESC(cur); 576 577 cmdsts = RGE_TDCMDSTS_OWN; 578 cmdsts |= txmap->dm_segs[i].ds_len; 579 580 if (cur == RGE_TX_LIST_CNT - 1) 581 cmdsts |= RGE_TDCMDSTS_EOR; 582 if (i == txmap->dm_nsegs - 1) 583 cmdsts |= RGE_TDCMDSTS_EOF; 584 585 d = &q->q_tx.rge_tx_list[cur]; 586 d->rge_cmdsts = htole32(cmdsts); 587 d->rge_extsts = htole32(cflags); 588 d->rge_addr = htole64(txmap->dm_segs[i].ds_addr); 589 } 590 591 /* Update info of TX queue and descriptors. */ 592 txq->txq_mbuf = m; 593 txq->txq_descidx = cur; 594 595 cmdsts = RGE_TDCMDSTS_SOF; 596 cmdsts |= txmap->dm_segs[0].ds_len; 597 598 if (idx == RGE_TX_LIST_CNT - 1) 599 cmdsts |= RGE_TDCMDSTS_EOR; 600 if (txmap->dm_nsegs == 1) 601 cmdsts |= RGE_TDCMDSTS_EOF; 602 603 d = &q->q_tx.rge_tx_list[idx]; 604 d->rge_cmdsts = htole32(cmdsts); 605 d->rge_extsts = htole32(cflags); 606 d->rge_addr = htole64(txmap->dm_segs[0].ds_addr); 607 608 if (cur >= idx) { 609 rge_tx_list_sync(sc, q, idx, txmap->dm_nsegs, 610 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 611 } else { 612 rge_tx_list_sync(sc, q, idx, RGE_TX_LIST_CNT - idx, 613 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 614 rge_tx_list_sync(sc, q, 0, cur + 1, 615 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 616 } 617 618 /* Transfer ownership of packet to the chip. */ 619 cmdsts |= RGE_TDCMDSTS_OWN; 620 rge_tx_list_sync(sc, q, idx, 1, BUS_DMASYNC_POSTWRITE); 621 d->rge_cmdsts = htole32(cmdsts); 622 rge_tx_list_sync(sc, q, idx, 1, BUS_DMASYNC_PREWRITE); 623 624 return (txmap->dm_nsegs); 625 } 626 627 static int 628 rge_ioctl(struct ifnet *ifp, u_long cmd, void *data) 629 { 630 struct rge_softc *sc = ifp->if_softc; 631 struct ifreq *ifr = (struct ifreq *)data; 632 int s, error = 0; 633 634 s = splnet(); 635 636 switch (cmd) { 637 case SIOCSIFMTU: 638 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RGE_JUMBO_MTU) { 639 error = EINVAL; 640 } else { 641 ifp->if_mtu = ifr->ifr_mtu; 642 error = 0; /* no need to reset (no ENETRESET) */ 643 } 644 break; 645 default: 646 error = ether_ioctl(ifp, cmd, data); 647 break; 648 } 649 650 if (error == ENETRESET) { 651 RGE_LOCK(sc); 652 if (sc->sc_if_flags & IFF_RUNNING) 653 rge_iff(sc); 654 RGE_UNLOCK(sc); 655 error = 0; 656 } 657 658 splx(s); 659 return (error); 660 } 661 662 static int 663 rge_ifflags_cb(struct ethercom *ec) 664 { 665 struct ifnet * const ifp = &ec->ec_if; 666 struct rge_softc * const sc = ifp->if_softc; 667 int ret = 0; 668 u_short change; 669 670 KASSERT(IFNET_LOCKED(ifp)); 671 RGE_LOCK(sc); 672 673 change = ifp->if_flags ^ sc->sc_if_flags; 674 sc->sc_if_flags = ifp->if_flags; 675 676 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 677 ret = ENETRESET; 678 } else if ((change & IFF_PROMISC) != 0) { 679 if ((sc->sc_if_flags & IFF_RUNNING) != 0) 680 rge_iff(sc); 681 } 682 683 RGE_UNLOCK(sc); 684 return ret; 685 } 686 687 static void 688 rge_start(struct ifnet *ifp) 689 { 690 struct rge_softc *sc = ifp->if_softc; 691 struct rge_queues *q = sc->sc_queues; 692 struct mbuf *m; 693 int free, idx, used; 694 int queued = 0; 695 696 #define LINK_STATE_IS_UP(_s) \ 697 ((_s) >= LINK_STATE_UP || (_s) == LINK_STATE_UNKNOWN) 698 699 if (!LINK_STATE_IS_UP(ifp->if_link_state)) { 700 IFQ_PURGE(&ifp->if_snd); 701 return; 702 } 703 704 /* Calculate free space. */ 705 idx = q->q_tx.rge_txq_prodidx; 706 free = q->q_tx.rge_txq_considx; 707 if (free <= idx) 708 free += RGE_TX_LIST_CNT; 709 free -= idx; 710 711 for (;;) { 712 if (free < RGE_TX_NSEGS + 2) { 713 SET(ifp->if_flags, IFF_OACTIVE); 714 break; 715 } 716 717 IFQ_DEQUEUE(&ifp->if_snd, m); 718 if (m == NULL) 719 break; 720 721 used = rge_encap(sc, q, m, idx); 722 if (used == 0) { 723 m_freem(m); 724 continue; 725 } 726 727 KASSERT(used <= free); 728 free -= used; 729 730 bpf_mtap(ifp, m, BPF_D_OUT); 731 732 idx += used; 733 if (idx >= RGE_TX_LIST_CNT) 734 idx -= RGE_TX_LIST_CNT; 735 736 queued++; 737 } 738 739 if (queued == 0) 740 return; 741 742 /* Set a timeout in case the chip goes out to lunch. */ 743 ifp->if_timer = 5; 744 745 q->q_tx.rge_txq_prodidx = idx; 746 rge_txstart(sc); 747 } 748 749 static void 750 rge_watchdog(struct ifnet *ifp) 751 { 752 struct rge_softc *sc = ifp->if_softc; 753 754 RGE_LOCK(sc); 755 756 device_printf(sc->sc_dev, "watchdog timeout\n"); 757 if_statinc(ifp, if_oerrors); 758 759 rge_init_locked(sc); 760 RGE_UNLOCK(sc); 761 } 762 763 static int 764 rge_init_locked(struct rge_softc *sc) 765 { 766 struct ifnet *ifp = &sc->sc_ec.ec_if; 767 struct rge_queues *q = sc->sc_queues; 768 uint32_t rxconf, val; 769 unsigned i, num_miti; 770 int error; 771 772 rge_stop_locked(sc, 0); 773 774 /* Set MAC address. */ 775 rge_set_macaddr(sc, CLLADDR(ifp->if_sadl)); 776 777 /* Initialize RX and TX descriptors lists. */ 778 rge_rx_list_init(q); 779 rge_tx_list_init(q); 780 781 if ((error = rge_chipinit(sc))) 782 return (error); 783 784 if ((error = rge_phy_config(sc))) 785 return (error); 786 787 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); 788 789 RGE_CLRBIT_1(sc, 0xf1, 0x80); 790 rge_disable_aspm_clkreq(sc); 791 RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, 792 RGE_JUMBO_MTU + ETHER_HDR_LEN + 32); 793 794 /* Load the addresses of the RX and TX lists into the chip. */ 795 RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO, 796 RGE_ADDR_LO(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr)); 797 RGE_WRITE_4(sc, RGE_RXDESC_ADDR_HI, 798 RGE_ADDR_HI(q->q_rx.rge_rx_list_map->dm_segs[0].ds_addr)); 799 RGE_WRITE_4(sc, RGE_TXDESC_ADDR_LO, 800 RGE_ADDR_LO(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr)); 801 RGE_WRITE_4(sc, RGE_TXDESC_ADDR_HI, 802 RGE_ADDR_HI(q->q_tx.rge_tx_list_map->dm_segs[0].ds_addr)); 803 804 /* Set the initial RX and TX configurations. */ 805 if (sc->rge_type == MAC_R25) 806 rxconf = RGE_RXCFG_CONFIG; 807 else if (sc->rge_type == MAC_R25B) 808 rxconf = RGE_RXCFG_CONFIG_8125B; 809 else if (RGE_TYPE_R25D(sc)) 810 rxconf = RGE_RXCFG_CONFIG_8125D; 811 else 812 rxconf = RGE_RXCFG_CONFIG_8126; 813 RGE_WRITE_4(sc, RGE_RXCFG, rxconf); 814 RGE_WRITE_4(sc, RGE_TXCFG, RGE_TXCFG_CONFIG); 815 816 val = rge_read_csi(sc, 0x70c) & ~0x3f000000; 817 rge_write_csi(sc, 0x70c, val | 0x27000000); 818 819 if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) { 820 /* Disable L1 timeout. */ 821 val = rge_read_csi(sc, 0x890) & ~0x00000001; 822 rge_write_csi(sc, 0x890, val); 823 } else if (!RGE_TYPE_R25D(sc)) 824 RGE_WRITE_2(sc, 0x0382, 0x221b); 825 826 RGE_WRITE_1(sc, RGE_RSS_CTRL, 0); 827 RGE_WRITE_2(sc, RGE_RXQUEUE_CTRL, 0); 828 RGE_CLRBIT_1(sc, RGE_CFG1, RGE_CFG1_SPEED_DOWN); 829 830 rge_write_mac_ocp(sc, 0xc140, 0xffff); 831 rge_write_mac_ocp(sc, 0xc142, 0xffff); 832 833 RGE_MAC_SETBIT(sc, 0xeb58, 0x0001); 834 835 if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) { 836 RGE_CLRBIT_1(sc, 0xd8, 0x02); 837 if (sc->rge_type == MAC_R27) { 838 RGE_CLRBIT_1(sc, 0x20e4, 0x04); 839 RGE_MAC_CLRBIT(sc, 0xe00c, 0x1000); 840 RGE_MAC_CLRBIT(sc, 0xc0c2, 0x0040); 841 } 842 } 843 844 val = rge_read_mac_ocp(sc, 0xe614); 845 val &= (sc->rge_type == MAC_R27) ? ~0x0f00 : ~0x0700; 846 if (sc->rge_type == MAC_R25 || RGE_TYPE_R25D(sc)) 847 rge_write_mac_ocp(sc, 0xe614, val | 0x0300); 848 else if (sc->rge_type == MAC_R25B) 849 rge_write_mac_ocp(sc, 0xe614, val | 0x0200); 850 else if (RGE_TYPE_R26(sc)) 851 rge_write_mac_ocp(sc, 0xe614, val | 0x0300); 852 else 853 rge_write_mac_ocp(sc, 0xe614, val | 0x0f00); 854 855 RGE_MAC_CLRBIT(sc, 0xe63e, 0x0c00); 856 857 RGE_MAC_CLRBIT(sc, 0xe63e, 0x0030); 858 859 val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0030; 860 rge_write_mac_ocp(sc, 0xe63e, val | 0x0020); 861 862 RGE_MAC_CLRBIT(sc, 0xc0b4, 0x0001); 863 RGE_MAC_SETBIT(sc, 0xc0b4, 0x0001); 864 865 RGE_MAC_SETBIT(sc, 0xc0b4, 0x000c); 866 867 val = rge_read_mac_ocp(sc, 0xeb6a) & ~0x00ff; 868 rge_write_mac_ocp(sc, 0xeb6a, val | 0x0033); 869 870 val = rge_read_mac_ocp(sc, 0xeb50) & ~0x03e0; 871 rge_write_mac_ocp(sc, 0xeb50, val | 0x0040); 872 873 RGE_MAC_CLRBIT(sc, 0xe056, 0x00f0); 874 875 RGE_WRITE_1(sc, RGE_TDFNR, 0x10); 876 877 RGE_MAC_CLRBIT(sc, 0xe040, 0x1000); 878 879 val = rge_read_mac_ocp(sc, 0xea1c) & ~0x0003; 880 rge_write_mac_ocp(sc, 0xea1c, val | 0x0001); 881 882 if (RGE_TYPE_R25D(sc)) 883 rge_write_mac_ocp(sc, 0xe0c0, 0x4403); 884 else 885 rge_write_mac_ocp(sc, 0xe0c0, 0x4000); 886 887 RGE_MAC_SETBIT(sc, 0xe052, 0x0060); 888 RGE_MAC_CLRBIT(sc, 0xe052, 0x0088); 889 890 val = rge_read_mac_ocp(sc, 0xd430) & ~0x0fff; 891 rge_write_mac_ocp(sc, 0xd430, val | 0x045f); 892 893 RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_PFM_EN | RGE_DLLPR_TX_10M_PS_EN); 894 895 if (sc->rge_type == MAC_R25) 896 RGE_SETBIT_1(sc, RGE_MCUCMD, 0x01); 897 898 if (!RGE_TYPE_R25D(sc)) { 899 /* Disable EEE plus. */ 900 RGE_MAC_CLRBIT(sc, 0xe080, 0x0002); 901 } 902 903 if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) 904 RGE_MAC_CLRBIT(sc, 0xea1c, 0x0304); 905 else 906 RGE_MAC_CLRBIT(sc, 0xea1c, 0x0004); 907 908 /* Clear tcam entries. */ 909 RGE_MAC_SETBIT(sc, 0xeb54, 0x0001); 910 DELAY(1); 911 RGE_MAC_CLRBIT(sc, 0xeb54, 0x0001); 912 913 RGE_CLRBIT_2(sc, 0x1880, 0x0030); 914 915 if (sc->rge_type == MAC_R27) { 916 val = rge_read_mac_ocp(sc, 0xd40c) & ~0xe038; 917 rge_write_phy_ocp(sc, 0xd40c, val | 0x8020); 918 } 919 920 /* Config interrupt type. */ 921 if (sc->rge_type == MAC_R27) 922 RGE_CLRBIT_1(sc, RGE_INT_CFG0, RGE_INT_CFG0_AVOID_MISS_INTR); 923 else if (sc->rge_type != MAC_R25) 924 RGE_CLRBIT_1(sc, RGE_INT_CFG0, RGE_INT_CFG0_EN); 925 926 /* Clear timer interrupts. */ 927 RGE_WRITE_4(sc, RGE_TIMERINT0, 0); 928 RGE_WRITE_4(sc, RGE_TIMERINT1, 0); 929 RGE_WRITE_4(sc, RGE_TIMERINT2, 0); 930 RGE_WRITE_4(sc, RGE_TIMERINT3, 0); 931 932 num_miti = 933 (sc->rge_type == MAC_R25B || RGE_TYPE_R26(sc)) ? 32 : 64; 934 /* Clear interrupt moderation timer. */ 935 for (i = 0; i < num_miti; i++) 936 RGE_WRITE_4(sc, RGE_INTMITI(i), 0); 937 938 if (RGE_TYPE_R26(sc)) { 939 RGE_CLRBIT_1(sc, RGE_INT_CFG0, 940 RGE_INT_CFG0_TIMEOUT_BYPASS | RGE_INT_CFG0_RDU_BYPASS_8126 | 941 RGE_INT_CFG0_MITIGATION_BYPASS); 942 RGE_WRITE_2(sc, RGE_INT_CFG1, 0); 943 } 944 945 RGE_MAC_SETBIT(sc, 0xc0ac, 0x1f80); 946 947 rge_write_mac_ocp(sc, 0xe098, 0xc302); 948 949 RGE_MAC_CLRBIT(sc, 0xe032, 0x0003); 950 val = rge_read_csi(sc, 0x98) & ~0x0000ff00; 951 rge_write_csi(sc, 0x98, val); 952 953 if (RGE_TYPE_R25D(sc)) { 954 val = rge_read_mac_ocp(sc, 0xe092) & ~0x00ff; 955 rge_write_mac_ocp(sc, 0xe092, val | 0x0008); 956 } else 957 RGE_MAC_CLRBIT(sc, 0xe092, 0x00ff); 958 959 if (ifp->if_capabilities & ETHERCAP_VLAN_HWTAGGING) 960 RGE_SETBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP); 961 962 RGE_SETBIT_2(sc, RGE_CPLUSCMD, RGE_CPLUSCMD_RXCSUM); 963 RGE_READ_2(sc, RGE_CPLUSCMD); 964 965 /* Set Maximum frame size. */ 966 RGE_WRITE_2(sc, RGE_RXMAXSIZE, RGE_JUMBO_FRAMELEN); 967 968 /* Disable RXDV gate. */ 969 RGE_CLRBIT_1(sc, RGE_PPSW, 0x08); 970 DELAY(2000); 971 972 /* Program promiscuous mode and multicast filters. */ 973 sc->sc_if_flags = ifp->if_flags; 974 rge_iff(sc); 975 976 if (sc->rge_type == MAC_R27) 977 RGE_CLRBIT_1(sc, RGE_RADMFIFO_PROTECT, 0x2001); 978 979 rge_disable_aspm_clkreq(sc); 980 981 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); 982 DELAY(10); 983 984 rge_ifmedia_upd(ifp); 985 986 /* Enable transmit and receive. */ 987 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_TXENB | RGE_CMD_RXENB); 988 989 /* Enable interrupts. */ 990 rge_setup_intr(sc, RGE_IMTYPE_SIM); 991 992 ifp->if_flags |= IFF_RUNNING; 993 sc->sc_if_flags |= IFF_RUNNING; 994 CLR(ifp->if_flags, IFF_OACTIVE); 995 996 callout_schedule(&sc->sc_timeout, 1); 997 998 return error; 999 } 1000 1001 static int 1002 rge_init(struct ifnet *ifp) 1003 { 1004 struct rge_softc *sc = ifp->if_softc; 1005 int error; 1006 1007 RGE_LOCK(sc); 1008 error = rge_init_locked(sc); 1009 RGE_UNLOCK(sc); 1010 1011 return error; 1012 } 1013 1014 /* 1015 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1016 */ 1017 static void 1018 rge_stop_locked(struct rge_softc *sc, int disable) 1019 { 1020 struct ifnet *ifp = &sc->sc_ec.ec_if; 1021 struct rge_queues *q = sc->sc_queues; 1022 unsigned i; 1023 1024 callout_halt(&sc->sc_timeout, NULL); 1025 1026 ifp->if_timer = 0; 1027 ifp->if_flags &= ~IFF_RUNNING; 1028 sc->sc_if_flags &= ~IFF_RUNNING; 1029 sc->rge_timerintr = 0; 1030 1031 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV | 1032 RGE_RXCFG_MULTI | RGE_RXCFG_BROAD | RGE_RXCFG_RUNT | 1033 RGE_RXCFG_ERRPKT); 1034 1035 rge_hw_reset(sc); 1036 1037 RGE_MAC_CLRBIT(sc, 0xc0ac, 0x1f80); 1038 1039 // intr_barrier(sc->sc_ih); 1040 // ifq_barrier(&ifp->if_snd); 1041 /* ifq_clr_oactive(&ifp->if_snd); Sevan - OpenBSD queue API */ 1042 1043 if (q->q_rx.rge_head != NULL) { 1044 m_freem(q->q_rx.rge_head); 1045 q->q_rx.rge_head = NULL; 1046 q->q_rx.rge_tail = NULL; 1047 } 1048 1049 /* Free the TX list buffers. */ 1050 for (i = 0; i < RGE_TX_LIST_CNT; i++) { 1051 if (q->q_tx.rge_txq[i].txq_mbuf != NULL) { 1052 bus_dmamap_unload(sc->sc_dmat, 1053 q->q_tx.rge_txq[i].txq_dmamap); 1054 m_freem(q->q_tx.rge_txq[i].txq_mbuf); 1055 q->q_tx.rge_txq[i].txq_mbuf = NULL; 1056 } 1057 } 1058 1059 /* Free the RX list buffers. */ 1060 for (i = 0; i < RGE_RX_LIST_CNT; i++) { 1061 if (q->q_rx.rge_rxq[i].rxq_mbuf != NULL) { 1062 bus_dmamap_unload(sc->sc_dmat, 1063 q->q_rx.rge_rxq[i].rxq_dmamap); 1064 m_freem(q->q_rx.rge_rxq[i].rxq_mbuf); 1065 q->q_rx.rge_rxq[i].rxq_mbuf = NULL; 1066 } 1067 } 1068 } 1069 1070 static void 1071 rge_stop(struct ifnet *ifp, int disable) 1072 { 1073 struct rge_softc *sc = ifp->if_softc; 1074 1075 RGE_LOCK(sc); 1076 rge_stop_locked(sc, disable); 1077 RGE_UNLOCK(sc); 1078 } 1079 1080 1081 /* 1082 * Set media options. 1083 */ 1084 static int 1085 rge_ifmedia_upd_sds(struct rge_softc *sc) 1086 { 1087 struct ifmedia *ifm = &sc->sc_media; 1088 uint16_t val; 1089 1090 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1091 case IFM_1000_LX: 1092 /* index 0, page 1, register 31 */ 1093 val = rge_read_sds(sc, 0x003f); 1094 val &= ~0x0008; 1095 rge_write_sds(sc, 0x003f, val); 1096 1097 /* index 0, page 2, register 0 */ 1098 val = rge_read_sds(sc, 0x0040); 1099 val &= ~0x3040; 1100 val |= 0x0040; 1101 rge_write_sds(sc, 0x0040, val); 1102 1103 rge_reset_sds(sc); 1104 break; 1105 case IFM_10G_LR: 1106 case IFM_AUTO: 1107 rge_reset_sds(sc); 1108 1109 RGE_WRITE_2(sc, 0x233a, 0x801a); 1110 val = RGE_READ_2(sc, 0x233e); 1111 val &= 0x3003; 1112 val |= 0x1000; 1113 RGE_WRITE_2(sc, 0x233e, val); 1114 1115 rge_write_phy_ocp(sc, 0xc40a, 0x0000); 1116 rge_write_phy_ocp(sc, 0xc466, 0x0003); 1117 rge_write_phy_ocp(sc, 0xc808, 0x0000); 1118 rge_write_phy_ocp(sc, 0xc80a, 0x0000); 1119 1120 val = rge_read_phy_ocp(sc, 0xc804); 1121 val &= ~0x000f; 1122 val |= 0x000c; 1123 rge_write_phy_ocp(sc, 0xc804, val); 1124 break; 1125 default: 1126 return EINVAL; 1127 } 1128 1129 return 0; 1130 } 1131 1132 static int 1133 rge_ifmedia_upd(struct ifnet *ifp) 1134 { 1135 struct rge_softc *sc = ifp->if_softc; 1136 struct ifmedia *ifm = &sc->sc_media; 1137 int anar, gig, val; 1138 1139 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1140 return (EINVAL); 1141 1142 /* Disable Gigabit Lite. */ 1143 RGE_PHY_CLRBIT(sc, 0xa428, 0x0200); 1144 RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001); 1145 if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) 1146 RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0007); 1147 1148 if (sc->rge_sfpmode == RGE_SFPMODE_RTL8127ATF) 1149 return rge_ifmedia_upd_sds(sc); 1150 1151 val = rge_read_phy_ocp(sc, 0xa5d4); 1152 switch (sc->rge_type) { 1153 case MAC_R27: 1154 val &= ~RGE_ADV_10000TFDX; 1155 /* fallthrough */ 1156 case MAC_R26_1: 1157 case MAC_R26_2: 1158 val &= ~RGE_ADV_5000TFDX; 1159 /* fallthrough */ 1160 default: 1161 val &= ~RGE_ADV_2500TFDX; 1162 break; 1163 } 1164 1165 anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1166 gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1167 1168 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1169 case IFM_AUTO: 1170 val |= RGE_ADV_2500TFDX; 1171 if (RGE_TYPE_R26(sc)) 1172 val |= RGE_ADV_5000TFDX; 1173 else if (sc->rge_type == MAC_R27) 1174 val |= RGE_ADV_5000TFDX | RGE_ADV_10000TFDX; 1175 break; 1176 case IFM_10G_T: 1177 val |= RGE_ADV_10000TFDX; 1178 ifp->if_baudrate = IF_Gbps(10); 1179 break; 1180 case IFM_5000_T: 1181 val |= RGE_ADV_5000TFDX; 1182 ifp->if_baudrate = IF_Gbps(5); 1183 break; 1184 case IFM_2500_T: 1185 val |= RGE_ADV_2500TFDX; 1186 ifp->if_baudrate = IF_Mbps(2500); 1187 break; 1188 case IFM_1000_T: 1189 ifp->if_baudrate = IF_Gbps(1); 1190 break; 1191 case IFM_100_TX: 1192 gig = rge_read_phy(sc, 0, MII_100T2CR) & 1193 ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 1194 anar = ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) ? 1195 ANAR_TX | ANAR_TX_FD | ANAR_10_FD | ANAR_10 : 1196 ANAR_TX | ANAR_10_FD | ANAR_10; 1197 ifp->if_baudrate = IF_Mbps(100); 1198 break; 1199 case IFM_10_T: 1200 gig = rge_read_phy(sc, 0, MII_100T2CR) & 1201 ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); 1202 anar = ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) ? 1203 ANAR_10_FD | ANAR_10 : ANAR_10; 1204 ifp->if_baudrate = IF_Mbps(10); 1205 break; 1206 default: 1207 device_printf(sc->sc_dev, 1208 "unsupported media type\n"); 1209 return (EINVAL); 1210 } 1211 1212 rge_write_phy(sc, 0, MII_ANAR, anar | ANAR_PAUSE_ASYM | ANAR_FC); 1213 rge_write_phy(sc, 0, MII_100T2CR, gig); 1214 rge_write_phy_ocp(sc, 0xa5d4, val); 1215 rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | 1216 BMCR_STARTNEG); 1217 1218 return (0); 1219 } 1220 1221 /* 1222 * Report current media status. 1223 */ 1224 static void 1225 rge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1226 { 1227 struct rge_softc *sc = ifp->if_softc; 1228 uint16_t status = 0; 1229 1230 ifmr->ifm_status = IFM_AVALID; 1231 ifmr->ifm_active = IFM_ETHER; 1232 1233 if (rge_get_link_status(sc)) { 1234 ifmr->ifm_status |= IFM_ACTIVE; 1235 1236 status = RGE_READ_2(sc, RGE_PHYSTAT); 1237 if ((status & RGE_PHYSTAT_FDX) || 1238 (status & (RGE_PHYSTAT_1000MBPS | RGE_PHYSTAT_2500MBPS | 1239 RGE_PHYSTAT_5000MBPS | RGE_PHYSTAT_10000MBPS))) 1240 ifmr->ifm_active |= IFM_FDX; 1241 else 1242 ifmr->ifm_active |= IFM_HDX; 1243 1244 if (sc->rge_sfpmode == RGE_SFPMODE_RTL8127ATF) { 1245 if (status & RGE_PHYSTAT_1000MBPS) 1246 ifmr->ifm_active |= IFM_1000_LX; 1247 else if (status & RGE_PHYSTAT_10000MBPS) 1248 ifmr->ifm_active |= IFM_10G_LR; 1249 } else { 1250 if (status & RGE_PHYSTAT_10MBPS) 1251 ifmr->ifm_active |= IFM_10_T; 1252 else if (status & RGE_PHYSTAT_100MBPS) 1253 ifmr->ifm_active |= IFM_100_TX; 1254 else if (status & RGE_PHYSTAT_1000MBPS) 1255 ifmr->ifm_active |= IFM_1000_T; 1256 else if (status & RGE_PHYSTAT_2500MBPS) 1257 ifmr->ifm_active |= IFM_2500_T; 1258 else if (status & RGE_PHYSTAT_5000MBPS) 1259 ifmr->ifm_active |= IFM_5000_T; 1260 else if (status & RGE_PHYSTAT_10000MBPS) 1261 ifmr->ifm_active |= IFM_10G_T; 1262 } 1263 } 1264 } 1265 1266 /* 1267 * Allocate memory for RX/TX rings. 1268 * 1269 * XXX There is no tear-down for this if it any part fails, so everything 1270 * remains allocated. 1271 */ 1272 static int 1273 rge_allocmem(struct rge_softc *sc) 1274 { 1275 struct rge_queues *q = sc->sc_queues; 1276 int error, i; 1277 1278 /* Allocate DMA'able memory for the TX ring. */ 1279 error = bus_dmamap_create(sc->sc_dmat, RGE_TX_LIST_SZ, 1, 1280 RGE_TX_LIST_SZ, 0, BUS_DMA_NOWAIT, &q->q_tx.rge_tx_list_map); 1281 if (error) { 1282 aprint_error_dev(sc->sc_dev, "can't create TX list map\n"); 1283 return (error); 1284 } 1285 error = bus_dmamem_alloc(sc->sc_dmat, RGE_TX_LIST_SZ, RGE_ALIGN, 0, 1286 &q->q_tx.rge_tx_listseg, 1, &q->q_tx.rge_tx_listnseg, 1287 BUS_DMA_NOWAIT); 1288 if (error) { 1289 aprint_error_dev(sc->sc_dev, "can't alloc TX list\n"); 1290 return (error); 1291 } 1292 1293 /* Load the map for the TX ring. */ 1294 error = bus_dmamem_map(sc->sc_dmat, &q->q_tx.rge_tx_listseg, 1295 q->q_tx.rge_tx_listnseg, RGE_TX_LIST_SZ, 1296 (void **) &q->q_tx.rge_tx_list, 1297 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 1298 if (error) { 1299 aprint_error_dev(sc->sc_dev, "can't map TX dma buffers\n"); 1300 bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, 1301 q->q_tx.rge_tx_listnseg); 1302 return (error); 1303 } 1304 memset(q->q_tx.rge_tx_list, 0, RGE_TX_LIST_SZ); 1305 error = bus_dmamap_load(sc->sc_dmat, q->q_tx.rge_tx_list_map, 1306 q->q_tx.rge_tx_list, RGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 1307 if (error) { 1308 aprint_error_dev(sc->sc_dev, "can't load TX dma map\n"); 1309 bus_dmamap_destroy(sc->sc_dmat, q->q_tx.rge_tx_list_map); 1310 bus_dmamem_unmap(sc->sc_dmat, 1311 q->q_tx.rge_tx_list, RGE_TX_LIST_SZ); 1312 bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, 1313 q->q_tx.rge_tx_listnseg); 1314 return (error); 1315 } 1316 1317 /* Create DMA maps for TX buffers. */ 1318 for (i = 0; i < RGE_TX_LIST_CNT; i++) { 1319 error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, 1320 RGE_TX_NSEGS, RGE_JUMBO_FRAMELEN, 0, 0, 1321 &q->q_tx.rge_txq[i].txq_dmamap); 1322 if (error) { 1323 aprint_error_dev(sc->sc_dev, "can't create DMA map for TX\n"); 1324 return (error); 1325 } 1326 } 1327 1328 /* Allocate DMA'able memory for the RX ring. */ 1329 error = bus_dmamap_create(sc->sc_dmat, RGE_RX_LIST_SZ, 1, 1330 RGE_RX_LIST_SZ, 0, 0, &q->q_rx.rge_rx_list_map); 1331 if (error) { 1332 aprint_error_dev(sc->sc_dev, "can't create RX list map\n"); 1333 return (error); 1334 } 1335 error = bus_dmamem_alloc(sc->sc_dmat, RGE_RX_LIST_SZ, RGE_ALIGN, 0, 1336 &q->q_rx.rge_rx_listseg, 1, &q->q_rx.rge_rx_listnseg, 1337 BUS_DMA_NOWAIT); 1338 if (error) { 1339 aprint_error_dev(sc->sc_dev, "can't alloc RX list\n"); 1340 return (error); 1341 } 1342 1343 /* Load the map for the RX ring. */ 1344 error = bus_dmamem_map(sc->sc_dmat, &q->q_rx.rge_rx_listseg, 1345 q->q_rx.rge_rx_listnseg, RGE_RX_LIST_SZ, 1346 (void **) &q->q_rx.rge_rx_list, 1347 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 1348 if (error) { 1349 aprint_error_dev(sc->sc_dev, "can't map RX dma buffers\n"); 1350 bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, 1351 q->q_rx.rge_rx_listnseg); 1352 return (error); 1353 } 1354 memset(q->q_rx.rge_rx_list, 0, RGE_RX_LIST_SZ); 1355 error = bus_dmamap_load(sc->sc_dmat, q->q_rx.rge_rx_list_map, 1356 q->q_rx.rge_rx_list, RGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 1357 if (error) { 1358 aprint_error_dev(sc->sc_dev, "can't load RX dma map\n"); 1359 bus_dmamap_destroy(sc->sc_dmat, q->q_rx.rge_rx_list_map); 1360 bus_dmamem_unmap(sc->sc_dmat, 1361 q->q_rx.rge_rx_list, RGE_RX_LIST_SZ); 1362 bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, 1363 q->q_rx.rge_rx_listnseg); 1364 return (error); 1365 } 1366 1367 /* 1368 * Create DMA maps for RX buffers. Use BUS_DMA_ALLOCNOW to avoid any 1369 * potential failure in bus_dmamap_load_mbuf() in the RX path. 1370 */ 1371 for (i = 0; i < RGE_RX_LIST_CNT; i++) { 1372 error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, 1, 1373 RGE_JUMBO_FRAMELEN, 0, BUS_DMA_ALLOCNOW, 1374 &q->q_rx.rge_rxq[i].rxq_dmamap); 1375 if (error) { 1376 aprint_error_dev(sc->sc_dev, "can't create DMA map for RX\n"); 1377 return (error); 1378 } 1379 } 1380 1381 return (error); 1382 } 1383 1384 /* 1385 * release memory allocated to RX/TX rings 1386 */ 1387 static int 1388 rge_deallocmem(struct rge_softc *sc) 1389 { 1390 struct rge_queues *q = sc->sc_queues; 1391 int i; 1392 1393 /* Destroy DMA maps for RX buffers */ 1394 for (i = 0; i < RGE_RX_LIST_CNT; i++) 1395 bus_dmamap_destroy(sc->sc_dmat, 1396 q->q_rx.rge_rxq[i].rxq_dmamap); 1397 1398 /* Unload the map for the RX ring */ 1399 bus_dmamap_unload(sc->sc_dmat, q->q_rx.rge_rx_list_map); 1400 bus_dmamem_unmap(sc->sc_dmat, 1401 q->q_rx.rge_rx_list, RGE_RX_LIST_SZ); 1402 1403 /* Deallocate DMA'able memory for the RX ring. */ 1404 bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg, 1405 q->q_rx.rge_rx_listnseg); 1406 bus_dmamap_destroy(sc->sc_dmat, q->q_rx.rge_rx_list_map); 1407 1408 /* Destroy DMA maps for TX buffers. */ 1409 for (i = 0; i < RGE_TX_LIST_CNT; i++) 1410 bus_dmamap_destroy(sc->sc_dmat, 1411 q->q_tx.rge_txq[i].txq_dmamap); 1412 1413 /* Unload the map for the TX ring */ 1414 bus_dmamap_unload(sc->sc_dmat, q->q_tx.rge_tx_list_map); 1415 bus_dmamem_unmap(sc->sc_dmat, 1416 q->q_tx.rge_tx_list_map, RGE_TX_LIST_SZ); 1417 1418 /* Deallocate DMA'able memory for the TX ring. */ 1419 bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg, 1420 q->q_tx.rge_tx_listnseg); 1421 bus_dmamap_destroy(sc->sc_dmat, q->q_tx.rge_tx_list_map); 1422 1423 return 0; 1424 } 1425 1426 /* 1427 * Set an RX descriptor and sync it. 1428 */ 1429 static void 1430 rge_load_rxbuf(struct rge_queues *q, int idx) 1431 { 1432 struct rge_softc *sc = q->q_sc; 1433 struct rge_rx_desc *r = &q->q_rx.rge_rx_list[idx]; 1434 struct rge_rxq *rxq = &q->q_rx.rge_rxq[idx]; 1435 bus_dmamap_t rxmap = rxq->rxq_dmamap; 1436 uint32_t cmdsts; 1437 1438 cmdsts = rxmap->dm_segs[0].ds_len | RGE_RDCMDSTS_OWN; 1439 if (idx == RGE_RX_LIST_CNT - 1) 1440 cmdsts |= RGE_RDCMDSTS_EOR; 1441 1442 r->hi_qword0.rge_addr = htole64(rxmap->dm_segs[0].ds_addr); 1443 r->hi_qword1.rx_qword4.rge_extsts = 0; 1444 r->hi_qword1.rx_qword4.rge_cmdsts = htole32(cmdsts); 1445 1446 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, 1447 idx * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc), 1448 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1449 } 1450 1451 /* 1452 * Initialize the RX descriptor and attach an mbuf cluster. 1453 */ 1454 static int 1455 rge_newbuf(struct rge_queues *q, int idx) 1456 { 1457 struct rge_softc *sc = q->q_sc; 1458 struct mbuf *m; 1459 struct rge_rxq *rxq; 1460 bus_dmamap_t rxmap; 1461 int error __diagused; 1462 1463 MGETHDR(m, M_DONTWAIT, MT_DATA); 1464 if (m == NULL) 1465 return (ENOBUFS); 1466 MCLAIM(m, &sc->sc_ec.ec_rx_mowner); 1467 1468 MCLGET(m, M_DONTWAIT); 1469 if (!(m->m_flags & M_EXT)) { 1470 m_freem(m); 1471 return (ENOBUFS); 1472 } 1473 m->m_len = m->m_pkthdr.len = MCLBYTES; 1474 1475 m_adj(m, ETHER_ALIGN); 1476 1477 rxq = &q->q_rx.rge_rxq[idx]; 1478 rxmap = rxq->rxq_dmamap; 1479 1480 if (rxq->rxq_mbuf != NULL) 1481 bus_dmamap_unload(sc->sc_dmat, rxq->rxq_dmamap); 1482 1483 /* This map was created with BUS_DMA_ALLOCNOW so should never fail. */ 1484 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT); 1485 KASSERTMSG(error == 0, "error=%d", error); 1486 1487 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1488 BUS_DMASYNC_PREREAD); 1489 1490 /* Map the segments into RX descriptors. */ 1491 1492 rxq->rxq_mbuf = m; 1493 rge_load_rxbuf(q, idx); 1494 1495 return 0; 1496 } 1497 1498 static int 1499 rge_rx_list_init(struct rge_queues *q) 1500 { 1501 unsigned i; 1502 1503 q->q_rx.rge_rxq_prodidx = q->q_rx.rge_rxq_considx = 0; 1504 q->q_rx.rge_head = NULL; 1505 q->q_rx.rge_tail = NULL; 1506 1507 memset(q->q_rx.rge_rx_list, 0, RGE_RX_LIST_SZ); 1508 1509 for (i = 0; i < RGE_RX_LIST_CNT; i++) { 1510 q->q_rx.rge_rxq[i].rxq_mbuf = NULL; 1511 if (rge_newbuf(q, i) != 0) { 1512 rge_rx_list_fini(q); 1513 return (ENOBUFS); 1514 } 1515 } 1516 1517 return (0); 1518 } 1519 1520 static void 1521 rge_rx_list_fini(struct rge_queues *q) 1522 { 1523 struct rge_softc *sc = q->q_sc; 1524 unsigned i; 1525 1526 /* Free the RX list buffers. */ 1527 for (i = 0; i < RGE_RX_LIST_CNT; i++) { 1528 if (q->q_rx.rge_rxq[i].rxq_mbuf != NULL) { 1529 bus_dmamap_unload(sc->sc_dmat, 1530 q->q_rx.rge_rxq[i].rxq_dmamap); 1531 m_freem(q->q_rx.rge_rxq[i].rxq_mbuf); 1532 q->q_rx.rge_rxq[i].rxq_mbuf = NULL; 1533 } 1534 } 1535 } 1536 1537 static void 1538 rge_tx_list_init(struct rge_queues *q) 1539 { 1540 struct rge_softc *sc = q->q_sc; 1541 unsigned i; 1542 1543 memset(q->q_tx.rge_tx_list, 0, RGE_TX_LIST_SZ); 1544 1545 for (i = 0; i < RGE_TX_LIST_CNT; i++) 1546 q->q_tx.rge_txq[i].txq_mbuf = NULL; 1547 1548 bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, 0, 1549 q->q_tx.rge_tx_list_map->dm_mapsize, 1550 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1551 1552 q->q_tx.rge_txq_prodidx = q->q_tx.rge_txq_considx = 0; 1553 } 1554 1555 static int 1556 rge_rxeof(struct rge_softc *sc) 1557 { 1558 struct mbuf *m; 1559 struct rge_queues *q = sc->sc_queues; 1560 struct ifnet *ifp = &sc->sc_ec.ec_if; 1561 struct rge_rx_desc *cur_rx; 1562 struct rge_rxq *rxq; 1563 uint32_t rxstat, extsts; 1564 int i, total_len, rx = 0; 1565 1566 for (i = q->q_rx.rge_rxq_considx; ; i = RGE_NEXT_RX_DESC(i)) { 1567 /* Invalidate the descriptor memory. */ 1568 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map, 1569 i * sizeof(struct rge_rx_desc), sizeof(struct rge_rx_desc), 1570 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1571 1572 cur_rx = &q->q_rx.rge_rx_list[i]; 1573 1574 if (RGE_OWN(cur_rx)) 1575 break; 1576 1577 rxstat = letoh32(cur_rx->hi_qword1.rx_qword4.rge_cmdsts); 1578 extsts = letoh32(cur_rx->hi_qword1.rx_qword4.rge_extsts); 1579 1580 total_len = RGE_RXBYTES(cur_rx); 1581 rxq = &q->q_rx.rge_rxq[i]; 1582 m = rxq->rxq_mbuf; 1583 rx = 1; 1584 1585 /* Invalidate the RX mbuf. */ 1586 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_dmamap, 0, 1587 rxq->rxq_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1588 1589 if (rxstat & RGE_RDCMDSTS_SOF) { 1590 if (q->q_rx.rge_head != NULL) { 1591 m_freem(q->q_rx.rge_head); 1592 q->q_rx.rge_head = NULL; 1593 q->q_rx.rge_tail = NULL; 1594 } 1595 } 1596 1597 if (rxstat & RGE_RDCMDSTS_RXERRSUM) { 1598 if_statinc(ifp, if_ierrors); 1599 /* 1600 * If this is part of a multi-fragment packet, 1601 * discard all the pieces. 1602 */ 1603 if (q->q_rx.rge_head != NULL) { 1604 m_freem(q->q_rx.rge_head); 1605 q->q_rx.rge_head = NULL; 1606 q->q_rx.rge_tail = NULL; 1607 } 1608 rge_load_rxbuf(q, i); 1609 continue; 1610 } 1611 1612 /* 1613 * If allocating a replacement mbuf fails, 1614 * reload the current one. 1615 */ 1616 if (rge_newbuf(q, i) != 0) { 1617 if_statinc(ifp, if_iqdrops); 1618 if (q->q_rx.rge_head != NULL) { 1619 m_freem(q->q_rx.rge_head); 1620 q->q_rx.rge_head = NULL; 1621 q->q_rx.rge_tail = NULL; 1622 } 1623 rge_load_rxbuf(q, i); 1624 continue; 1625 } 1626 1627 m->m_pkthdr.len = m->m_len = total_len; 1628 m_set_rcvif(m, ifp); 1629 1630 if (q->q_rx.rge_head != NULL) { 1631 m_remove_pkthdr(m); 1632 q->q_rx.rge_tail->m_next = m; 1633 q->q_rx.rge_tail = m; 1634 q->q_rx.rge_head->m_pkthdr.len += m->m_len; 1635 } else { 1636 q->q_rx.rge_head = m; 1637 q->q_rx.rge_tail = m; 1638 } 1639 1640 if ((rxstat & RGE_RDCMDSTS_EOF) == 0) 1641 continue; 1642 1643 m = q->q_rx.rge_head; 1644 q->q_rx.rge_head = NULL; 1645 q->q_rx.rge_tail = NULL; 1646 1647 m->m_flags |= M_HASFCS; 1648 1649 /* Check IP header checksum. */ 1650 if ((extsts & RGE_RDEXTSTS_IPCSUMERR) && 1651 (extsts & RGE_RDEXTSTS_IPV4)) 1652 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1653 1654 /* Check TCP/UDP checksum. */ 1655 1656 if ((extsts & (RGE_RDEXTSTS_IPV4 | RGE_RDEXTSTS_IPV6)) && 1657 (((extsts & RGE_RDEXTSTS_TCPPKT) && 1658 (extsts & RGE_RDEXTSTS_TCPCSUMERR)) || 1659 ((extsts & RGE_RDEXTSTS_UDPPKT) && 1660 (extsts & RGE_RDEXTSTS_UDPCSUMERR)))) 1661 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1662 1663 if (extsts & RGE_RDEXTSTS_VTAG) { 1664 vlan_set_tag(m, 1665 bswap16(extsts & RGE_RDEXTSTS_VLAN_MASK)); 1666 } 1667 1668 if_percpuq_enqueue(ifp->if_percpuq, m); 1669 } 1670 1671 q->q_rx.rge_rxq_considx = i; 1672 1673 return (rx); 1674 } 1675 1676 static int 1677 rge_txeof(struct rge_softc *sc) 1678 { 1679 struct rge_queues *q = sc->sc_queues; 1680 struct ifnet *ifp = &sc->sc_ec.ec_if; 1681 struct rge_txq *txq; 1682 uint32_t txstat; 1683 int cons, idx, prod; 1684 int free = 0; 1685 1686 prod = q->q_tx.rge_txq_prodidx; 1687 cons = q->q_tx.rge_txq_considx; 1688 1689 while (prod != cons) { 1690 txq = &q->q_tx.rge_txq[cons]; 1691 idx = txq->txq_descidx; 1692 1693 bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, 1694 idx * sizeof(struct rge_tx_desc), 1695 sizeof(struct rge_tx_desc), 1696 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1697 1698 txstat = letoh32(q->q_tx.rge_tx_list[idx].rge_cmdsts); 1699 1700 if (txstat & RGE_TDCMDSTS_OWN) { 1701 free = 2; 1702 break; 1703 } 1704 1705 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 0, 1706 txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1707 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1708 m_freem(txq->txq_mbuf); 1709 txq->txq_mbuf = NULL; 1710 1711 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1712 if (txstat & (RGE_TDCMDSTS_EXCESSCOLL | RGE_TDCMDSTS_COLL)) 1713 if_statinc_ref(ifp, nsr, if_collisions); 1714 if (txstat & RGE_TDCMDSTS_TXERR) 1715 if_statinc_ref(ifp, nsr, if_oerrors); 1716 else 1717 if_statinc_ref(ifp, nsr, if_opackets); 1718 IF_STAT_PUTREF(ifp); 1719 1720 bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, 1721 idx * sizeof(struct rge_tx_desc), 1722 sizeof(struct rge_tx_desc), 1723 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1724 1725 cons = RGE_NEXT_TX_DESC(idx); 1726 free = 1; 1727 } 1728 1729 if (free == 0) 1730 return (0); 1731 1732 q->q_tx.rge_txq_considx = cons; 1733 1734 if (free == 2) 1735 rge_txstart(sc); 1736 1737 CLR(ifp->if_flags, IFF_OACTIVE); 1738 ifp->if_timer = 0; 1739 if_schedule_deferred_start(ifp); 1740 1741 return (1); 1742 } 1743 1744 static int 1745 rge_reset(struct rge_softc *sc) 1746 { 1747 int i; 1748 1749 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV | 1750 RGE_RXCFG_MULTI | RGE_RXCFG_BROAD | RGE_RXCFG_RUNT | 1751 RGE_RXCFG_ERRPKT); 1752 1753 /* Enable RXDV gate. */ 1754 RGE_SETBIT_1(sc, RGE_PPSW, 0x08); 1755 1756 RGE_SETBIT_1(sc, RGE_CMD, RGE_CMD_STOPREQ); 1757 DELAY(200); 1758 1759 for (i = 0; i < 3000; i++) { 1760 DELAY(50); 1761 if ((RGE_READ_1(sc, RGE_MCUCMD) & (RGE_MCUCMD_RXFIFO_EMPTY | 1762 RGE_MCUCMD_TXFIFO_EMPTY)) == (RGE_MCUCMD_RXFIFO_EMPTY | 1763 RGE_MCUCMD_TXFIFO_EMPTY)) 1764 break; 1765 } 1766 if (sc->rge_type != MAC_R25) { 1767 for (i = 0; i < 3000; i++) { 1768 DELAY(50); 1769 if ((RGE_READ_2(sc, RGE_IM) & 0x0103) == 0x0103) 1770 break; 1771 } 1772 } 1773 1774 RGE_WRITE_1(sc, RGE_CMD, 1775 RGE_READ_1(sc, RGE_CMD) & (RGE_CMD_TXENB | RGE_CMD_RXENB)); 1776 1777 /* Soft reset. */ 1778 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET); 1779 1780 for (i = 0; i < RGE_TIMEOUT; i++) { 1781 DELAY(100); 1782 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_RESET)) 1783 break; 1784 } 1785 if (i == RGE_TIMEOUT) { 1786 device_printf(sc->sc_dev, "reset never completed!\n"); 1787 return ETIMEDOUT; 1788 } 1789 1790 return 0; 1791 } 1792 1793 static void 1794 rge_iff(struct rge_softc *sc) 1795 { 1796 struct ethercom *ec = &sc->sc_ec; 1797 struct ether_multi *enm; 1798 struct ether_multistep step; 1799 uint32_t hashes[2]; 1800 uint32_t rxfilt; 1801 int h = 0; 1802 1803 RGE_ASSERT_LOCKED(sc); 1804 1805 rxfilt = RGE_READ_4(sc, RGE_RXCFG); 1806 rxfilt &= ~(RGE_RXCFG_ALLPHYS | RGE_RXCFG_MULTI); 1807 ec->ec_flags &= ~ETHER_F_ALLMULTI; 1808 1809 /* 1810 * Always accept frames destined to our station address. 1811 * Always accept broadcast frames. 1812 */ 1813 rxfilt |= RGE_RXCFG_INDIV | RGE_RXCFG_BROAD; 1814 1815 if (sc->sc_if_flags & IFF_PROMISC) { 1816 allmulti: 1817 ec->ec_flags |= ETHER_F_ALLMULTI; 1818 rxfilt |= RGE_RXCFG_MULTI; 1819 if (sc->sc_if_flags & IFF_PROMISC) 1820 rxfilt |= RGE_RXCFG_ALLPHYS; 1821 hashes[0] = hashes[1] = 0xffffffff; 1822 } else { 1823 rxfilt |= RGE_RXCFG_MULTI; 1824 /* Program new filter. */ 1825 memset(hashes, 0, sizeof(hashes)); 1826 1827 ETHER_LOCK(ec); 1828 ETHER_FIRST_MULTI(step, ec, enm); 1829 while (enm != NULL) { 1830 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1831 ETHER_ADDR_LEN) != 0) { 1832 ETHER_UNLOCK(ec); 1833 goto allmulti; 1834 } 1835 h = ether_crc32_be(enm->enm_addrlo, 1836 ETHER_ADDR_LEN) >> 26; 1837 1838 if (h < 32) 1839 hashes[0] |= (1U << h); 1840 else 1841 hashes[1] |= (1U << (h - 32)); 1842 1843 ETHER_NEXT_MULTI(step, enm); 1844 } 1845 ETHER_UNLOCK(ec); 1846 } 1847 1848 RGE_WRITE_4(sc, RGE_RXCFG, rxfilt); 1849 RGE_WRITE_4(sc, RGE_MAR0, bswap32(hashes[1])); 1850 RGE_WRITE_4(sc, RGE_MAR4, bswap32(hashes[0])); 1851 } 1852 1853 static int 1854 rge_chipinit(struct rge_softc *sc) 1855 { 1856 int error; 1857 1858 if ((error = rge_exit_oob(sc)) != 0) 1859 return error; 1860 rge_set_phy_power(sc, 1); 1861 rge_hw_init(sc); 1862 rge_hw_reset(sc); 1863 1864 return 0; 1865 } 1866 1867 static void 1868 rge_set_phy_power(struct rge_softc *sc, int on) 1869 { 1870 int i; 1871 1872 if (on) { 1873 RGE_SETBIT_1(sc, RGE_PMCH, 0xc0); 1874 1875 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN); 1876 1877 for (i = 0; i < RGE_TIMEOUT; i++) { 1878 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 3) 1879 break; 1880 DELAY(1000); 1881 } 1882 } else { 1883 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN); 1884 RGE_CLRBIT_1(sc, RGE_PMCH, 0x80); 1885 RGE_CLRBIT_1(sc, RGE_PPSW, 0x40); 1886 } 1887 } 1888 1889 static void 1890 rge_mac_config_mcu(struct rge_softc *sc, enum rge_mac_type type) 1891 { 1892 uint16_t reg; 1893 int i, npages; 1894 1895 if (type == MAC_R25) { 1896 for (npages = 0; npages < 3; npages++) { 1897 rge_switch_mcu_ram_page(sc, npages); 1898 for (i = 0; i < nitems(rtl8125_mac_bps); i++) { 1899 if (npages == 0) 1900 rge_write_mac_ocp(sc, 1901 rtl8125_mac_bps[i].reg, 1902 rtl8125_mac_bps[i].val); 1903 else if (npages == 1) 1904 rge_write_mac_ocp(sc, 1905 rtl8125_mac_bps[i].reg, 0); 1906 else { 1907 if (rtl8125_mac_bps[i].reg < 0xf9f8) 1908 rge_write_mac_ocp(sc, 1909 rtl8125_mac_bps[i].reg, 0); 1910 } 1911 } 1912 if (npages == 2) { 1913 rge_write_mac_ocp(sc, 0xf9f8, 0x6486); 1914 rge_write_mac_ocp(sc, 0xf9fa, 0x0b15); 1915 rge_write_mac_ocp(sc, 0xf9fc, 0x090e); 1916 rge_write_mac_ocp(sc, 0xf9fe, 0x1139); 1917 } 1918 } 1919 rge_write_mac_ocp(sc, 0xfc26, 0x8000); 1920 rge_write_mac_ocp(sc, 0xfc2a, 0x0540); 1921 rge_write_mac_ocp(sc, 0xfc2e, 0x0a06); 1922 rge_write_mac_ocp(sc, 0xfc30, 0x0eb8); 1923 rge_write_mac_ocp(sc, 0xfc32, 0x3a5c); 1924 rge_write_mac_ocp(sc, 0xfc34, 0x10a8); 1925 rge_write_mac_ocp(sc, 0xfc40, 0x0d54); 1926 rge_write_mac_ocp(sc, 0xfc42, 0x0e24); 1927 rge_write_mac_ocp(sc, 0xfc48, 0x307a); 1928 } else if (type == MAC_R25B) { 1929 rge_switch_mcu_ram_page(sc, 0); 1930 for (i = 0; i < nitems(rtl8125b_mac_bps); i++) { 1931 rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg, 1932 rtl8125b_mac_bps[i].val); 1933 } 1934 } else if (type == MAC_R25D_1) { 1935 for (npages = 0; npages < 3; npages++) { 1936 rge_switch_mcu_ram_page(sc, npages); 1937 1938 rge_write_mac_ocp(sc, 0xf800, 1939 (npages == 0) ? 0xe002 : 0); 1940 rge_write_mac_ocp(sc, 0xf802, 1941 (npages == 0) ? 0xe006 : 0); 1942 rge_write_mac_ocp(sc, 0xf804, 1943 (npages == 0) ? 0x4166 : 0); 1944 rge_write_mac_ocp(sc, 0xf806, 1945 (npages == 0) ? 0x9cf6 : 0); 1946 rge_write_mac_ocp(sc, 0xf808, 1947 (npages == 0) ? 0xc002 : 0); 1948 rge_write_mac_ocp(sc, 0xf80a, 1949 (npages == 0) ? 0xb800 : 0); 1950 rge_write_mac_ocp(sc, 0xf80c, 1951 (npages == 0) ? 0x14a4 : 0); 1952 rge_write_mac_ocp(sc, 0xf80e, 1953 (npages == 0) ? 0xc102 : 0); 1954 rge_write_mac_ocp(sc, 0xf810, 1955 (npages == 0) ? 0xb900 : 0); 1956 1957 for (reg = 0xf812; reg <= 0xf9f6; reg += 2) 1958 rge_write_mac_ocp(sc, reg, 0); 1959 1960 rge_write_mac_ocp(sc, 0xf9f8, 1961 (npages == 2) ? 0x6938 : 0); 1962 rge_write_mac_ocp(sc, 0xf9fa, 1963 (npages == 2) ? 0x0a18 : 0); 1964 rge_write_mac_ocp(sc, 0xf9fc, 1965 (npages == 2) ? 0x0217 : 0); 1966 rge_write_mac_ocp(sc, 0xf9fe, 1967 (npages == 2) ? 0x0d2a : 0); 1968 } 1969 rge_write_mac_ocp(sc, 0xfc26, 0x8000); 1970 rge_write_mac_ocp(sc, 0xfc28, 0x14a2); 1971 rge_write_mac_ocp(sc, 0xfc48, 0x0001); 1972 } else if (type == MAC_R25D_2) { 1973 for (npages = 0; npages < 3; npages++) { 1974 rge_switch_mcu_ram_page(sc, npages); 1975 1976 for (i = 0; i < nitems(rtl8125d_2_mac_bps); i++) { 1977 if (npages == 0) 1978 rge_write_mac_ocp(sc, 1979 rtl8125d_2_mac_bps[i].reg, 1980 rtl8125d_2_mac_bps[i].val); 1981 else 1982 rge_write_mac_ocp(sc, 1983 rtl8125d_2_mac_bps[i].reg, 0); 1984 } 1985 1986 for (reg = 0xf884; reg <= 0xf9f6; reg += 2) 1987 rge_write_mac_ocp(sc, reg, 0); 1988 1989 rge_write_mac_ocp(sc, 0xf9f8, 1990 (npages == 2) ? 0x6938 : 0); 1991 rge_write_mac_ocp(sc, 0xf9fa, 1992 (npages == 2) ? 0x0a19: 0); 1993 rge_write_mac_ocp(sc, 0xf9fc, 1994 (npages == 2) ? 0x030e: 0); 1995 rge_write_mac_ocp(sc, 0xf9fe, 1996 (npages == 2) ? 0x0b2f: 0); 1997 } 1998 rge_write_mac_ocp(sc, 0xfc26, 0x8000); 1999 rge_write_mac_ocp(sc, 0xfc28, 0x2382); 2000 rge_write_mac_ocp(sc, 0xfc48, 0x0001); 2001 } 2002 } 2003 2004 static void 2005 rge_mac_config_ext_mcu(struct rge_softc *sc, enum rge_mac_type type) 2006 { 2007 const struct rge_mac_bps *bps; 2008 uint64_t mcodever = 0; 2009 int i; 2010 2011 /* Read microcode version. */ 2012 rge_switch_mcu_ram_page(sc, 2); 2013 sc->rge_mcodever = 0; 2014 for (i = 0; i < 8; i += 2) { 2015 sc->rge_mcodever <<= 16; 2016 sc->rge_mcodever |= rge_read_mac_ocp(sc, 0xf9f8 + i); 2017 } 2018 rge_switch_mcu_ram_page(sc, 0); 2019 2020 if (type == MAC_R26_1) { 2021 bps = &rtl8126_1_mac_bps; 2022 mcodever = 2023 rge_mcu_get_bin_version(rtl8126_1_mac_bps_vals, bps->count); 2024 if (sc->rge_mcodever != mcodever) { 2025 /* Switch to page 0. */ 2026 rge_switch_mcu_ram_page(sc, 0); 2027 for (i = 0; i < bps->count; i++) 2028 rge_write_mac_ocp(sc, bps->regs[i], 2029 bps->vals[i]); 2030 } 2031 rge_write_mac_ocp(sc, 0xfc26, 0x8000); 2032 rge_write_mac_ocp(sc, 0xfc2c, 0x2360); 2033 rge_write_mac_ocp(sc, 0xfc2e, 0x14a4); 2034 rge_write_mac_ocp(sc, 0xfc30, 0x415e); 2035 rge_write_mac_ocp(sc, 0xfc32, 0x41e4); 2036 rge_write_mac_ocp(sc, 0xfc34, 0x4280); 2037 rge_write_mac_ocp(sc, 0xfc36, 0x234a); 2038 rge_write_mac_ocp(sc, 0xfc48, 0x00fc); 2039 } else if (type == MAC_R26_2) { 2040 bps = &rtl8126_2_mac_bps; 2041 mcodever = 2042 rge_mcu_get_bin_version(rtl8126_2_mac_bps_vals, bps->count); 2043 if (sc->rge_mcodever != mcodever) { 2044 /* Switch to page 0. */ 2045 rge_switch_mcu_ram_page(sc, 0); 2046 for (i = 0; i < 256; i++) 2047 rge_write_mac_ocp(sc, bps->regs[i], 2048 bps->vals[i]); 2049 /* Switch to page 1. */ 2050 rge_switch_mcu_ram_page(sc, 1); 2051 for (; i < bps->count; i++) 2052 rge_write_mac_ocp(sc, bps->regs[i], 2053 bps->vals[i]); 2054 } 2055 rge_write_mac_ocp(sc, 0xfc26, 0x8000); 2056 rge_write_mac_ocp(sc, 0xfc2c, 0x14a4); 2057 rge_write_mac_ocp(sc, 0xfc2e, 0x4176); 2058 rge_write_mac_ocp(sc, 0xfc30, 0x41fc); 2059 rge_write_mac_ocp(sc, 0xfc32, 0x4298); 2060 rge_write_mac_ocp(sc, 0xfc3a, 0x234a); 2061 rge_write_mac_ocp(sc, 0xfc48, 0x023c); 2062 } else if (type == MAC_R27) { 2063 bps = &rtl8127_mac_bps; 2064 mcodever = 2065 rge_mcu_get_bin_version(rtl8127_mac_bps_vals, bps->count); 2066 if (sc->rge_mcodever != mcodever) { 2067 /* Switch to page 0. */ 2068 rge_switch_mcu_ram_page(sc, 0); 2069 for (i = 0; i < 256; i++) 2070 rge_write_mac_ocp(sc, bps->regs[i], 2071 bps->vals[i]); 2072 /* Switch to page 1. */ 2073 rge_switch_mcu_ram_page(sc, 1); 2074 for (; i < bps->count; i++) 2075 rge_write_mac_ocp(sc, bps->regs[i], 2076 bps->vals[i]); 2077 } 2078 rge_write_mac_ocp(sc, 0xfc26, 0x8000); 2079 rge_write_mac_ocp(sc, 0xfc28, 0x1520); 2080 rge_write_mac_ocp(sc, 0xfc2a, 0x41e0); 2081 rge_write_mac_ocp(sc, 0xfc2c, 0x508c); 2082 rge_write_mac_ocp(sc, 0xfc2e, 0x50f6); 2083 rge_write_mac_ocp(sc, 0xfc30, 0x34fa); 2084 rge_write_mac_ocp(sc, 0xfc32, 0x0166); 2085 rge_write_mac_ocp(sc, 0xfc34, 0x1a6a); 2086 rge_write_mac_ocp(sc, 0xfc36, 0x1a2c); 2087 rge_write_mac_ocp(sc, 0xfc48, 0x00ff); 2088 } 2089 2090 /* Write microcode version. */ 2091 rge_mcu_set_version(sc, mcodever); 2092 }; 2093 2094 static uint64_t 2095 rge_mcu_get_bin_version(const uint16_t *mac_bps, uint16_t entries) 2096 { 2097 uint64_t binver = 0; 2098 int i; 2099 2100 for (i = 0; i < 4; i++) { 2101 binver <<= 16; 2102 binver |= mac_bps[entries - 4 + i]; 2103 } 2104 2105 return binver; 2106 } 2107 2108 static void 2109 rge_mcu_set_version(struct rge_softc *sc, uint64_t mcodever) 2110 { 2111 int i; 2112 2113 /* Switch to page 2. */ 2114 rge_switch_mcu_ram_page(sc, 2); 2115 2116 for (i = 0; i < 8; i += 2) { 2117 rge_write_mac_ocp(sc, 0xf9f8 + 6 - i, (uint16_t)mcodever); 2118 mcodever >>= 16; 2119 } 2120 2121 /* Switch back to page 0. */ 2122 rge_switch_mcu_ram_page(sc, 0); 2123 } 2124 2125 static void 2126 rge_ephy_config(struct rge_softc *sc) 2127 { 2128 switch (sc->rge_type) { 2129 case MAC_R25: 2130 rge_ephy_config_mac_r25(sc); 2131 break; 2132 case MAC_R25B: 2133 rge_ephy_config_mac_r25b(sc); 2134 break; 2135 case MAC_R27: 2136 rge_ephy_config_mac_r27(sc); 2137 break; 2138 default: 2139 break; /* Nothing to do. */ 2140 } 2141 } 2142 2143 void 2144 rge_ephy_config_mac_r25(struct rge_softc *sc) 2145 { 2146 uint16_t val; 2147 int i; 2148 2149 for (i = 0; i < nitems(mac_r25_ephy); i++) 2150 rge_write_ephy(sc, mac_r25_ephy[i].reg, mac_r25_ephy[i].val); 2151 2152 val = rge_read_ephy(sc, 0x002a) & ~0x7000; 2153 rge_write_ephy(sc, 0x002a, val | 0x3000); 2154 RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040); 2155 RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00); 2156 RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000); 2157 rge_write_ephy(sc, 0x0002, 0x6042); 2158 rge_write_ephy(sc, 0x0006, 0x0014); 2159 val = rge_read_ephy(sc, 0x006a) & ~0x7000; 2160 rge_write_ephy(sc, 0x006a, val | 0x3000); 2161 RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040); 2162 RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00); 2163 RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000); 2164 rge_write_ephy(sc, 0x0042, 0x6042); 2165 rge_write_ephy(sc, 0x0046, 0x0014); 2166 } 2167 2168 void 2169 rge_ephy_config_mac_r25b(struct rge_softc *sc) 2170 { 2171 int i; 2172 2173 for (i = 0; i < nitems(mac_r25b_ephy); i++) 2174 rge_write_ephy(sc, mac_r25b_ephy[i].reg, mac_r25b_ephy[i].val); 2175 } 2176 2177 void 2178 rge_ephy_config_mac_r27(struct rge_softc *sc) 2179 { 2180 int i; 2181 2182 for (i = 0; i < nitems(mac_r27_ephy); i++) 2183 rge_r27_write_ephy(sc, mac_r27_ephy[i].reg, 2184 mac_r27_ephy[i].val); 2185 2186 /* Clear extended address. */ 2187 rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, 0); 2188 } 2189 2190 static int 2191 rge_phy_config(struct rge_softc *sc) 2192 { 2193 uint16_t val = 0; 2194 int i; 2195 2196 rge_ephy_config(sc); 2197 2198 /* PHY reset. */ 2199 rge_write_phy(sc, 0, MII_ANAR, 2200 rge_read_phy(sc, 0, MII_ANAR) & 2201 ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10)); 2202 rge_write_phy(sc, 0, MII_100T2CR, 2203 rge_read_phy(sc, 0, MII_100T2CR) & 2204 ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX)); 2205 switch (sc->rge_type) { 2206 case MAC_R27: 2207 val |= RGE_ADV_10000TFDX; 2208 /* fallthrough */ 2209 case MAC_R26_1: 2210 case MAC_R26_2: 2211 val |= RGE_ADV_5000TFDX; 2212 /* fallthrough */ 2213 default: 2214 val |= RGE_ADV_2500TFDX; 2215 break; 2216 } 2217 2218 RGE_PHY_CLRBIT(sc, 0xa5d4, val); 2219 rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | 2220 BMCR_STARTNEG); 2221 for (i = 0; i < 2500; i++) { 2222 if (!(rge_read_phy(sc, 0, MII_BMCR) & BMCR_RESET)) 2223 break; 2224 DELAY(1000); 2225 } 2226 if (i == 2500) { 2227 device_printf(sc->sc_dev, "PHY reset failed\n"); 2228 return (ETIMEDOUT); 2229 } 2230 2231 /* Read ram code version. */ 2232 rge_write_phy_ocp(sc, 0xa436, 0x801e); 2233 sc->rge_rcodever = rge_read_phy_ocp(sc, 0xa438); 2234 2235 /* Get fiber mode */ 2236 if (sc->rge_type == MAC_R27) 2237 sc->rge_sfpmode = rge_read_mac_ocp(sc, 0xd006); 2238 2239 switch (sc->rge_type) { 2240 case MAC_R25: 2241 rge_phy_config_mac_r25(sc); 2242 break; 2243 case MAC_R25B: 2244 rge_phy_config_mac_r25b(sc); 2245 break; 2246 case MAC_R25D_1: 2247 rge_phy_config_mac_r25d_1(sc); 2248 break; 2249 case MAC_R25D_2: 2250 rge_phy_config_mac_r25d_2(sc); 2251 break; 2252 case MAC_R26_1: 2253 rge_phy_config_mac_r26_1(sc); 2254 break; 2255 case MAC_R26_2: 2256 rge_phy_config_mac_r26_2(sc); 2257 break; 2258 case MAC_R27: 2259 rge_phy_config_mac_r27(sc); 2260 break; 2261 default: 2262 break; /* Can't happen. */ 2263 } 2264 RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000); 2265 2266 /* Disable EEE. */ 2267 RGE_MAC_CLRBIT(sc, 0xe040, 0x0003); 2268 if (sc->rge_type == MAC_R25) { 2269 RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006); 2270 RGE_PHY_CLRBIT(sc, 0xa432, 0x0010); 2271 } else if (sc->rge_type == MAC_R25B || RGE_TYPE_R25D(sc)) 2272 RGE_PHY_SETBIT(sc, 0xa432, 0x0010); 2273 2274 RGE_PHY_CLRBIT(sc, 0xa5d0, (sc->rge_type == MAC_R27) ? 0x000e : 0x0006); 2275 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001); 2276 if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) 2277 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002); 2278 RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010); 2279 RGE_PHY_CLRBIT(sc, 0xa428, 0x0080); 2280 RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200); 2281 2282 /* Disable advanced EEE. */ 2283 RGE_MAC_CLRBIT(sc, 0xe052, 0x0001); 2284 RGE_PHY_CLRBIT(sc, 0xa442, 0x3000); 2285 RGE_PHY_CLRBIT(sc, 0xa430, 0x8000); 2286 2287 return (0); 2288 } 2289 2290 static 2291 void 2292 rge_phy_config_mac_r27(struct rge_softc *sc) 2293 { 2294 uint16_t val; 2295 int i; 2296 static const uint16_t mac_cfg_value[] = 2297 { 0x815a, 0x0150, 0x81f4, 0x0150, 0x828e, 0x0150, 0x81b1, 0x0000, 2298 0x824b, 0x0000, 0x82e5, 0x0000 }; 2299 2300 static const uint16_t mac_cfg2_value[] = 2301 { 0x88d7, 0x01a0, 0x88d9, 0x01a0, 0x8ffa, 0x002a, 0x8fee, 0xffdf, 2302 0x8ff0, 0xffff, 0x8ff2, 0x0a4a, 0x8ff4, 0xaa5a, 0x8ff6, 0x0a4a, 2303 0x8ff8, 0xaa5a }; 2304 2305 static const uint16_t mac_cfg_a438_value[] = 2306 { 0x003b, 0x0086, 0x00b7, 0x00db, 0x00fe, 0x00fe, 0x00fe, 0x00fe, 2307 0x00c3, 0x0078, 0x0047, 0x0023 }; 2308 2309 rge_phy_config_mcu(sc, RGE_MAC_R27_RCODE_VER); 2310 2311 rge_write_phy_ocp(sc, 0xa4d2, 0x0000); 2312 rge_read_phy_ocp(sc, 0xa4d4); 2313 2314 RGE_PHY_CLRBIT(sc, 0xa442, 0x0800); 2315 rge_write_phy_ocp(sc, 0xa436, 0x8415); 2316 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2317 rge_write_phy_ocp(sc, 0xa438, val | 0x9300); 2318 rge_write_phy_ocp(sc, 0xa436, 0x81a3); 2319 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2320 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00); 2321 rge_write_phy_ocp(sc, 0xa436, 0x81ae); 2322 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2323 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00); 2324 rge_write_phy_ocp(sc, 0xa436, 0x81b9); 2325 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2326 rge_write_phy_ocp(sc, 0xa438, val | 0xb900); 2327 rge_write_phy_ocp(sc, 0xb87c, 0x83b0); 2328 RGE_PHY_CLRBIT(sc,0xb87e, 0x0e00); 2329 rge_write_phy_ocp(sc, 0xb87c, 0x83c5); 2330 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00); 2331 rge_write_phy_ocp(sc, 0xb87c, 0x83da); 2332 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00); 2333 rge_write_phy_ocp(sc, 0xb87c, 0x83ef); 2334 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00); 2335 val = rge_read_phy_ocp(sc, 0xbf38) & ~0x01f0; 2336 rge_write_phy_ocp(sc, 0xbf38, val | 0x0160); 2337 val = rge_read_phy_ocp(sc, 0xbf3a) & ~0x001f; 2338 rge_write_phy_ocp(sc, 0xbf3a, val | 0x0014); 2339 RGE_PHY_CLRBIT(sc, 0xbf28, 0x6000); 2340 RGE_PHY_CLRBIT(sc, 0xbf2c, 0xc000); 2341 val = rge_read_phy_ocp(sc, 0xbf28) & ~0x1fff; 2342 rge_write_phy_ocp(sc, 0xbf28, val | 0x0187); 2343 val = rge_read_phy_ocp(sc, 0xbf2a) & ~0x003f; 2344 rge_write_phy_ocp(sc, 0xbf2a, val | 0x0003); 2345 rge_write_phy_ocp(sc, 0xa436, 0x8173); 2346 rge_write_phy_ocp(sc, 0xa438, 0x8620); 2347 rge_write_phy_ocp(sc, 0xa436, 0x8175); 2348 rge_write_phy_ocp(sc, 0xa438, 0x8671); 2349 rge_write_phy_ocp(sc, 0xa436, 0x817c); 2350 RGE_PHY_SETBIT(sc, 0xa438, 0x2000); 2351 rge_write_phy_ocp(sc, 0xa436, 0x8187); 2352 RGE_PHY_SETBIT(sc, 0xa438, 0x2000); 2353 rge_write_phy_ocp(sc, 0xA436, 0x8192); 2354 RGE_PHY_SETBIT(sc, 0xA438, 0x2000); 2355 rge_write_phy_ocp(sc, 0xA436, 0x819D); 2356 RGE_PHY_SETBIT(sc, 0xA438, 0x2000); 2357 rge_write_phy_ocp(sc, 0xA436, 0x81A8); 2358 RGE_PHY_CLRBIT(sc, 0xA438, 0x2000); 2359 rge_write_phy_ocp(sc, 0xA436, 0x81B3); 2360 RGE_PHY_CLRBIT(sc, 0xA438, 0x2000); 2361 rge_write_phy_ocp(sc, 0xA436, 0x81BE); 2362 RGE_PHY_SETBIT(sc, 0xA438, 0x2000); 2363 rge_write_phy_ocp(sc, 0xa436, 0x817d); 2364 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2365 rge_write_phy_ocp(sc, 0xa438, val | 0xa600); 2366 rge_write_phy_ocp(sc, 0xa436, 0x8188); 2367 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2368 rge_write_phy_ocp(sc, 0xa438, val | 0xa600); 2369 rge_write_phy_ocp(sc, 0xa436, 0x8193); 2370 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2371 rge_write_phy_ocp(sc, 0xa438, val | 0xa600); 2372 rge_write_phy_ocp(sc, 0xa436, 0x819e); 2373 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2374 rge_write_phy_ocp(sc, 0xa438, val | 0xa600); 2375 rge_write_phy_ocp(sc, 0xa436, 0x81a9); 2376 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2377 rge_write_phy_ocp(sc, 0xa438, val | 0x1400); 2378 rge_write_phy_ocp(sc, 0xa436, 0x81b4); 2379 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2380 rge_write_phy_ocp(sc, 0xa438, val | 0x1400); 2381 rge_write_phy_ocp(sc, 0xa436, 0x81bf); 2382 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2383 rge_write_phy_ocp(sc, 0xa438, val | 0xa600); 2384 RGE_PHY_CLRBIT(sc, 0xaeaa, 0x0028); 2385 rge_write_phy_ocp(sc, 0xb87c, 0x84f0); 2386 rge_write_phy_ocp(sc, 0xb87e, 0x201c); 2387 rge_write_phy_ocp(sc, 0xb87c, 0x84f2); 2388 rge_write_phy_ocp(sc, 0xb87e, 0x3117); 2389 rge_write_phy_ocp(sc, 0xaec6, 0x0000); 2390 rge_write_phy_ocp(sc, 0xae20, 0xffff); 2391 rge_write_phy_ocp(sc, 0xaece, 0xffff); 2392 rge_write_phy_ocp(sc, 0xaed2, 0xffff); 2393 rge_write_phy_ocp(sc, 0xaec8, 0x0000); 2394 RGE_PHY_CLRBIT(sc, 0xaed0, 0x0001); 2395 rge_write_phy_ocp(sc, 0xadb8, 0x0150); 2396 rge_write_phy_ocp(sc, 0xb87c, 0x8197); 2397 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2398 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); 2399 rge_write_phy_ocp(sc, 0xb87c, 0x8231); 2400 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2401 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); 2402 rge_write_phy_ocp(sc, 0xb87c, 0x82cb); 2403 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2404 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); 2405 rge_write_phy_ocp(sc, 0xb87c, 0x82cd); 2406 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2407 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700); 2408 rge_write_phy_ocp(sc, 0xb87c, 0x8233); 2409 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2410 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700); 2411 rge_write_phy_ocp(sc, 0xb87c, 0x8199); 2412 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2413 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700); 2414 for (i = 0; i < nitems(mac_cfg_value); i+=2) { 2415 rge_write_phy_ocp(sc, 0xb87c, mac_cfg_value[i]); 2416 rge_write_phy_ocp(sc, 0xb87e, mac_cfg_value[i + 1]); 2417 } 2418 rge_write_phy_ocp(sc, 0xb87c, 0x84f7); 2419 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2420 rge_write_phy_ocp(sc, 0xb87e, val | 0x2800); 2421 RGE_PHY_SETBIT(sc, 0xaec2, 0x1000); 2422 rge_write_phy_ocp(sc, 0xb87c, 0x81b3); 2423 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2424 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00); 2425 rge_write_phy_ocp(sc, 0xb87c, 0x824d); 2426 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2427 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00); 2428 rge_write_phy_ocp(sc, 0xb87c, 0x82e7); 2429 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2430 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00); 2431 val = rge_read_phy_ocp(sc, 0xae4e) & ~0x000f; 2432 rge_write_phy_ocp(sc, 0xae4e, val | 0x0001); 2433 rge_write_phy_ocp(sc, 0xb87c, 0x82ce); 2434 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xf000; 2435 rge_write_phy_ocp(sc, 0xb87e, val | 0x4000); 2436 rge_write_phy_ocp(sc, 0xb87c, 0x84ac); 2437 rge_write_phy_ocp(sc, 0xb87e, 0x0000); 2438 rge_write_phy_ocp(sc, 0xb87c, 0x84ae); 2439 rge_write_phy_ocp(sc, 0xb87e, 0x0000); 2440 rge_write_phy_ocp(sc, 0xb87c, 0x84b0); 2441 rge_write_phy_ocp(sc, 0xb87e, 0xf818); 2442 rge_write_phy_ocp(sc, 0xb87c, 0x84b2); 2443 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2444 rge_write_phy_ocp(sc, 0xb87e, val | 0x6000); 2445 rge_write_phy_ocp(sc, 0xb87c, 0x8ffc); 2446 rge_write_phy_ocp(sc, 0xb87e, 0x6008); 2447 rge_write_phy_ocp(sc, 0xb87c, 0x8ffe); 2448 rge_write_phy_ocp(sc, 0xb87e, 0xf450); 2449 rge_write_phy_ocp(sc, 0xb87c, 0x8015); 2450 RGE_PHY_SETBIT(sc, 0xb87e, 0x0200); 2451 rge_write_phy_ocp(sc, 0xb87c, 0x8016); 2452 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0800); 2453 rge_write_phy_ocp(sc, 0xb87c, 0x8fe6); 2454 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2455 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); 2456 rge_write_phy_ocp(sc, 0xb87c, 0x8fe4); 2457 rge_write_phy_ocp(sc, 0xb87e, 0x2114); 2458 rge_write_phy_ocp(sc, 0xb87c, 0x8647); 2459 rge_write_phy_ocp(sc, 0xb87e, 0xa7B1); 2460 rge_write_phy_ocp(sc, 0xb87c, 0x8649); 2461 rge_write_phy_ocp(sc, 0xb87e, 0xbbca); 2462 rge_write_phy_ocp(sc, 0xb87c, 0x864b); 2463 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2464 rge_write_phy_ocp(sc, 0xb87e, val | 0xdc00); 2465 rge_write_phy_ocp(sc, 0xb87c, 0x8154); 2466 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xc000; 2467 rge_write_phy_ocp(sc, 0xb87e, val | 0x4000); 2468 rge_write_phy_ocp(sc, 0xb87c, 0x8158); 2469 RGE_PHY_CLRBIT(sc, 0xb87e, 0xc000); 2470 rge_write_phy_ocp(sc, 0xb87c, 0x826c); 2471 rge_write_phy_ocp(sc, 0xb87e, 0xffff); 2472 rge_write_phy_ocp(sc, 0xb87c, 0x826e); 2473 rge_write_phy_ocp(sc, 0xb87e, 0xffff); 2474 rge_write_phy_ocp(sc, 0xb87c, 0x8872); 2475 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2476 rge_write_phy_ocp(sc, 0xb87e, val | 0x0e00); 2477 rge_write_phy_ocp(sc, 0xa436, 0x8012); 2478 RGE_PHY_SETBIT(sc, 0xa438, 0x0800); 2479 rge_write_phy_ocp(sc, 0xa436, 0x8012); 2480 RGE_PHY_SETBIT(sc, 0xa438, 0x4000); 2481 RGE_PHY_SETBIT(sc, 0xb576, 0x0001); 2482 rge_write_phy_ocp(sc, 0xa436, 0x834a); 2483 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2484 rge_write_phy_ocp(sc, 0xa438, val | 0x0700); 2485 rge_write_phy_ocp(sc, 0xb87c, 0x8217); 2486 val = rge_read_phy_ocp(sc, 0xb87e) & ~0x3f00; 2487 rge_write_phy_ocp(sc, 0xb87e, val | 0x2a00); 2488 rge_write_phy_ocp(sc, 0xa436, 0x81b1); 2489 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2490 rge_write_phy_ocp(sc, 0xa438, val | 0x0b00); 2491 rge_write_phy_ocp(sc, 0xb87c, 0x8fed); 2492 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2493 rge_write_phy_ocp(sc, 0xb87e, val | 0x4e00); 2494 rge_write_phy_ocp(sc, 0xb87c, 0x88ac); 2495 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2496 rge_write_phy_ocp(sc, 0xb87e, val | 0x2300); 2497 RGE_PHY_SETBIT(sc, 0xbf0c, 0x3800); 2498 rge_write_phy_ocp(sc, 0xb87c, 0x88de); 2499 RGE_PHY_CLRBIT(sc, 0xb87e, 0xFF00); 2500 rge_write_phy_ocp(sc, 0xb87c, 0x80B4); 2501 rge_write_phy_ocp(sc, 0xb87e, 0x5195); 2502 rge_write_phy_ocp(sc, 0xa436, 0x8370); 2503 rge_write_phy_ocp(sc, 0xa438, 0x8671); 2504 rge_write_phy_ocp(sc, 0xa436, 0x8372); 2505 rge_write_phy_ocp(sc, 0xa438, 0x86c8); 2506 rge_write_phy_ocp(sc, 0xa436, 0x8401); 2507 rge_write_phy_ocp(sc, 0xa438, 0x86c8); 2508 rge_write_phy_ocp(sc, 0xa436, 0x8403); 2509 rge_write_phy_ocp(sc, 0xa438, 0x86da); 2510 rge_write_phy_ocp(sc, 0xa436, 0x8406); 2511 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; 2512 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); 2513 rge_write_phy_ocp(sc, 0xa436, 0x8408); 2514 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; 2515 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); 2516 rge_write_phy_ocp(sc, 0xa436, 0x840a); 2517 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; 2518 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); 2519 rge_write_phy_ocp(sc, 0xa436, 0x840c); 2520 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; 2521 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); 2522 rge_write_phy_ocp(sc, 0xa436, 0x840e); 2523 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; 2524 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); 2525 rge_write_phy_ocp(sc, 0xa436, 0x8410); 2526 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; 2527 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); 2528 rge_write_phy_ocp(sc, 0xa436, 0x8412); 2529 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; 2530 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); 2531 rge_write_phy_ocp(sc, 0xa436, 0x8414); 2532 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; 2533 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); 2534 rge_write_phy_ocp(sc, 0xa436, 0x8416); 2535 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; 2536 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); 2537 rge_write_phy_ocp(sc, 0xa436, 0x82bd); 2538 rge_write_phy_ocp(sc, 0xa438, 0x1f40); 2539 val = rge_read_phy_ocp(sc, 0xbfb4) & ~0x07ff; 2540 rge_write_phy_ocp(sc, 0xbfb4, val | 0x0328); 2541 rge_write_phy_ocp(sc, 0xbfb6, 0x3e14); 2542 rge_write_phy_ocp(sc, 0xa436, 0x81c4); 2543 for (i = 0; i < nitems(mac_cfg_a438_value); i++) 2544 rge_write_phy_ocp(sc, 0xa438, mac_cfg_a438_value[i]); 2545 for (i = 0; i < nitems(mac_cfg2_value); i+=2) { 2546 rge_write_phy_ocp(sc, 0xb87c, mac_cfg2_value[i]); 2547 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_value[i + 1]); 2548 } 2549 rge_write_phy_ocp(sc, 0xb87c, 0x88d5); 2550 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2551 rge_write_phy_ocp(sc, 0xb87e, val | 0x0200); 2552 rge_write_phy_ocp(sc, 0xa436, 0x84bb); 2553 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2554 rge_write_phy_ocp(sc, 0xa438, val | 0x0a00); 2555 rge_write_phy_ocp(sc, 0xa436, 0x84c0); 2556 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2557 rge_write_phy_ocp(sc, 0xa438, val | 0x1600); 2558 RGE_PHY_SETBIT(sc, 0xa430, 0x0003); 2559 } 2560 2561 static void 2562 rge_phy_config_mac_r26_1(struct rge_softc *sc) 2563 { 2564 uint16_t val; 2565 int i; 2566 static const uint16_t mac_cfg2_a438_value[] = 2567 { 0x0044, 0x00a8, 0x00d6, 0x00ec, 0x00f6, 0x00fc, 0x00fe, 2568 0x00fe, 0x00bc, 0x0058, 0x002a, 0x003f, 0x3f02, 0x023c, 2569 0x3b0a, 0x1c00, 0x0000, 0x0000, 0x0000, 0x0000 }; 2570 2571 static const uint16_t mac_cfg2_b87e_value[] = 2572 { 0x03ed, 0x03ff, 0x0009, 0x03fe, 0x000b, 0x0021, 0x03f7, 2573 0x03b8, 0x03e0, 0x0049, 0x0049, 0x03e0, 0x03b8, 0x03f7, 2574 0x0021, 0x000b, 0x03fe, 0x0009, 0x03ff, 0x03ed, 0x000e, 2575 0x03fe, 0x03ed, 0x0006, 0x001a, 0x03f1, 0x03d8, 0x0023, 2576 0x0054, 0x0322, 0x00dd, 0x03ab, 0x03dc, 0x0027, 0x000e, 2577 0x03e5, 0x03f9, 0x0012, 0x0001, 0x03f1 }; 2578 2579 rge_phy_config_mcu(sc, RGE_MAC_R26_1_RCODE_VER); 2580 2581 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); 2582 rge_write_phy_ocp(sc, 0xa436, 0x80bf); 2583 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2584 rge_write_phy_ocp(sc, 0xa438, val | 0xed00); 2585 rge_write_phy_ocp(sc, 0xa436, 0x80cd); 2586 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2587 rge_write_phy_ocp(sc, 0xa438, val | 0x1000); 2588 rge_write_phy_ocp(sc, 0xa436, 0x80d1); 2589 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2590 rge_write_phy_ocp(sc, 0xa438, val | 0xc800); 2591 rge_write_phy_ocp(sc, 0xa436, 0x80d4); 2592 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2593 rge_write_phy_ocp(sc, 0xa438, val | 0xc800); 2594 rge_write_phy_ocp(sc, 0xa436, 0x80e1); 2595 rge_write_phy_ocp(sc, 0xa438, 0x10cc); 2596 rge_write_phy_ocp(sc, 0xa436, 0x80e5); 2597 rge_write_phy_ocp(sc, 0xa438, 0x4f0c); 2598 rge_write_phy_ocp(sc, 0xa436, 0x8387); 2599 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2600 rge_write_phy_ocp(sc, 0xa438, val | 0x4700); 2601 val = rge_read_phy_ocp(sc, 0xa80c) & ~0x00c0; 2602 rge_write_phy_ocp(sc, 0xa80c, val | 0x0080); 2603 RGE_PHY_CLRBIT(sc, 0xac90, 0x0010); 2604 RGE_PHY_CLRBIT(sc, 0xad2c, 0x8000); 2605 rge_write_phy_ocp(sc, 0xb87c, 0x8321); 2606 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2607 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); 2608 RGE_PHY_SETBIT(sc, 0xacf8, 0x000c); 2609 rge_write_phy_ocp(sc, 0xa436, 0x8183); 2610 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2611 rge_write_phy_ocp(sc, 0xa438, val | 0x5900); 2612 RGE_PHY_SETBIT(sc, 0xad94, 0x0020); 2613 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); 2614 RGE_PHY_SETBIT(sc, 0xb648, 0x4000); 2615 rge_write_phy_ocp(sc, 0xb87c, 0x839e); 2616 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2617 rge_write_phy_ocp(sc, 0xb87e, val | 0x2f00); 2618 rge_write_phy_ocp(sc, 0xb87c, 0x83f2); 2619 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2620 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); 2621 RGE_PHY_SETBIT(sc, 0xada0, 0x0002); 2622 rge_write_phy_ocp(sc, 0xb87c, 0x80f3); 2623 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2624 rge_write_phy_ocp(sc, 0xb87e, val | 0x9900); 2625 rge_write_phy_ocp(sc, 0xb87c, 0x8126); 2626 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2627 rge_write_phy_ocp(sc, 0xb87e, val | 0xc100); 2628 rge_write_phy_ocp(sc, 0xb87c, 0x893a); 2629 rge_write_phy_ocp(sc, 0xb87e, 0x8080); 2630 rge_write_phy_ocp(sc, 0xb87c, 0x8647); 2631 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2632 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600); 2633 rge_write_phy_ocp(sc, 0xb87c, 0x862c); 2634 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2635 rge_write_phy_ocp(sc, 0xb87e, val | 0x1200); 2636 rge_write_phy_ocp(sc, 0xb87c, 0x864a); 2637 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2638 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600); 2639 rge_write_phy_ocp(sc, 0xb87c, 0x80a0); 2640 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc); 2641 rge_write_phy_ocp(sc, 0xb87c, 0x805e); 2642 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc); 2643 rge_write_phy_ocp(sc, 0xb87c, 0x8056); 2644 rge_write_phy_ocp(sc, 0xb87e, 0x3077); 2645 rge_write_phy_ocp(sc, 0xb87c, 0x8058); 2646 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2647 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00); 2648 rge_write_phy_ocp(sc, 0xb87c, 0x8098); 2649 rge_write_phy_ocp(sc, 0xb87e, 0x3077); 2650 rge_write_phy_ocp(sc, 0xb87c, 0x809a); 2651 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2652 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00); 2653 rge_write_phy_ocp(sc, 0xb87c, 0x8052); 2654 rge_write_phy_ocp(sc, 0xb87e, 0x3733); 2655 rge_write_phy_ocp(sc, 0xb87c, 0x8094); 2656 rge_write_phy_ocp(sc, 0xb87e, 0x3733); 2657 rge_write_phy_ocp(sc, 0xb87c, 0x807f); 2658 rge_write_phy_ocp(sc, 0xb87e, 0x7c75); 2659 rge_write_phy_ocp(sc, 0xb87c, 0x803d); 2660 rge_write_phy_ocp(sc, 0xb87e, 0x7c75); 2661 rge_write_phy_ocp(sc, 0xb87c, 0x8036); 2662 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2663 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000); 2664 rge_write_phy_ocp(sc, 0xb87c, 0x8078); 2665 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2666 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000); 2667 rge_write_phy_ocp(sc, 0xb87c, 0x8031); 2668 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2669 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300); 2670 rge_write_phy_ocp(sc, 0xb87c, 0x8073); 2671 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2672 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300); 2673 val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00; 2674 rge_write_phy_ocp(sc, 0xae06, val | 0x7c00); 2675 rge_write_phy_ocp(sc, 0xb87c, 0x89D1); 2676 rge_write_phy_ocp(sc, 0xb87e, 0x0004); 2677 rge_write_phy_ocp(sc, 0xa436, 0x8fbd); 2678 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2679 rge_write_phy_ocp(sc, 0xa438, val | 0x0a00); 2680 rge_write_phy_ocp(sc, 0xa436, 0x8fbe); 2681 rge_write_phy_ocp(sc, 0xa438, 0x0d09); 2682 rge_write_phy_ocp(sc, 0xb87c, 0x89cd); 2683 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f); 2684 rge_write_phy_ocp(sc, 0xb87c, 0x89cf); 2685 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f); 2686 rge_write_phy_ocp(sc, 0xb87c, 0x83a4); 2687 rge_write_phy_ocp(sc, 0xb87e, 0x6600); 2688 rge_write_phy_ocp(sc, 0xb87c, 0x83a6); 2689 rge_write_phy_ocp(sc, 0xb87e, 0x6601); 2690 rge_write_phy_ocp(sc, 0xb87c, 0x83c0); 2691 rge_write_phy_ocp(sc, 0xb87e, 0x6600); 2692 rge_write_phy_ocp(sc, 0xb87c, 0x83c2); 2693 rge_write_phy_ocp(sc, 0xb87e, 0x6601); 2694 rge_write_phy_ocp(sc, 0xb87c, 0x8414); 2695 rge_write_phy_ocp(sc, 0xb87e, 0x6600); 2696 rge_write_phy_ocp(sc, 0xb87c, 0x8416); 2697 rge_write_phy_ocp(sc, 0xb87e, 0x6601); 2698 rge_write_phy_ocp(sc, 0xb87c, 0x83f8); 2699 rge_write_phy_ocp(sc, 0xb87e, 0x6600); 2700 rge_write_phy_ocp(sc, 0xb87c, 0x83fa); 2701 rge_write_phy_ocp(sc, 0xb87e, 0x6601); 2702 2703 rge_patch_phy_mcu(sc, 1); 2704 val = rge_read_phy_ocp(sc, 0xbd96) & ~0x1f00; 2705 rge_write_phy_ocp(sc, 0xbd96, val | 0x1000); 2706 val = rge_read_phy_ocp(sc, 0xbf1c) & ~0x0007; 2707 rge_write_phy_ocp(sc, 0xbf1c, val | 0x0007); 2708 RGE_PHY_CLRBIT(sc, 0xbfbe, 0x8000); 2709 val = rge_read_phy_ocp(sc, 0xbf40) & ~0x0380; 2710 rge_write_phy_ocp(sc, 0xbf40, val | 0x0280); 2711 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0080; 2712 rge_write_phy_ocp(sc, 0xbf90, val | 0x0060); 2713 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0010; 2714 rge_write_phy_ocp(sc, 0xbf90, val | 0x000c); 2715 rge_patch_phy_mcu(sc, 0); 2716 2717 rge_write_phy_ocp(sc, 0xa436, 0x843b); 2718 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2719 rge_write_phy_ocp(sc, 0xa438, val | 0x2000); 2720 rge_write_phy_ocp(sc, 0xa436, 0x843d); 2721 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2722 rge_write_phy_ocp(sc, 0xa438, val | 0x2000); 2723 RGE_PHY_CLRBIT(sc, 0xb516, 0x007f); 2724 RGE_PHY_CLRBIT(sc, 0xbf80, 0x0030); 2725 2726 rge_write_phy_ocp(sc, 0xa436, 0x8188); 2727 for (i = 0; i < 11; i++) 2728 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]); 2729 2730 rge_write_phy_ocp(sc, 0xb87c, 0x8015); 2731 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2732 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); 2733 rge_write_phy_ocp(sc, 0xb87c, 0x8ffd); 2734 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2735 rge_write_phy_ocp(sc, 0xb87e, val | 0); 2736 rge_write_phy_ocp(sc, 0xb87c, 0x8fff); 2737 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2738 rge_write_phy_ocp(sc, 0xb87e, val | 0x7f00); 2739 rge_write_phy_ocp(sc, 0xb87c, 0x8ffb); 2740 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2741 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2742 rge_write_phy_ocp(sc, 0xb87c, 0x8fe9); 2743 rge_write_phy_ocp(sc, 0xb87e, 0x0002); 2744 rge_write_phy_ocp(sc, 0xb87c, 0x8fef); 2745 rge_write_phy_ocp(sc, 0xb87e, 0x00a5); 2746 rge_write_phy_ocp(sc, 0xb87c, 0x8ff1); 2747 rge_write_phy_ocp(sc, 0xb87e, 0x0106); 2748 rge_write_phy_ocp(sc, 0xb87c, 0x8fe1); 2749 rge_write_phy_ocp(sc, 0xb87e, 0x0102); 2750 rge_write_phy_ocp(sc, 0xb87c, 0x8fe3); 2751 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2752 rge_write_phy_ocp(sc, 0xb87e, val | 0x0400); 2753 RGE_PHY_SETBIT(sc, 0xa654, 0x0800); 2754 RGE_PHY_CLRBIT(sc, 0xa654, 0x0003); 2755 rge_write_phy_ocp(sc, 0xac3a, 0x5851); 2756 val = rge_read_phy_ocp(sc, 0xac3c) & ~0xd000; 2757 rge_write_phy_ocp(sc, 0xac3c, val | 0x2000); 2758 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0200; 2759 rge_write_phy_ocp(sc, 0xac42, val | 0x01c0); 2760 RGE_PHY_CLRBIT(sc, 0xac3e, 0xe000); 2761 RGE_PHY_CLRBIT(sc, 0xac42, 0x0038); 2762 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0002; 2763 rge_write_phy_ocp(sc, 0xac42, val | 0x0005); 2764 rge_write_phy_ocp(sc, 0xac1a, 0x00db); 2765 rge_write_phy_ocp(sc, 0xade4, 0x01b5); 2766 RGE_PHY_CLRBIT(sc, 0xad9c, 0x0c00); 2767 rge_write_phy_ocp(sc, 0xb87c, 0x814b); 2768 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2769 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); 2770 rge_write_phy_ocp(sc, 0xb87c, 0x814d); 2771 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2772 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); 2773 rge_write_phy_ocp(sc, 0xb87c, 0x814f); 2774 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2775 rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00); 2776 rge_write_phy_ocp(sc, 0xb87c, 0x8142); 2777 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2778 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2779 rge_write_phy_ocp(sc, 0xb87c, 0x8144); 2780 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2781 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2782 rge_write_phy_ocp(sc, 0xb87c, 0x8150); 2783 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2784 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2785 rge_write_phy_ocp(sc, 0xb87c, 0x8118); 2786 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2787 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); 2788 rge_write_phy_ocp(sc, 0xb87c, 0x811a); 2789 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2790 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); 2791 rge_write_phy_ocp(sc, 0xb87c, 0x811c); 2792 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2793 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); 2794 rge_write_phy_ocp(sc, 0xb87c, 0x810f); 2795 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2796 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2797 rge_write_phy_ocp(sc, 0xb87c, 0x8111); 2798 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2799 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2800 rge_write_phy_ocp(sc, 0xb87c, 0x811d); 2801 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2802 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2803 RGE_PHY_SETBIT(sc, 0xac36, 0x1000); 2804 RGE_PHY_CLRBIT(sc, 0xad1c, 0x0100); 2805 val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0; 2806 rge_write_phy_ocp(sc, 0xade8, val | 0x1400); 2807 rge_write_phy_ocp(sc, 0xb87c, 0x864b); 2808 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2809 rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00); 2810 2811 rge_write_phy_ocp(sc, 0xa436, 0x8f97); 2812 for (; i < nitems(mac_cfg2_a438_value); i++) 2813 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]); 2814 2815 RGE_PHY_SETBIT(sc, 0xad9c, 0x0020); 2816 rge_write_phy_ocp(sc, 0xb87c, 0x8122); 2817 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2818 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00); 2819 2820 rge_write_phy_ocp(sc, 0xb87c, 0x82c8); 2821 for (i = 0; i < 20; i++) 2822 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]); 2823 2824 rge_write_phy_ocp(sc, 0xb87c, 0x80ef); 2825 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2826 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00); 2827 2828 rge_write_phy_ocp(sc, 0xb87c, 0x82a0); 2829 for (; i < nitems(mac_cfg2_b87e_value); i++) 2830 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]); 2831 2832 rge_write_phy_ocp(sc, 0xa436, 0x8018); 2833 RGE_PHY_SETBIT(sc, 0xa438, 0x2000); 2834 rge_write_phy_ocp(sc, 0xb87c, 0x8fe4); 2835 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2836 rge_write_phy_ocp(sc, 0xb87e, val | 0); 2837 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0; 2838 rge_write_phy_ocp(sc, 0xb54c, val | 0x3700); 2839 } 2840 2841 static void 2842 rge_phy_config_mac_r26_2(struct rge_softc *sc) 2843 { 2844 uint16_t val; 2845 int i; 2846 static const uint16_t mac_cfg3_b87e_value[] = 2847 { 0x03ed, 0x03ff, 0x0009, 0x03fe, 0x000b, 0x0021, 0x03f7, 2848 0x03b8, 0x03e0, 0x0049, 0x0049, 0x03e0, 0x03b8, 0x03f7, 2849 0x0021, 0x000b, 0x03fe, 0x0009, 0x03ff, 0x03ed, 0x82a0, 2850 0x000e, 0x03fe, 0x03ed, 0x0006, 0x001a, 0x03f1, 0x03d8, 2851 0x0023, 0x0054, 0x0322, 0x00dd, 0x03ab, 0x03dc, 0x0027, 2852 0x000e, 0x03e5, 0x03f9, 0x0012, 0x0001, 0x03f1 }; 2853 2854 rge_phy_config_mcu(sc, RGE_MAC_R26_2_RCODE_VER); 2855 2856 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); 2857 rge_write_phy_ocp(sc, 0xa436, 0x8183); 2858 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2859 rge_write_phy_ocp(sc, 0xa438, val | 0x5900); 2860 RGE_PHY_SETBIT(sc, 0xa654, 0x0800); 2861 RGE_PHY_SETBIT(sc, 0xb648, 0x4000); 2862 RGE_PHY_SETBIT(sc, 0xad2c, 0x8000); 2863 RGE_PHY_SETBIT(sc, 0xad94, 0x0020); 2864 RGE_PHY_SETBIT(sc, 0xada0, 0x0002); 2865 val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00; 2866 rge_write_phy_ocp(sc, 0xae06, val | 0x7c00); 2867 rge_write_phy_ocp(sc, 0xb87c, 0x8647); 2868 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2869 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600); 2870 rge_write_phy_ocp(sc, 0xb87c, 0x8036); 2871 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2872 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000); 2873 rge_write_phy_ocp(sc, 0xb87c, 0x8078); 2874 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2875 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000); 2876 rge_write_phy_ocp(sc, 0xb87c, 0x89e9); 2877 RGE_PHY_SETBIT(sc, 0xb87e, 0xff00); 2878 rge_write_phy_ocp(sc, 0xb87c, 0x8ffd); 2879 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2880 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2881 rge_write_phy_ocp(sc, 0xb87c, 0x8ffe); 2882 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2883 rge_write_phy_ocp(sc, 0xb87e, val | 0x0200); 2884 rge_write_phy_ocp(sc, 0xb87c, 0x8fff); 2885 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2886 rge_write_phy_ocp(sc, 0xb87e, val | 0x0400); 2887 rge_write_phy_ocp(sc, 0xa436, 0x8018); 2888 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2889 rge_write_phy_ocp(sc, 0xa438, val | 0x7700); 2890 rge_write_phy_ocp(sc, 0xa436, 0x8f9c); 2891 rge_write_phy_ocp(sc, 0xa438, 0x0005); 2892 rge_write_phy_ocp(sc, 0xa438, 0x0000); 2893 rge_write_phy_ocp(sc, 0xa438, 0x00ed); 2894 rge_write_phy_ocp(sc, 0xa438, 0x0502); 2895 rge_write_phy_ocp(sc, 0xa438, 0x0b00); 2896 rge_write_phy_ocp(sc, 0xa438, 0xd401); 2897 rge_write_phy_ocp(sc, 0xa436, 0x8fa8); 2898 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 2899 rge_write_phy_ocp(sc, 0xa438, val | 0x2900); 2900 rge_write_phy_ocp(sc, 0xb87c, 0x814b); 2901 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2902 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); 2903 rge_write_phy_ocp(sc, 0xb87c, 0x814d); 2904 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2905 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); 2906 rge_write_phy_ocp(sc, 0xb87c, 0x814f); 2907 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2908 rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00); 2909 rge_write_phy_ocp(sc, 0xb87c, 0x8142); 2910 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2911 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2912 rge_write_phy_ocp(sc, 0xb87c, 0x8144); 2913 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2914 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2915 rge_write_phy_ocp(sc, 0xb87c, 0x8150); 2916 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2917 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2918 rge_write_phy_ocp(sc, 0xb87c, 0x8118); 2919 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2920 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); 2921 rge_write_phy_ocp(sc, 0xb87c, 0x811a); 2922 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2923 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); 2924 rge_write_phy_ocp(sc, 0xb87c, 0x811c); 2925 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2926 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); 2927 rge_write_phy_ocp(sc, 0xb87c, 0x810f); 2928 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2929 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2930 rge_write_phy_ocp(sc, 0xb87c, 0x8111); 2931 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2932 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2933 rge_write_phy_ocp(sc, 0xb87c, 0x811d); 2934 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2935 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 2936 RGE_PHY_SETBIT(sc, 0xad1c, 0x0100); 2937 val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0; 2938 rge_write_phy_ocp(sc, 0xade8, val | 0x1400); 2939 rge_write_phy_ocp(sc, 0xb87c, 0x864b); 2940 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2941 rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00); 2942 rge_write_phy_ocp(sc, 0xb87c, 0x862c); 2943 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2944 rge_write_phy_ocp(sc, 0xb87e, val | 0x1200); 2945 rge_write_phy_ocp(sc, 0xa436, 0x8566); 2946 rge_write_phy_ocp(sc, 0xa438, 0x003f); 2947 rge_write_phy_ocp(sc, 0xa438, 0x3f02); 2948 rge_write_phy_ocp(sc, 0xa438, 0x023c); 2949 rge_write_phy_ocp(sc, 0xa438, 0x3b0a); 2950 rge_write_phy_ocp(sc, 0xa438, 0x1c00); 2951 rge_write_phy_ocp(sc, 0xa438, 0x0000); 2952 rge_write_phy_ocp(sc, 0xa438, 0x0000); 2953 rge_write_phy_ocp(sc, 0xa438, 0x0000); 2954 rge_write_phy_ocp(sc, 0xa438, 0x0000); 2955 RGE_PHY_SETBIT(sc, 0xad9c, 0x0020); 2956 rge_write_phy_ocp(sc, 0xb87c, 0x8122); 2957 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2958 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00); 2959 rge_write_phy_ocp(sc, 0xb87c, 0x82c8); 2960 for (i = 0; i < 20; i++) 2961 rge_write_phy_ocp(sc, 0xb87e, mac_cfg3_b87e_value[i]); 2962 rge_write_phy_ocp(sc, 0xb87c, 0x80ef); 2963 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2964 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00); 2965 for (; i < nitems(mac_cfg3_b87e_value); i++) 2966 rge_write_phy_ocp(sc, 0xb87e, mac_cfg3_b87e_value[i]); 2967 RGE_PHY_SETBIT(sc, 0xa430, 0x0003); 2968 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0; 2969 rge_write_phy_ocp(sc, 0xb54c, val | 0x3700); 2970 RGE_PHY_SETBIT(sc, 0xb648, 0x0040); 2971 rge_write_phy_ocp(sc, 0xb87c, 0x8082); 2972 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2973 rge_write_phy_ocp(sc, 0xb87e, val | 0x5d00); 2974 rge_write_phy_ocp(sc, 0xb87c, 0x807c); 2975 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2976 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); 2977 rge_write_phy_ocp(sc, 0xb87c, 0x809d); 2978 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 2979 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); 2980 } 2981 2982 static void 2983 rge_phy_config_mac_r25(struct rge_softc *sc) 2984 { 2985 uint16_t val; 2986 int i; 2987 static const uint16_t mac_cfg3_a438_value[] = 2988 { 0x0043, 0x00a7, 0x00d6, 0x00ec, 0x00f6, 0x00fb, 0x00fd, 0x00ff, 2989 0x00bb, 0x0058, 0x0029, 0x0013, 0x0009, 0x0004, 0x0002 }; 2990 2991 static const uint16_t mac_cfg3_b88e_value[] = 2992 { 0xc091, 0x6e12, 0xc092, 0x1214, 0xc094, 0x1516, 0xc096, 0x171b, 2993 0xc098, 0x1b1c, 0xc09a, 0x1f1f, 0xc09c, 0x2021, 0xc09e, 0x2224, 2994 0xc0a0, 0x2424, 0xc0a2, 0x2424, 0xc0a4, 0x2424, 0xc018, 0x0af2, 2995 0xc01a, 0x0d4a, 0xc01c, 0x0f26, 0xc01e, 0x118d, 0xc020, 0x14f3, 2996 0xc022, 0x175a, 0xc024, 0x19c0, 0xc026, 0x1c26, 0xc089, 0x6050, 2997 0xc08a, 0x5f6e, 0xc08c, 0x6e6e, 0xc08e, 0x6e6e, 0xc090, 0x6e12 }; 2998 2999 rge_phy_config_mcu(sc, RGE_MAC_R25_RCODE_VER); 3000 3001 RGE_PHY_SETBIT(sc, 0xad4e, 0x0010); 3002 val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff; 3003 rge_write_phy_ocp(sc, 0xad16, val | 0x03ff); 3004 val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f; 3005 rge_write_phy_ocp(sc, 0xad32, val | 0x0006); 3006 RGE_PHY_CLRBIT(sc, 0xac08, 0x1000); 3007 RGE_PHY_CLRBIT(sc, 0xac08, 0x0100); 3008 val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003; 3009 rge_write_phy_ocp(sc, 0xacc0, val | 0x0002); 3010 val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0; 3011 rge_write_phy_ocp(sc, 0xad40, val | 0x0040); 3012 val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007; 3013 rge_write_phy_ocp(sc, 0xad40, val | 0x0004); 3014 RGE_PHY_CLRBIT(sc, 0xac14, 0x0080); 3015 RGE_PHY_CLRBIT(sc, 0xac80, 0x0300); 3016 val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007; 3017 rge_write_phy_ocp(sc, 0xac5e, val | 0x0002); 3018 rge_write_phy_ocp(sc, 0xad4c, 0x00a8); 3019 rge_write_phy_ocp(sc, 0xac5c, 0x01ff); 3020 val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0; 3021 rge_write_phy_ocp(sc, 0xac8a, val | 0x0030); 3022 rge_write_phy_ocp(sc, 0xb87c, 0x8157); 3023 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3024 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); 3025 rge_write_phy_ocp(sc, 0xb87c, 0x8159); 3026 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3027 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); 3028 rge_write_phy_ocp(sc, 0xb87c, 0x80a2); 3029 rge_write_phy_ocp(sc, 0xb87e, 0x0153); 3030 rge_write_phy_ocp(sc, 0xb87c, 0x809c); 3031 rge_write_phy_ocp(sc, 0xb87e, 0x0153); 3032 3033 rge_write_phy_ocp(sc, 0xa436, 0x81b3); 3034 for (i = 0; i < nitems(mac_cfg3_a438_value); i++) 3035 rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]); 3036 for (i = 0; i < 26; i++) 3037 rge_write_phy_ocp(sc, 0xa438, 0); 3038 rge_write_phy_ocp(sc, 0xa436, 0x8257); 3039 rge_write_phy_ocp(sc, 0xa438, 0x020f); 3040 rge_write_phy_ocp(sc, 0xa436, 0x80ea); 3041 rge_write_phy_ocp(sc, 0xa438, 0x7843); 3042 3043 rge_patch_phy_mcu(sc, 1); 3044 RGE_PHY_CLRBIT(sc, 0xb896, 0x0001); 3045 RGE_PHY_CLRBIT(sc, 0xb892, 0xff00); 3046 for (i = 0; i < nitems(mac_cfg3_b88e_value); i += 2) { 3047 rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]); 3048 rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]); 3049 } 3050 RGE_PHY_SETBIT(sc, 0xb896, 0x0001); 3051 rge_patch_phy_mcu(sc, 0); 3052 3053 RGE_PHY_SETBIT(sc, 0xd068, 0x2000); 3054 rge_write_phy_ocp(sc, 0xa436, 0x81a2); 3055 RGE_PHY_SETBIT(sc, 0xa438, 0x0100); 3056 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00; 3057 rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00); 3058 RGE_PHY_CLRBIT(sc, 0xa454, 0x0001); 3059 RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020); 3060 RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010); 3061 RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001); 3062 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); 3063 RGE_PHY_SETBIT(sc, 0xa424, 0x0008); 3064 } 3065 3066 static void 3067 rge_phy_config_mac_r25b(struct rge_softc *sc) 3068 { 3069 uint16_t val; 3070 int i; 3071 3072 rge_phy_config_mcu(sc, RGE_MAC_R25B_RCODE_VER); 3073 3074 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); 3075 val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0; 3076 rge_write_phy_ocp(sc, 0xac46, val | 0x0090); 3077 val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003; 3078 rge_write_phy_ocp(sc, 0xad30, val | 0x0001); 3079 rge_write_phy_ocp(sc, 0xb87c, 0x80f5); 3080 rge_write_phy_ocp(sc, 0xb87e, 0x760e); 3081 rge_write_phy_ocp(sc, 0xb87c, 0x8107); 3082 rge_write_phy_ocp(sc, 0xb87e, 0x360e); 3083 rge_write_phy_ocp(sc, 0xb87c, 0x8551); 3084 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3085 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); 3086 val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000; 3087 rge_write_phy_ocp(sc, 0xbf00, val | 0xa000); 3088 val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00; 3089 rge_write_phy_ocp(sc, 0xbf46, val | 0x0300); 3090 for (i = 0; i < 10; i++) { 3091 rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6); 3092 rge_write_phy_ocp(sc, 0xa438, 0x2417); 3093 } 3094 RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040); 3095 val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000; 3096 rge_write_phy_ocp(sc, 0xbf84, val | 0xa000); 3097 rge_write_phy_ocp(sc, 0xa436, 0x8170); 3098 val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700; 3099 rge_write_phy_ocp(sc, 0xa438, val | 0xd800); 3100 RGE_PHY_SETBIT(sc, 0xa424, 0x0008); 3101 } 3102 3103 static void 3104 rge_phy_config_mac_r25d_1(struct rge_softc *sc) 3105 { 3106 uint16_t val; 3107 int i; 3108 3109 rge_phy_config_mcu(sc, RGE_MAC_R25D_1_RCODE_VER); 3110 3111 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); 3112 3113 rge_patch_phy_mcu(sc, 1); 3114 RGE_PHY_SETBIT(sc, 0xbf96, 0x8000); 3115 val = rge_read_phy_ocp(sc, 0xbf94) & ~0x0007; 3116 rge_write_phy_ocp(sc, 0xbf94, val | 0x0005); 3117 val = rge_read_phy_ocp(sc, 0xbf8e) & ~0x3c00; 3118 rge_write_phy_ocp(sc, 0xbf8e, val | 0x2800); 3119 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; 3120 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); 3121 RGE_PHY_SETBIT(sc, 0xbcd8, 0xc000); 3122 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; 3123 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); 3124 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; 3125 rge_write_phy_ocp(sc, 0xbc80, val | 0x0004); 3126 RGE_PHY_SETBIT(sc, 0xbc82, 0xe000); 3127 RGE_PHY_SETBIT(sc, 0xbc82, 0x1c00); 3128 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; 3129 rge_write_phy_ocp(sc, 0xbc80, val | 0x0005); 3130 val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0; 3131 rge_write_phy_ocp(sc, 0xbc82, val | 0x0040); 3132 RGE_PHY_SETBIT(sc, 0xbc82, 0x001c); 3133 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); 3134 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; 3135 rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000); 3136 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); 3137 RGE_PHY_CLRBIT(sc, 0xbd70, 0x0100); 3138 RGE_PHY_SETBIT(sc, 0xa466, 0x0002); 3139 rge_write_phy_ocp(sc, 0xa436, 0x836a); 3140 RGE_PHY_CLRBIT(sc, 0xa438, 0xff00); 3141 rge_patch_phy_mcu(sc, 0); 3142 3143 rge_write_phy_ocp(sc, 0xb87c, 0x832c); 3144 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3145 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); 3146 val = rge_read_phy_ocp(sc, 0xb106) & ~0x0700; 3147 rge_write_phy_ocp(sc, 0xb106, val | 0x0100); 3148 val = rge_read_phy_ocp(sc, 0xb206) & ~0x0700; 3149 rge_write_phy_ocp(sc, 0xb206, val | 0x0200); 3150 val = rge_read_phy_ocp(sc, 0xb306) & ~0x0700; 3151 rge_write_phy_ocp(sc, 0xb306, val | 0x0300); 3152 rge_write_phy_ocp(sc, 0xb87c, 0x80cb); 3153 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3154 rge_write_phy_ocp(sc, 0xb87e, val | 0x0300); 3155 rge_write_phy_ocp(sc, 0xbcf4, 0x0000); 3156 rge_write_phy_ocp(sc, 0xbcf6, 0x0000); 3157 rge_write_phy_ocp(sc, 0xbc12, 0x0000); 3158 rge_write_phy_ocp(sc, 0xb87c, 0x844d); 3159 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3160 rge_write_phy_ocp(sc, 0xb87e, val | 0x0200); 3161 3162 rge_write_phy_ocp(sc, 0xb87c, 0x8feb); 3163 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3164 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); 3165 rge_write_phy_ocp(sc, 0xb87c, 0x8fe9); 3166 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3167 rge_write_phy_ocp(sc, 0xb87e, val | 0x0600); 3168 3169 val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc; 3170 rge_write_phy_ocp(sc, 0xac7e, val | 0x00B4); 3171 rge_write_phy_ocp(sc, 0xb87c, 0x8105); 3172 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3173 rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00); 3174 rge_write_phy_ocp(sc, 0xb87c, 0x8117); 3175 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3176 rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00); 3177 rge_write_phy_ocp(sc, 0xb87c, 0x8103); 3178 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3179 rge_write_phy_ocp(sc, 0xb87e, val | 0x7400); 3180 rge_write_phy_ocp(sc, 0xb87c, 0x8115); 3181 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3182 rge_write_phy_ocp(sc, 0xb87e, val | 0x3400); 3183 RGE_PHY_CLRBIT(sc, 0xad40, 0x0030); 3184 val = rge_read_phy_ocp(sc, 0xad66) & ~0x000f; 3185 rge_write_phy_ocp(sc, 0xad66, val | 0x0007); 3186 val = rge_read_phy_ocp(sc, 0xad68) & ~0xf000; 3187 rge_write_phy_ocp(sc, 0xad68, val | 0x8000); 3188 val = rge_read_phy_ocp(sc, 0xad68) & ~0x0f00; 3189 rge_write_phy_ocp(sc, 0xad68, val | 0x0500); 3190 val = rge_read_phy_ocp(sc, 0xad68) & ~0x000f; 3191 rge_write_phy_ocp(sc, 0xad68, val | 0x0002); 3192 val = rge_read_phy_ocp(sc, 0xad6a) & ~0xf000; 3193 rge_write_phy_ocp(sc, 0xad6a, val | 0x7000); 3194 rge_write_phy_ocp(sc, 0xac50, 0x01e8); 3195 rge_write_phy_ocp(sc, 0xa436, 0x81fa); 3196 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3197 rge_write_phy_ocp(sc, 0xa438, val | 0x5400); 3198 val = rge_read_phy_ocp(sc, 0xa864) & ~0x00f0; 3199 rge_write_phy_ocp(sc, 0xa864, val | 0x00c0); 3200 val = rge_read_phy_ocp(sc, 0xa42c) & ~0x00ff; 3201 rge_write_phy_ocp(sc, 0xa42c, val | 0x0002); 3202 rge_write_phy_ocp(sc, 0xa436, 0x80e1); 3203 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3204 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00); 3205 rge_write_phy_ocp(sc, 0xa436, 0x80de); 3206 val = rge_read_phy_ocp(sc, 0xa438) & ~0xf000; 3207 rge_write_phy_ocp(sc, 0xa438, val | 0x0700); 3208 RGE_PHY_SETBIT(sc, 0xa846, 0x0080); 3209 rge_write_phy_ocp(sc, 0xa436, 0x80ba); 3210 rge_write_phy_ocp(sc, 0xa438, 0x8a04); 3211 rge_write_phy_ocp(sc, 0xa436, 0x80bd); 3212 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3213 rge_write_phy_ocp(sc, 0xa438, val | 0xca00); 3214 rge_write_phy_ocp(sc, 0xa436, 0x80b7); 3215 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3216 rge_write_phy_ocp(sc, 0xa438, val | 0xb300); 3217 rge_write_phy_ocp(sc, 0xa436, 0x80ce); 3218 rge_write_phy_ocp(sc, 0xa438, 0x8a04); 3219 rge_write_phy_ocp(sc, 0xa436, 0x80d1); 3220 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3221 rge_write_phy_ocp(sc, 0xa438, val | 0xca00); 3222 rge_write_phy_ocp(sc, 0xa436, 0x80cb); 3223 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3224 rge_write_phy_ocp(sc, 0xa438, val | 0xbb00); 3225 rge_write_phy_ocp(sc, 0xa436, 0x80a6); 3226 rge_write_phy_ocp(sc, 0xa438, 0x4909); 3227 rge_write_phy_ocp(sc, 0xa436, 0x80a8); 3228 rge_write_phy_ocp(sc, 0xa438, 0x05b8); 3229 rge_write_phy_ocp(sc, 0xa436, 0x8200); 3230 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3231 rge_write_phy_ocp(sc, 0xa438, val | 0x5800); 3232 rge_write_phy_ocp(sc, 0xa436, 0x8ff1); 3233 rge_write_phy_ocp(sc, 0xa438, 0x7078); 3234 rge_write_phy_ocp(sc, 0xa436, 0x8ff3); 3235 rge_write_phy_ocp(sc, 0xa438, 0x5d78); 3236 rge_write_phy_ocp(sc, 0xa436, 0x8ff5); 3237 rge_write_phy_ocp(sc, 0xa438, 0x7862); 3238 rge_write_phy_ocp(sc, 0xa436, 0x8ff7); 3239 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3240 rge_write_phy_ocp(sc, 0xa438, val | 0x1400); 3241 3242 rge_write_phy_ocp(sc, 0xa436, 0x814c); 3243 rge_write_phy_ocp(sc, 0xa438, 0x8455); 3244 rge_write_phy_ocp(sc, 0xa436, 0x814e); 3245 rge_write_phy_ocp(sc, 0xa438, 0x84a6); 3246 rge_write_phy_ocp(sc, 0xa436, 0x8163); 3247 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3248 rge_write_phy_ocp(sc, 0xa438, val | 0x0600); 3249 rge_write_phy_ocp(sc, 0xa436, 0x816a); 3250 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3251 rge_write_phy_ocp(sc, 0xa438, val | 0x0500); 3252 rge_write_phy_ocp(sc, 0xa436, 0x8171); 3253 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3254 rge_write_phy_ocp(sc, 0xa438, val | 0x1f00); 3255 3256 val = rge_read_phy_ocp(sc, 0xbc3a) & ~0x000f; 3257 rge_write_phy_ocp(sc, 0xbc3a, val | 0x0006); 3258 for (i = 0; i < 10; i++) { 3259 rge_write_phy_ocp(sc, 0xa436, 0x8064 + i * 3); 3260 RGE_PHY_CLRBIT(sc, 0xa438, 0x0700); 3261 } 3262 val = rge_read_phy_ocp(sc, 0xbfa0) & ~0xff70; 3263 rge_write_phy_ocp(sc, 0xbfa0, val | 0x5500); 3264 rge_write_phy_ocp(sc, 0xbfa2, 0x9d00); 3265 rge_write_phy_ocp(sc, 0xa436, 0x8165); 3266 val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700; 3267 rge_write_phy_ocp(sc, 0xa438, val | 0x0200); 3268 3269 rge_write_phy_ocp(sc, 0xa436, 0x8019); 3270 RGE_PHY_SETBIT(sc, 0xa438, 0x0100); 3271 rge_write_phy_ocp(sc, 0xa436, 0x8fe3); 3272 rge_write_phy_ocp(sc, 0xa438, 0x0005); 3273 rge_write_phy_ocp(sc, 0xa438, 0x0000); 3274 rge_write_phy_ocp(sc, 0xa438, 0x00ed); 3275 rge_write_phy_ocp(sc, 0xa438, 0x0502); 3276 rge_write_phy_ocp(sc, 0xa438, 0x0b00); 3277 rge_write_phy_ocp(sc, 0xa438, 0xd401); 3278 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3279 rge_write_phy_ocp(sc, 0xa438, val | 0x2900); 3280 3281 rge_write_phy_ocp(sc, 0xa436, 0x8018); 3282 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3283 rge_write_phy_ocp(sc, 0xa438, val | 0x1700); 3284 3285 rge_write_phy_ocp(sc, 0xa436, 0x815b); 3286 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; 3287 rge_write_phy_ocp(sc, 0xa438, val | 0x1700); 3288 3289 RGE_PHY_CLRBIT(sc, 0xa4e0, 0x8000); 3290 RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020); 3291 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); 3292 RGE_PHY_SETBIT(sc, 0xa430, 0x1001); 3293 RGE_PHY_SETBIT(sc, 0xa442, 0x0080); 3294 } 3295 3296 static void 3297 rge_phy_config_mac_r25d_2(struct rge_softc *sc) 3298 { 3299 uint16_t val; 3300 3301 rge_phy_config_mcu(sc, RGE_MAC_R25D_2_RCODE_VER); 3302 3303 RGE_PHY_SETBIT(sc, 0xa442, 0x0800); 3304 3305 rge_patch_phy_mcu(sc, 1); 3306 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; 3307 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); 3308 RGE_PHY_SETBIT(sc, 0xbcd8, 0xc000); 3309 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; 3310 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); 3311 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; 3312 rge_write_phy_ocp(sc, 0xbc80, val | 0x0004); 3313 RGE_PHY_SETBIT(sc, 0xbc82, 0xe000); 3314 RGE_PHY_SETBIT(sc, 0xbc82, 0x1c00); 3315 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; 3316 rge_write_phy_ocp(sc, 0xbc80, val | 0x0005); 3317 val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0; 3318 rge_write_phy_ocp(sc, 0xbc82, val | 0x0040); 3319 RGE_PHY_SETBIT(sc, 0xbc82, 0x001c); 3320 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); 3321 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; 3322 rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000); 3323 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); 3324 rge_patch_phy_mcu(sc, 0); 3325 3326 val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc; 3327 rge_write_phy_ocp(sc, 0xac7e, val | 0x00b4); 3328 rge_write_phy_ocp(sc, 0xb87c, 0x8105); 3329 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3330 rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00); 3331 rge_write_phy_ocp(sc, 0xb87c, 0x8117); 3332 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3333 rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00); 3334 rge_write_phy_ocp(sc, 0xb87c, 0x8103); 3335 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3336 rge_write_phy_ocp(sc, 0xb87e, val | 0x7400); 3337 rge_write_phy_ocp(sc, 0xb87c, 0x8115); 3338 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3339 rge_write_phy_ocp(sc, 0xb87e, val | 0x3400); 3340 rge_write_phy_ocp(sc, 0xb87c, 0x8feb); 3341 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3342 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); 3343 rge_write_phy_ocp(sc, 0xb87c, 0x8fea); 3344 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3345 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); 3346 rge_write_phy_ocp(sc, 0xb87c, 0x80d6); 3347 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; 3348 rge_write_phy_ocp(sc, 0xb87e, val | 0xef00); 3349 RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020); 3350 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); 3351 RGE_PHY_CLRBIT(sc, 0xa448, 0x0400); 3352 RGE_PHY_CLRBIT(sc, 0xa586, 0x0400); 3353 RGE_PHY_SETBIT(sc, 0xa430, 0x1001); 3354 RGE_PHY_SETBIT(sc, 0xa442, 0x0080); 3355 } 3356 3357 static void 3358 rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever) 3359 { 3360 if (sc->rge_rcodever != rcodever) { 3361 int i; 3362 3363 rge_patch_phy_mcu(sc, 1); 3364 3365 if (sc->rge_type == MAC_R25) { 3366 rge_write_phy_ocp(sc, 0xa436, 0x8024); 3367 rge_write_phy_ocp(sc, 0xa438, 0x8601); 3368 rge_write_phy_ocp(sc, 0xa436, 0xb82e); 3369 rge_write_phy_ocp(sc, 0xa438, 0x0001); 3370 3371 RGE_PHY_SETBIT(sc, 0xb820, 0x0080); 3372 3373 for (i = 0; i < nitems(mac_r25_mcu); i++) 3374 rge_write_phy_ocp(sc, 3375 mac_r25_mcu[i].reg, mac_r25_mcu[i].val); 3376 3377 RGE_PHY_CLRBIT(sc, 0xb820, 0x0080); 3378 3379 rge_write_phy_ocp(sc, 0xa436, 0); 3380 rge_write_phy_ocp(sc, 0xa438, 0); 3381 RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001); 3382 rge_write_phy_ocp(sc, 0xa436, 0x8024); 3383 rge_write_phy_ocp(sc, 0xa438, 0); 3384 } else if (sc->rge_type == MAC_R25B) { 3385 for (i = 0; i < nitems(mac_r25b_mcu); i++) 3386 rge_write_phy_ocp(sc, 3387 mac_r25b_mcu[i].reg, mac_r25b_mcu[i].val); 3388 } else if (sc->rge_type == MAC_R25D_1) { 3389 for (i = 0; i < 2403; i++) 3390 rge_write_phy_ocp(sc, 3391 mac_r25d_1_mcu[i].reg, 3392 mac_r25d_1_mcu[i].val); 3393 rge_patch_phy_mcu(sc, 0); 3394 3395 rge_patch_phy_mcu(sc, 1); 3396 for (; i < 2528; i++) 3397 rge_write_phy_ocp(sc, 3398 mac_r25d_1_mcu[i].reg, 3399 mac_r25d_1_mcu[i].val); 3400 rge_patch_phy_mcu(sc, 0); 3401 3402 rge_patch_phy_mcu(sc, 1); 3403 for (; i < nitems(mac_r25d_1_mcu); i++) 3404 rge_write_phy_ocp(sc, 3405 mac_r25d_1_mcu[i].reg, 3406 mac_r25d_1_mcu[i].val); 3407 } else if (sc->rge_type == MAC_R25D_2) { 3408 for (i = 0; i < 1269; i++) 3409 rge_write_phy_ocp(sc, 3410 mac_r25d_2_mcu[i].reg, 3411 mac_r25d_2_mcu[i].val); 3412 rge_patch_phy_mcu(sc, 0); 3413 3414 rge_patch_phy_mcu(sc, 1); 3415 for (; i < nitems(mac_r25d_2_mcu); i++) 3416 rge_write_phy_ocp(sc, 3417 mac_r25d_2_mcu[i].reg, 3418 mac_r25d_2_mcu[i].val); 3419 } else if (sc->rge_type == MAC_R26_1) { 3420 for (i = 0; i < 6989; i++) 3421 rge_write_phy_ocp(sc, 3422 mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val); 3423 rge_patch_phy_mcu(sc, 0); 3424 3425 rge_patch_phy_mcu(sc, 1); 3426 for (; i < nitems(mac_r26_1_mcu); i++) 3427 rge_write_phy_ocp(sc, 3428 mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val); 3429 } else if (sc->rge_type == MAC_R26_2) { 3430 for (i = 0; i < nitems(mac_r26_2_mcu); i++) 3431 rge_write_phy_ocp(sc, 3432 mac_r26_2_mcu[i].reg, mac_r26_2_mcu[i].val); 3433 } else if (sc->rge_type == MAC_R27) { 3434 for (i = 0; i < 1887; i++) 3435 rge_write_phy_ocp(sc, 3436 mac_r27_mcu[i].reg, mac_r27_mcu[i].val); 3437 rge_patch_phy_mcu(sc, 0); 3438 3439 rge_patch_phy_mcu(sc, 1); 3440 for (; i < nitems(mac_r27_mcu); i++) 3441 rge_write_phy_ocp(sc, 3442 mac_r27_mcu[i].reg, mac_r27_mcu[i].val); 3443 } 3444 3445 rge_patch_phy_mcu(sc, 0); 3446 3447 /* Write ram code version. */ 3448 rge_write_phy_ocp(sc, 0xa436, 0x801e); 3449 rge_write_phy_ocp(sc, 0xa438, rcodever); 3450 } 3451 } 3452 3453 static void 3454 rge_set_macaddr(struct rge_softc *sc, const uint8_t *addr) 3455 { 3456 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); 3457 RGE_WRITE_4(sc, RGE_MAC0, 3458 (uint32_t)addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); 3459 RGE_WRITE_4(sc, RGE_MAC4, 3460 addr[5] << 8 | addr[4]); 3461 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); 3462 } 3463 3464 static void 3465 rge_get_macaddr(struct rge_softc *sc, uint8_t *addr) 3466 { 3467 int i; 3468 3469 for (i = 0; i < ETHER_ADDR_LEN; i++) 3470 addr[i] = RGE_READ_1(sc, RGE_ADDR0 + i); 3471 } 3472 3473 static void 3474 rge_hw_init(struct rge_softc *sc) 3475 { 3476 uint16_t reg; 3477 3478 rge_disable_aspm_clkreq(sc); 3479 RGE_CLRBIT_1(sc, 0xf1, 0x80); 3480 3481 /* Disable UPS. */ 3482 RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010); 3483 3484 /* Disable MAC MCU. */ 3485 rge_disable_aspm_clkreq(sc); 3486 rge_write_mac_ocp(sc, 0xfc48, 0); 3487 for (reg = 0xfc28; reg < 0xfc48; reg += 2) 3488 rge_write_mac_ocp(sc, reg, 0); 3489 DELAY(3000); 3490 rge_write_mac_ocp(sc, 0xfc26, 0); 3491 3492 if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) 3493 rge_mac_config_ext_mcu(sc, sc->rge_type); 3494 else 3495 rge_mac_config_mcu(sc, sc->rge_type); 3496 3497 /* Disable PHY power saving. */ 3498 if (sc->rge_type == MAC_R25) 3499 rge_disable_phy_ocp_pwrsave(sc); 3500 3501 /* Set PCIe uncorrectable error status. */ 3502 rge_write_csi(sc, 0x108, 3503 rge_read_csi(sc, 0x108) | 0x00100000); 3504 } 3505 3506 void 3507 rge_hw_reset(struct rge_softc *sc) 3508 { 3509 /* Disable interrupts */ 3510 RGE_WRITE_4(sc, RGE_IMR, 0); 3511 RGE_WRITE_4(sc, RGE_ISR, RGE_READ_4(sc, RGE_ISR)); 3512 3513 /* Clear timer interrupts. */ 3514 RGE_WRITE_4(sc, RGE_TIMERINT0, 0); 3515 RGE_WRITE_4(sc, RGE_TIMERINT1, 0); 3516 RGE_WRITE_4(sc, RGE_TIMERINT2, 0); 3517 RGE_WRITE_4(sc, RGE_TIMERINT3, 0); 3518 3519 rge_reset(sc); 3520 } 3521 3522 static void 3523 rge_disable_phy_ocp_pwrsave(struct rge_softc *sc) 3524 { 3525 if (rge_read_phy_ocp(sc, 0xc416) != 0x0500) { 3526 rge_patch_phy_mcu(sc, 1); 3527 rge_write_phy_ocp(sc, 0xc416, 0); 3528 rge_write_phy_ocp(sc, 0xc416, 0x0500); 3529 rge_patch_phy_mcu(sc, 0); 3530 } 3531 } 3532 3533 static void 3534 rge_patch_phy_mcu(struct rge_softc *sc, int set) 3535 { 3536 int i; 3537 3538 if (set) 3539 RGE_PHY_SETBIT(sc, 0xb820, 0x0010); 3540 else 3541 RGE_PHY_CLRBIT(sc, 0xb820, 0x0010); 3542 3543 for (i = 0; i < 1000; i++) { 3544 if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) == 0x0040) 3545 break; 3546 DELAY(100); 3547 } 3548 if (i == 1000) { 3549 DPRINTF(("timeout waiting to patch phy mcu\n")); 3550 return; 3551 } 3552 } 3553 3554 static void 3555 rge_add_media_types(struct rge_softc *sc) 3556 { 3557 if (sc->rge_sfpmode) { 3558 /* No distinction between SX/SR and LX/LR */ 3559 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_LX, 0, NULL); 3560 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_LR, 0, NULL); 3561 return; 3562 } 3563 3564 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL); 3565 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 3566 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL); 3567 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 3568 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T, 0, NULL); 3569 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3570 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T, 0, NULL); 3571 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL); 3572 3573 if (RGE_TYPE_R26(sc)) { 3574 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T, 0, NULL); 3575 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T | IFM_FDX, 3576 0, NULL); 3577 } else if (sc->rge_type == MAC_R27) { 3578 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_T, 0, NULL); 3579 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_T | IFM_FDX, 3580 0, NULL); 3581 } 3582 } 3583 3584 static void 3585 rge_config_imtype(struct rge_softc *sc, int imtype) 3586 { 3587 switch (imtype) { 3588 case RGE_IMTYPE_NONE: 3589 sc->rge_intrs = RGE_INTRS; 3590 sc->rge_rx_ack = RGE_ISR_RX_OK | RGE_ISR_RX_DESC_UNAVAIL | 3591 RGE_ISR_RX_FIFO_OFLOW; 3592 sc->rge_tx_ack = RGE_ISR_TX_OK; 3593 break; 3594 case RGE_IMTYPE_SIM: 3595 sc->rge_intrs = RGE_INTRS_TIMER; 3596 sc->rge_rx_ack = RGE_ISR_PCS_TIMEOUT; 3597 sc->rge_tx_ack = RGE_ISR_PCS_TIMEOUT; 3598 break; 3599 default: 3600 panic("%s: unknown imtype %d", device_xname(sc->sc_dev), imtype); 3601 } 3602 } 3603 3604 static void 3605 rge_disable_aspm_clkreq(struct rge_softc *sc) 3606 { 3607 int unlock = 1; 3608 3609 if ((RGE_READ_1(sc, RGE_EECMD) & RGE_EECMD_WRITECFG) == 3610 RGE_EECMD_WRITECFG) 3611 unlock = 0; 3612 3613 if (unlock) 3614 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); 3615 3616 if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27) 3617 RGE_CLRBIT_1(sc, RGE_INT_CFG0, 0x08); 3618 else 3619 RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN); 3620 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS); 3621 3622 if (unlock) 3623 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); 3624 } 3625 3626 static void 3627 rge_disable_hw_im(struct rge_softc *sc) 3628 { 3629 RGE_WRITE_2(sc, RGE_IM, 0); 3630 } 3631 3632 static void 3633 rge_disable_sim_im(struct rge_softc *sc) 3634 { 3635 RGE_WRITE_4(sc, RGE_TIMERINT0, 0); 3636 sc->rge_timerintr = 0; 3637 } 3638 3639 static void 3640 rge_setup_sim_im(struct rge_softc *sc) 3641 { 3642 RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600); 3643 RGE_WRITE_4(sc, RGE_TIMERCNT, 1); 3644 sc->rge_timerintr = 1; 3645 } 3646 3647 static void 3648 rge_setup_intr(struct rge_softc *sc, int imtype) 3649 { 3650 rge_config_imtype(sc, imtype); 3651 3652 /* Enable interrupts. */ 3653 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs); 3654 3655 switch (imtype) { 3656 case RGE_IMTYPE_NONE: 3657 rge_disable_sim_im(sc); 3658 rge_disable_hw_im(sc); 3659 break; 3660 case RGE_IMTYPE_SIM: 3661 rge_disable_hw_im(sc); 3662 rge_setup_sim_im(sc); 3663 break; 3664 default: 3665 panic("%s: unknown imtype %d", device_xname(sc->sc_dev), imtype); 3666 } 3667 } 3668 3669 static void 3670 rge_switch_mcu_ram_page(struct rge_softc *sc, int page) 3671 { 3672 uint16_t val; 3673 3674 val = rge_read_mac_ocp(sc, 0xe446) & ~0x0003; 3675 val |= page; 3676 rge_write_mac_ocp(sc, 0xe446, val); 3677 } 3678 3679 static int 3680 rge_exit_oob(struct rge_softc *sc) 3681 { 3682 int error, i; 3683 3684 /* Disable RealWoW. */ 3685 rge_write_mac_ocp(sc, 0xc0bc, 0x00ff); 3686 3687 if ((error = rge_reset(sc)) != 0) 3688 return error; 3689 3690 /* Disable OOB. */ 3691 RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB); 3692 3693 RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000); 3694 3695 for (i = 0; i < 10; i++) { 3696 DELAY(100); 3697 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200) 3698 break; 3699 } 3700 3701 rge_write_mac_ocp(sc, 0xc0aa, 0x07d0); 3702 rge_write_mac_ocp(sc, 0xc0a6, 0x01b5); 3703 rge_write_mac_ocp(sc, 0xc01e, 0x5555); 3704 3705 for (i = 0; i < 10; i++) { 3706 DELAY(100); 3707 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200) 3708 break; 3709 } 3710 3711 if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) { 3712 for (i = 0; i < RGE_TIMEOUT; i++) { 3713 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2) 3714 break; 3715 DELAY(1000); 3716 } 3717 RGE_MAC_CLRBIT(sc, 0xd42c, 0x0100); 3718 if (sc->rge_type != MAC_R25) 3719 RGE_PHY_CLRBIT(sc, 0xa466, 0x0001); 3720 RGE_PHY_CLRBIT(sc, 0xa468, 0x000a); 3721 } 3722 3723 return 0; 3724 } 3725 3726 static void 3727 rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val) 3728 { 3729 int i; 3730 3731 RGE_WRITE_4(sc, RGE_CSIDR, val); 3732 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) | 3733 (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT) | RGE_CSIAR_BUSY); 3734 3735 for (i = 0; i < 10; i++) { 3736 DELAY(100); 3737 if (!(RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY)) 3738 break; 3739 } 3740 3741 DELAY(20); 3742 } 3743 3744 static uint32_t 3745 rge_read_csi(struct rge_softc *sc, uint32_t reg) 3746 { 3747 int i; 3748 3749 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) | 3750 (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT)); 3751 3752 for (i = 0; i < 10; i++) { 3753 DELAY(100); 3754 if (RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY) 3755 break; 3756 } 3757 3758 DELAY(20); 3759 3760 return (RGE_READ_4(sc, RGE_CSIDR)); 3761 } 3762 3763 static void 3764 rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) 3765 { 3766 uint32_t tmp; 3767 3768 tmp = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT; 3769 tmp += val; 3770 tmp |= RGE_MACOCP_BUSY; 3771 RGE_WRITE_4(sc, RGE_MACOCP, tmp); 3772 } 3773 3774 static uint16_t 3775 rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg) 3776 { 3777 uint32_t val; 3778 3779 val = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT; 3780 RGE_WRITE_4(sc, RGE_MACOCP, val); 3781 3782 return (RGE_READ_4(sc, RGE_MACOCP) & RGE_MACOCP_DATA_MASK); 3783 } 3784 3785 static void 3786 rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val) 3787 { 3788 uint32_t tmp; 3789 int i; 3790 3791 tmp = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT; 3792 tmp |= RGE_EPHYAR_BUSY | (val & RGE_EPHYAR_DATA_MASK); 3793 RGE_WRITE_4(sc, RGE_EPHYAR, tmp); 3794 3795 for (i = 0; i < 10; i++) { 3796 DELAY(100); 3797 if (!(RGE_READ_4(sc, RGE_EPHYAR) & RGE_EPHYAR_BUSY)) 3798 break; 3799 } 3800 3801 DELAY(20); 3802 } 3803 3804 static uint16_t 3805 rge_read_ephy(struct rge_softc *sc, uint16_t reg) 3806 { 3807 uint32_t val; 3808 int i; 3809 3810 val = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT; 3811 RGE_WRITE_4(sc, RGE_EPHYAR, val); 3812 3813 for (i = 0; i < 10; i++) { 3814 DELAY(100); 3815 val = RGE_READ_4(sc, RGE_EPHYAR); 3816 if (val & RGE_EPHYAR_BUSY) 3817 break; 3818 } 3819 3820 DELAY(20); 3821 3822 return (val & RGE_EPHYAR_DATA_MASK); 3823 } 3824 3825 static int 3826 rge_wait_sds(struct rge_softc *sc) 3827 { 3828 uint16_t tmp; 3829 int i; 3830 3831 for (i = 0; i < 100; i++) { 3832 tmp = RGE_READ_2(sc, RGE_SDS_CMD); 3833 if (tmp & RGE_SDS_CMD_IN) 3834 return 1; 3835 DELAY(1); 3836 } 3837 3838 return 0; 3839 } 3840 3841 static uint16_t 3842 rge_read_sds(struct rge_softc *sc, uint16_t reg) 3843 { 3844 uint16_t val = 0xffff; 3845 3846 RGE_WRITE_2(sc, RGE_SDS_ADDR, reg); 3847 RGE_WRITE_2(sc, RGE_SDS_CMD, RGE_SDS_CMD_IN); 3848 3849 if (rge_wait_sds(sc)) 3850 val = RGE_READ_2(sc, RGE_SDS_DATA_OUT); 3851 3852 return val; 3853 } 3854 3855 static void 3856 rge_write_sds(struct rge_softc *sc, uint16_t reg, uint16_t val) 3857 { 3858 RGE_WRITE_2(sc, RGE_SDS_DATA_IN, val); 3859 RGE_WRITE_2(sc, RGE_SDS_ADDR, reg); 3860 RGE_WRITE_2(sc, RGE_SDS_CMD, RGE_SDS_CMD_IN | RGE_SDS_WE_IN); 3861 3862 rge_wait_sds(sc); 3863 } 3864 3865 static void 3866 rge_reset_sds(struct rge_softc *sc) 3867 { 3868 uint8_t b; 3869 3870 b = RGE_READ_1(sc, 0x2350); 3871 b &= ~0x01; 3872 RGE_WRITE_1(sc, 0x2350, b); 3873 DELAY(1); 3874 3875 RGE_WRITE_2(sc, 0x233a, 0x801f); 3876 b = RGE_READ_1(sc, 0x2350); 3877 b |= 0x01; 3878 RGE_WRITE_1(sc, 0x2350, b); 3879 DELAY(10); 3880 } 3881 3882 static uint16_t 3883 rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg) 3884 { 3885 uint16_t val; 3886 3887 val = (reg >> 12); 3888 rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, val); 3889 3890 return reg & 0x0fff; 3891 } 3892 3893 static void 3894 rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val) 3895 { 3896 rge_write_ephy(sc, rge_check_ephy_ext_add(sc, reg), val); 3897 } 3898 3899 static void 3900 rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val) 3901 { 3902 uint16_t off, phyaddr; 3903 3904 phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8); 3905 phyaddr <<= 4; 3906 3907 off = addr ? reg : 0x10 + (reg % 8); 3908 3909 phyaddr += (off - 16) << 1; 3910 3911 rge_write_phy_ocp(sc, phyaddr, val); 3912 } 3913 3914 static uint16_t 3915 rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg) 3916 { 3917 uint16_t off, phyaddr; 3918 3919 phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8); 3920 phyaddr <<= 4; 3921 3922 off = addr ? reg : 0x10 + (reg % 8); 3923 3924 phyaddr += (off - 16) << 1; 3925 3926 return (rge_read_phy_ocp(sc, phyaddr)); 3927 } 3928 3929 static void 3930 rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) 3931 { 3932 uint32_t tmp; 3933 int i; 3934 3935 tmp = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT; 3936 tmp |= RGE_PHYOCP_BUSY | val; 3937 RGE_WRITE_4(sc, RGE_PHYOCP, tmp); 3938 3939 for (i = 0; i < RGE_TIMEOUT; i++) { 3940 DELAY(1); 3941 if (!(RGE_READ_4(sc, RGE_PHYOCP) & RGE_PHYOCP_BUSY)) 3942 break; 3943 } 3944 } 3945 3946 static uint16_t 3947 rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg) 3948 { 3949 uint32_t val; 3950 int i; 3951 3952 val = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT; 3953 RGE_WRITE_4(sc, RGE_PHYOCP, val); 3954 3955 for (i = 0; i < RGE_TIMEOUT; i++) { 3956 DELAY(1); 3957 val = RGE_READ_4(sc, RGE_PHYOCP); 3958 if (val & RGE_PHYOCP_BUSY) 3959 break; 3960 } 3961 3962 return (val & RGE_PHYOCP_DATA_MASK); 3963 } 3964 3965 static int 3966 rge_get_link_status(struct rge_softc *sc) 3967 { 3968 return ((RGE_READ_2(sc, RGE_PHYSTAT) & RGE_PHYSTAT_LINK) ? 1 : 0); 3969 } 3970 3971 static void 3972 rge_txstart(void *arg) 3973 { 3974 struct rge_softc *sc = arg; 3975 3976 RGE_WRITE_2(sc, RGE_TXSTART, RGE_TXSTART_START); 3977 } 3978 3979 static void 3980 rge_tick(void *arg) 3981 { 3982 struct rge_softc *sc = arg; 3983 3984 RGE_LOCK(sc); 3985 rge_link_state(sc); 3986 RGE_UNLOCK(sc); 3987 3988 callout_schedule(&sc->sc_timeout, hz); 3989 } 3990 3991 static void 3992 rge_link_state(struct rge_softc *sc) 3993 { 3994 struct ifnet *ifp = &sc->sc_ec.ec_if; 3995 int link = LINK_STATE_DOWN; 3996 3997 if (rge_get_link_status(sc)) 3998 link = LINK_STATE_UP; 3999 4000 if (ifp->if_link_state != link) { /* XXX not safe to access */ 4001 if_link_state_change(ifp, link); 4002 } 4003 } 4004 4005 /* Module interface */ 4006 4007 MODULE(MODULE_CLASS_DRIVER, if_rge, "pci"); 4008 4009 #ifdef _MODULE 4010 #include "ioconf.c" 4011 #endif 4012 4013 static int 4014 if_rge_modcmd(modcmd_t cmd, void *opaque) 4015 { 4016 int error = 0; 4017 4018 switch (cmd) { 4019 case MODULE_CMD_INIT: 4020 #ifdef _MODULE 4021 error = config_init_component(cfdriver_ioconf_rge, 4022 cfattach_ioconf_rge, cfdata_ioconf_rge); 4023 #endif 4024 return error; 4025 case MODULE_CMD_FINI: 4026 #ifdef _MODULE 4027 error = config_fini_component(cfdriver_ioconf_rge, 4028 cfattach_ioconf_rge, cfdata_ioconf_rge); 4029 #endif 4030 return error; 4031 default: 4032 return ENOTTY; 4033 } 4034 } 4035
Indexes created Sun Oct 25 00:26:45 UTC 2026