1 /* $NetBSD: fwohci_cardbus.c,v 1.37 2021/07/24 21:31:36 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: fwohci_cardbus.c,v 1.37 2021/07/24 21:31:36 andvar Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/socket.h> 38 #include <sys/device.h> 39 #include <sys/select.h> 40 41 #include <sys/bus.h> 42 43 #if defined pciinc 44 #include <dev/pci/pcidevs.h> 45 #endif 46 47 #include <dev/cardbus/cardbusvar.h> 48 #include <dev/pci/pcidevs.h> 49 50 #include <dev/ieee1394/firewire.h> 51 #include <dev/ieee1394/firewirereg.h> 52 #include <dev/ieee1394/fwdma.h> 53 #include <dev/ieee1394/fwohcireg.h> 54 #include <dev/ieee1394/fwohcivar.h> 55 56 struct fwohci_cardbus_softc { 57 struct fwohci_softc sc_sc; 58 cardbus_chipset_tag_t sc_cc; 59 cardbus_function_tag_t sc_cf; 60 cardbus_devfunc_t sc_ct; 61 void *sc_ih; 62 }; 63 64 static int fwohci_cardbus_match(device_t, cfdata_t, void *); 65 static void fwohci_cardbus_attach(device_t, device_t, void *); 66 static int fwohci_cardbus_detach(device_t, int); 67 68 CFATTACH_DECL_NEW(fwohci_cardbus, sizeof(struct fwohci_cardbus_softc), 69 fwohci_cardbus_match, fwohci_cardbus_attach, fwohci_cardbus_detach, NULL); 70 71 static int 72 fwohci_cardbus_match(device_t parent, cfdata_t match, void *aux) 73 { 74 struct cardbus_attach_args *ca = (struct cardbus_attach_args *)aux; 75 76 if (PCI_CLASS(ca->ca_class) == PCI_CLASS_SERIALBUS && 77 PCI_SUBCLASS(ca->ca_class) == 78 PCI_SUBCLASS_SERIALBUS_FIREWIRE && 79 PCI_INTERFACE(ca->ca_class) == PCI_INTERFACE_OHCI) 80 return 1; 81 82 return 0; 83 } 84 85 static void 86 fwohci_cardbus_attach(device_t parent, device_t self, void *aux) 87 { 88 struct cardbus_attach_args *ca = aux; 89 struct fwohci_cardbus_softc *sc = device_private(self); 90 cardbus_devfunc_t ct = ca->ca_ct; 91 cardbus_chipset_tag_t cc = ct->ct_cc; 92 cardbus_function_tag_t cf = ct->ct_cf; 93 pcireg_t csr; 94 char devinfo[256]; 95 96 pci_devinfo(ca->ca_id, ca->ca_class, 0, devinfo, sizeof(devinfo)); 97 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 98 PCI_REVISION(ca->ca_class)); 99 aprint_naive("\n"); 100 101 fwohci_init(&sc->sc_sc); 102 103 /* Map I/O registers */ 104 if (Cardbus_mapreg_map(ct, PCI_OHCI_MAP_REGISTER, PCI_MAPREG_TYPE_MEM, 105 0, &sc->sc_sc.bst, &sc->sc_sc.bsh, NULL, &sc->sc_sc.bssize)) { 106 aprint_error_dev(self, "can't map OHCI register space\n"); 107 return; 108 } 109 110 sc->sc_sc.fc.dev = self; 111 sc->sc_sc.fc.dmat = ca->ca_dmat; 112 sc->sc_cc = cc; 113 sc->sc_cf = cf; 114 sc->sc_ct = ct; 115 116 /* Disable interrupts, so we don't get any spurious ones. */ 117 OWRITE(&sc->sc_sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 118 119 /* Enable the device. */ 120 csr = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG); 121 Cardbus_conf_write(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG, 122 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE); 123 124 sc->sc_ih = Cardbus_intr_establish(ct, IPL_BIO, fwohci_intr, sc); 125 if (sc->sc_ih == NULL) { 126 aprint_error_dev(self, "couldn't establish interrupt\n"); 127 return; 128 } 129 130 /* XXX NULL should be replaced by some call to Cardbus code */ 131 if (fwohci_attach(&sc->sc_sc) != 0) { 132 Cardbus_intr_disestablish(ct, sc->sc_ih); 133 sc->sc_ih = NULL; 134 } 135 } 136 137 int 138 fwohci_cardbus_detach(device_t self, int flags) 139 { 140 struct fwohci_cardbus_softc *sc = device_private(self); 141 cardbus_devfunc_t ct = sc->sc_ct; 142 int rv; 143 144 rv = fwohci_detach(&sc->sc_sc, flags); 145 146 if (rv) 147 return (rv); 148 if (sc->sc_ih != NULL) { 149 Cardbus_intr_disestablish(ct, sc->sc_ih); 150 sc->sc_ih = NULL; 151 } 152 if (sc->sc_sc.bssize) { 153 Cardbus_mapreg_unmap(ct, PCI_OHCI_MAP_REGISTER, 154 sc->sc_sc.bst, sc->sc_sc.bsh, 155 sc->sc_sc.bssize); 156 sc->sc_sc.bssize = 0; 157 } 158 return (0); 159 } 160
Indexes created Sun Oct 25 00:26:45 UTC 2026