1 /* $NetBSD: hpc.c,v 1.75 2026/06/11 01:03:58 rumble Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Soren S. Jorvang 5 * Copyright (c) 2001 Rafal K. Boni 6 * Copyright (c) 2001 Jason R. Thorpe 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: hpc.c,v 1.75 2026/06/11 01:03:58 rumble Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/reboot.h> 45 #include <sys/callout.h> 46 47 #include <sys/bus.h> 48 #include <machine/machtype.h> 49 #include <machine/sysconf.h> 50 51 #include <sgimips/gio/gioreg.h> 52 #include <sgimips/gio/giovar.h> 53 54 #include <sgimips/hpc/hpcvar.h> 55 #include <sgimips/hpc/hpcreg.h> 56 #include <sgimips/ioc/iocreg.h> 57 58 #include <dev/ic/smc93cx6var.h> 59 60 #include "locators.h" 61 62 struct hpc_device { 63 const char *hd_name; 64 bus_addr_t hd_base; 65 bus_addr_t hd_devoff; 66 bus_addr_t hd_dmaoff; 67 int hd_irq; 68 int hd_sysmask; 69 }; 70 71 static const struct hpc_device hpc1_devices[] = { 72 /* probe order is important for IP20 zsc */ 73 74 { "zsc", /* Personal Iris/Indigo serial 0/1 duart 1 */ 75 HPC_BASE_ADDRESS_0, 76 0x0d10, 0, 77 5, 78 HPCDEV_IP12 | HPCDEV_IP20 }, 79 80 { "zsc", /* Personal Iris/Indigo kbd/ms duart 0 */ 81 HPC_BASE_ADDRESS_0, 82 0x0d00, 0, 83 5, 84 HPCDEV_IP12 | HPCDEV_IP20 }, 85 86 { "sq", /* Personal Iris/Indigo onboard ethernet */ 87 HPC_BASE_ADDRESS_0, 88 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 89 3, 90 HPCDEV_IP12 | HPCDEV_IP20 }, 91 92 { "sq", /* E++ GIO adapter slot 0 (Indigo) */ 93 HPC_BASE_ADDRESS_1, 94 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 95 6, 96 HPCDEV_IP12 | HPCDEV_IP20 }, 97 98 { "sq", /* E++ GIO adapter slot 0 (Indy) */ 99 HPC_BASE_ADDRESS_1, 100 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 101 22, 102 HPCDEV_IP24 }, 103 104 { "sq", /* E++ GIO adapter slot 1 (Indigo) */ 105 HPC_BASE_ADDRESS_2, 106 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 107 6, 108 HPCDEV_IP12 | HPCDEV_IP20 }, 109 110 { "sq", /* E++ GIO adapter slot 1 (Indy/Challenge S) */ 111 HPC_BASE_ADDRESS_2, 112 HPC1_ENET_DEVREGS, HPC1_ENET_REGS, 113 23, 114 HPCDEV_IP24 }, 115 116 { "wdsc", /* Personal Iris/Indigo onboard SCSI */ 117 HPC_BASE_ADDRESS_0, 118 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 119 2, /* XXX 1 = IRQ_LOCAL0 + 2 */ 120 HPCDEV_IP12 | HPCDEV_IP20 }, 121 122 { "wdsc", /* GIO32 SCSI adapter slot 0 (Indigo) */ 123 HPC_BASE_ADDRESS_1, 124 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 125 6, 126 HPCDEV_IP12 | HPCDEV_IP20 }, 127 128 { "wdsc", /* GIO32 SCSI adapter slot 0 (Indy) */ 129 HPC_BASE_ADDRESS_1, 130 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 131 22, 132 HPCDEV_IP24 }, 133 134 { "wdsc", /* GIO32 SCSI adapter slot 1 (Indigo) */ 135 HPC_BASE_ADDRESS_2, 136 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 137 6, 138 HPCDEV_IP12 | HPCDEV_IP20 }, 139 140 { "wdsc", /* GIO32 SCSI adapter slot 1 (Indy/Challenge S) */ 141 HPC_BASE_ADDRESS_2, 142 HPC1_SCSI0_DEVREGS, HPC1_SCSI0_REGS, 143 23, 144 HPCDEV_IP24 }, 145 146 { "haud", /* Personal Iris/Indigo Hollywood Audio DSP */ 147 HPC_BASE_ADDRESS_0, 148 HPC1_DSP_DEVREGS, HPC1_DSP_SRAM, 149 8 + 4, /* IRQ_LOCAL1 + 4 */ 150 HPCDEV_IP12 | HPCDEV_IP20 }, 151 152 { NULL, 153 0, 154 0, 0, 155 0, 156 0 157 } 158 }; 159 160 static const struct hpc_device hpc3_devices[] = { 161 { "zsc", /* serial 0/1 duart 0 */ 162 HPC_BASE_ADDRESS_0, 163 /* XXX Magic numbers */ 164 HPC3_PBUS_CH6_DEVREGS + IOC_SERIAL_REGS, 0, 165 29, 166 HPCDEV_IP22 | HPCDEV_IP24 }, 167 168 { "pckbc", /* Indigo2/Indy ps2 keyboard/mouse controller */ 169 HPC_BASE_ADDRESS_0, 170 HPC3_PBUS_CH6_DEVREGS + IOC_KB_REGS, 0, 171 28, 172 HPCDEV_IP22 | HPCDEV_IP24 }, 173 174 { "sq", /* Indigo2/Indy/Challenge S/Challenge M onboard enet */ 175 HPC_BASE_ADDRESS_0, 176 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 177 3, 178 HPCDEV_IP22 | HPCDEV_IP24 }, 179 180 { "sq", /* Challenge S IOPLUS secondary ethernet */ 181 HPC_BASE_ADDRESS_1, 182 HPC3_ENET_DEVREGS, HPC3_ENET_REGS, 183 0, 184 HPCDEV_IP24 }, 185 186 { "wdsc", /* Indigo2/Indy/Challenge S/Challenge M onboard SCSI */ 187 HPC_BASE_ADDRESS_0, 188 HPC3_SCSI0_DEVREGS, HPC3_SCSI0_REGS, 189 1, /* XXX 1 = IRQ_LOCAL0 + 1 */ 190 HPCDEV_IP22 | HPCDEV_IP24 }, 191 192 { "wdsc", /* Indigo2/Challenge M secondary onboard SCSI */ 193 HPC_BASE_ADDRESS_0, 194 HPC3_SCSI1_DEVREGS, HPC3_SCSI1_REGS, 195 2, /* XXX 2 = IRQ_LOCAL0 + 2 */ 196 HPCDEV_IP22 }, 197 198 { "haltwo", /* Indigo2/Indy onboard audio */ 199 HPC_BASE_ADDRESS_0, 200 HPC3_PBUS_CH0_DEVREGS, HPC3_PBUS_DMAREGS, 201 8 + 4, /* XXX IRQ_LOCAL1 + 4 */ 202 HPCDEV_IP22 | HPCDEV_IP24 }, 203 204 { "pi1ppc", /* Indigo2/Indy/Challenge S/Challenge M onboard pport */ 205 HPC_BASE_ADDRESS_0, 206 HPC3_PBUS_CH6_DEVREGS + IOC_PLP_REGS, 0, 207 -1, 208 HPCDEV_IP22 | HPCDEV_IP24 }, 209 210 { "button", /* Indy front panel */ 211 HPC_BASE_ADDRESS_0, 212 HPC3_PBUS_CH6_DEVREGS + IOC_PANEL, 0, 213 9, 214 HPCDEV_IP24 }, 215 216 { NULL, 217 0, 218 0, 0, 219 0, 220 0 221 } 222 }; 223 224 struct hpc_softc { 225 device_t sc_dev; 226 227 bus_addr_t sc_base; 228 229 bus_space_tag_t sc_ct; 230 bus_space_handle_t sc_ch; 231 }; 232 233 static struct hpc_values hpc1_values = { 234 .revision = 1, 235 .scsi0_regs = HPC1_SCSI0_REGS, 236 .scsi0_regs_size = HPC1_SCSI0_REGS_SIZE, 237 .scsi0_cbp = HPC1_SCSI0_CBP, 238 .scsi0_ndbp = HPC1_SCSI0_NDBP, 239 .scsi0_bc = HPC1_SCSI0_BC, 240 .scsi0_ctl = HPC1_SCSI0_CTL, 241 .scsi0_gio = HPC1_SCSI0_GIO, 242 .scsi0_dev = HPC1_SCSI0_DEV, 243 .scsi0_dmacfg = HPC1_SCSI0_DMACFG, 244 .scsi0_piocfg = HPC1_SCSI0_PIOCFG, 245 .scsi1_regs = 0, 246 .scsi1_regs_size = 0, 247 .scsi1_cbp = 0, 248 .scsi1_ndbp = 0, 249 .scsi1_bc = 0, 250 .scsi1_ctl = 0, 251 .scsi1_gio = 0, 252 .scsi1_dev = 0, 253 .scsi1_dmacfg = 0, 254 .scsi1_piocfg = 0, 255 .enet_regs = HPC1_ENET_REGS, 256 .enet_regs_size = HPC1_ENET_REGS_SIZE, 257 .enet_intdelay = HPC1_ENET_INTDELAY, 258 .enet_intdelayval = HPC1_ENET_INTDELAY_OFF, 259 .enetr_cbp = HPC1_ENETR_CBP, 260 .enetr_ndbp = HPC1_ENETR_NDBP, 261 .enetr_bc = HPC1_ENETR_BC, 262 .enetr_ctl = HPC1_ENETR_CTL, 263 .enetr_ctl_active = HPC1_ENETR_CTL_ACTIVE, 264 .enetr_reset = HPC1_ENETR_RESET, 265 .enetr_dmacfg = 0, 266 .enetr_piocfg = 0, 267 .enetx_cbp = HPC1_ENETX_CBP, 268 .enetx_ndbp = HPC1_ENETX_NDBP, 269 .enetx_bc = HPC1_ENETX_BC, 270 .enetx_ctl = HPC1_ENETX_CTL, 271 .enetx_ctl_active = HPC1_ENETX_CTL_ACTIVE, 272 .enetx_dev = 0, 273 .enetr_fifo = HPC1_ENETR_FIFO, 274 .enetr_fifo_size = HPC1_ENETR_FIFO_SIZE, 275 .enetx_fifo = HPC1_ENETX_FIFO, 276 .enetx_fifo_size = HPC1_ENETX_FIFO_SIZE, 277 .scsi0_devregs_size = HPC1_SCSI0_DEVREGS_SIZE, 278 .scsi1_devregs_size = 0, 279 .enet_devregs = HPC1_ENET_DEVREGS, 280 .enet_devregs_size = HPC1_ENET_DEVREGS_SIZE, 281 .pbus_fifo = 0, 282 .pbus_fifo_size = 0, 283 .pbus_bbram = 0, 284 #define MAX_SCSI_XFER (512*1024) 285 .scsi_max_xfer = MAX_SCSI_XFER, 286 .scsi_dma_segs = (MAX_SCSI_XFER / 4096), 287 .scsi_dma_segs_size = 4096, 288 .scsi_dma_datain_cmd = (HPC1_SCSI_DMACTL_ACTIVE | HPC1_SCSI_DMACTL_DIR), 289 .scsi_dma_dataout_cmd = HPC1_SCSI_DMACTL_ACTIVE, 290 .scsi_dmactl_flush = HPC1_SCSI_DMACTL_FLUSH, 291 .scsi_dmactl_active = HPC1_SCSI_DMACTL_ACTIVE, 292 .scsi_dmactl_reset = HPC1_SCSI_DMACTL_RESET 293 }; 294 295 static struct hpc_values hpc3_values = { 296 .revision = 3, 297 .scsi0_regs = HPC3_SCSI0_REGS, 298 .scsi0_regs_size = HPC3_SCSI0_REGS_SIZE, 299 .scsi0_cbp = HPC3_SCSI0_CBP, 300 .scsi0_ndbp = HPC3_SCSI0_NDBP, 301 .scsi0_bc = HPC3_SCSI0_BC, 302 .scsi0_ctl = HPC3_SCSI0_CTL, 303 .scsi0_gio = HPC3_SCSI0_GIO, 304 .scsi0_dev = HPC3_SCSI0_DEV, 305 .scsi0_dmacfg = HPC3_SCSI0_DMACFG, 306 .scsi0_piocfg = HPC3_SCSI0_PIOCFG, 307 .scsi1_regs = HPC3_SCSI1_REGS, 308 .scsi1_regs_size = HPC3_SCSI1_REGS_SIZE, 309 .scsi1_cbp = HPC3_SCSI1_CBP, 310 .scsi1_ndbp = HPC3_SCSI1_NDBP, 311 .scsi1_bc = HPC3_SCSI1_BC, 312 .scsi1_ctl = HPC3_SCSI1_CTL, 313 .scsi1_gio = HPC3_SCSI1_GIO, 314 .scsi1_dev = HPC3_SCSI1_DEV, 315 .scsi1_dmacfg = HPC3_SCSI1_DMACFG, 316 .scsi1_piocfg = HPC3_SCSI1_PIOCFG, 317 .enet_regs = HPC3_ENET_REGS, 318 .enet_regs_size = HPC3_ENET_REGS_SIZE, 319 .enet_intdelay = 0, 320 .enet_intdelayval = 0, 321 .enetr_cbp = HPC3_ENETR_CBP, 322 .enetr_ndbp = HPC3_ENETR_NDBP, 323 .enetr_bc = HPC3_ENETR_BC, 324 .enetr_ctl = HPC3_ENETR_CTL, 325 .enetr_ctl_active = HPC3_ENETR_CTL_ACTIVE, 326 .enetr_reset = HPC3_ENETR_RESET, 327 .enetr_dmacfg = HPC3_ENETR_DMACFG, 328 .enetr_piocfg = HPC3_ENETR_PIOCFG, 329 .enetx_cbp = HPC3_ENETX_CBP, 330 .enetx_ndbp = HPC3_ENETX_NDBP, 331 .enetx_bc = HPC3_ENETX_BC, 332 .enetx_ctl = HPC3_ENETX_CTL, 333 .enetx_ctl_active = HPC3_ENETX_CTL_ACTIVE, 334 .enetx_dev = HPC3_ENETX_DEV, 335 .enetr_fifo = HPC3_ENETR_FIFO, 336 .enetr_fifo_size = HPC3_ENETR_FIFO_SIZE, 337 .enetx_fifo = HPC3_ENETX_FIFO, 338 .enetx_fifo_size = HPC3_ENETX_FIFO_SIZE, 339 .scsi0_devregs_size = HPC3_SCSI0_DEVREGS_SIZE, 340 .scsi1_devregs_size = HPC3_SCSI1_DEVREGS_SIZE, 341 .enet_devregs = HPC3_ENET_DEVREGS, 342 .enet_devregs_size = HPC3_ENET_DEVREGS_SIZE, 343 .pbus_fifo = HPC3_PBUS_FIFO, 344 .pbus_fifo_size = HPC3_PBUS_FIFO_SIZE, 345 .pbus_bbram = HPC3_PBUS_BBRAM, 346 .scsi_max_xfer = MAX_SCSI_XFER, 347 .scsi_dma_segs = (MAX_SCSI_XFER / 8192), 348 .scsi_dma_segs_size = 8192, 349 .scsi_dma_datain_cmd = HPC3_SCSI_DMACTL_ACTIVE, 350 .scsi_dma_dataout_cmd =(HPC3_SCSI_DMACTL_ACTIVE | HPC3_SCSI_DMACTL_DIR), 351 .scsi_dmactl_flush = HPC3_SCSI_DMACTL_FLUSH, 352 .scsi_dmactl_active = HPC3_SCSI_DMACTL_ACTIVE, 353 .scsi_dmactl_reset = HPC3_SCSI_DMACTL_RESET 354 }; 355 356 static int hpc_match(device_t, cfdata_t, void *); 357 static void hpc_attach(device_t, device_t, void *); 358 static int hpc_print(void *, const char *); 359 360 static int hpc_revision(struct hpc_softc *, struct gio_attach_args *); 361 362 static int hpc_submatch(device_t, cfdata_t, const int *, void *); 363 364 //static int hpc_power_intr(void *); 365 366 #if defined(BLINK) 367 static callout_t hpc_blink_ch; 368 static void hpc_blink(void *); 369 #endif 370 371 static int hpc_read_eeprom(int, bus_space_tag_t, bus_space_handle_t, 372 uint8_t *, size_t); 373 374 CFATTACH_DECL_NEW(hpc, sizeof(struct hpc_softc), 375 hpc_match, hpc_attach, NULL, NULL); 376 377 static void hpc_bus_mem_init(bus_space_tag_t, void *); 378 379 static struct mips_bus_space hpc_mbst; 380 bus_space_tag_t hpc_memt = NULL; 381 382 383 static int 384 hpc_match(device_t parent, cfdata_t cf, void *aux) 385 { 386 struct gio_attach_args* ga = aux; 387 388 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20 || 389 mach_type == MACH_SGI_IP22) { 390 /* Make sure it's actually there and readable */ 391 if (!platform.badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), 392 sizeof(uint32_t))) 393 return 1; 394 } 395 396 return 0; 397 } 398 399 static void 400 hpc_attach(device_t parent, device_t self, void *aux) 401 { 402 struct hpc_softc *sc = device_private(self); 403 struct gio_attach_args* ga = aux; 404 struct hpc_attach_args ha; 405 const struct hpc_device *hd; 406 uint32_t hpctype; 407 int isonboard; 408 int isioplus; 409 int sysmask; 410 411 sc->sc_dev = self; 412 413 #ifdef BLINK 414 callout_init(&hpc_blink_ch, 0); 415 #endif 416 417 switch (mach_type) { 418 case MACH_SGI_IP12: 419 sysmask = HPCDEV_IP12; 420 break; 421 422 case MACH_SGI_IP20: 423 sysmask = HPCDEV_IP20; 424 break; 425 426 case MACH_SGI_IP22: 427 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) 428 sysmask = HPCDEV_IP22; 429 else 430 sysmask = HPCDEV_IP24; 431 break; 432 433 default: 434 panic("hpc_attach: can't handle HPC on an IP%d", mach_type); 435 }; 436 437 if ((hpctype = hpc_revision(sc, ga)) == 0) 438 panic("hpc_attach: could not identify HPC revision\n"); 439 440 /* force big-endian mode */ 441 if (hpctype == 15) 442 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0; 443 444 /* 445 * All machines have only one HPC on the mainboard itself. ''Extra'' 446 * HPCs require bus arbiter and other magic to run happily. 447 */ 448 isonboard = (ga->ga_addr == HPC_BASE_ADDRESS_0); 449 isioplus = (ga->ga_addr == HPC_BASE_ADDRESS_1 && hpctype == 3 && 450 sysmask == HPCDEV_IP24); 451 452 printf(": SGI HPC%d%s (%s)\n", (hpctype == 3) ? 3 : 1, 453 (hpctype == 15) ? ".5" : "", (isonboard) ? "onboard" : 454 (isioplus) ? "IOPLUS mezzanine" : "GIO slot"); 455 456 /* 457 * Configure the bus arbiter appropriately. 458 * 459 * In the case of Challenge S, we must tell the IOPLUS board which 460 * DMA channel to use (we steal it from one of the slots). SGI permits 461 * an HPC1.5 in slot 1, in which case IOPLUS must use EXP0, or any 462 * other DMA-capable board in slot 0, which leaves us to use EXP1. Of 463 * course, this means that only one GIO board may use DMA. 464 * 465 * Note that this never happens on Indigo2. 466 */ 467 if (isioplus) { 468 int arb_slot; 469 470 if (platform.badaddr( 471 (void *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_2), 4)) 472 arb_slot = GIO_SLOT_EXP1; 473 else 474 arb_slot = GIO_SLOT_EXP0; 475 476 if (gio_arb_config(arb_slot, GIO_ARB_LB | GIO_ARB_MST | 477 GIO_ARB_64BIT | GIO_ARB_HPC2_64BIT)) { 478 printf("%s: failed to configure GIO bus arbiter\n", 479 device_xname(sc->sc_dev)); 480 return; 481 } 482 483 printf("%s: using EXP%d's DMA channel\n", 484 device_xname(sc->sc_dev), 485 (arb_slot == GIO_SLOT_EXP0) ? 0 : 1); 486 487 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 488 HPC3_PBUS_CFGPIO_REGS, 0x0003ffff); 489 490 if (arb_slot == GIO_SLOT_EXP0) 491 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 492 HPC3_PBUS_CH0_DEVREGS, 0x20202020); 493 else 494 bus_space_write_4(ga->ga_iot, ga->ga_ioh, 495 HPC3_PBUS_CH0_DEVREGS, 0x30303030); 496 } else if (!isonboard) { 497 int arb_slot; 498 499 arb_slot = (ga->ga_addr == HPC_BASE_ADDRESS_1) ? 500 GIO_SLOT_EXP0 : GIO_SLOT_EXP1; 501 502 if (gio_arb_config(arb_slot, GIO_ARB_RT | GIO_ARB_MST)) { 503 printf("%s: failed to configure GIO bus arbiter\n", 504 device_xname(sc->sc_dev)); 505 return; 506 } 507 } 508 509 hpc_bus_mem_init(&hpc_mbst, NULL); 510 hpc_memt = &hpc_mbst; 511 512 sc->sc_ct = normal_memt; 513 sc->sc_ch = ga->ga_ioh; 514 515 sc->sc_base = ga->ga_addr; 516 517 hpc_read_eeprom(hpctype, normal_memt, 518 MIPS_PHYS_TO_KSEG1(sc->sc_base), ha.hpc_eeprom, 519 sizeof(ha.hpc_eeprom)); 520 521 hd = (hpctype == 3) ? hpc3_devices : hpc1_devices; 522 for (; hd->hd_name != NULL; hd++) { 523 if (!(hd->hd_sysmask & sysmask) || hd->hd_base != sc->sc_base) 524 continue; 525 526 ha.ha_name = hd->hd_name; 527 ha.ha_devoff = hd->hd_devoff; 528 ha.ha_dmaoff = hd->hd_dmaoff; 529 ha.ha_irq = hd->hd_irq; 530 531 /* XXX This is disgusting. */ 532 ha.ha_st = normal_memt; 533 if (bus_space_map(normal_memt, sc->sc_base, 0, 534 BUS_SPACE_MAP_LINEAR, &ha.ha_sh) != 0) 535 continue; 536 ha.ha_dmat = &sgimips_default_bus_dma_tag; 537 if (hpctype == 3) 538 ha.hpc_regs = &hpc3_values; 539 else 540 ha.hpc_regs = &hpc1_values; 541 ha.hpc_regs->revision = hpctype; 542 543 /* XXXgross! avoid complaining in E++ and GIO32 SCSI cases */ 544 if (hpctype != 3 && sc->sc_base != HPC_BASE_ADDRESS_0) { 545 config_found(self, &ha, NULL, 546 CFARGS(.submatch = hpc_submatch)); 547 } else { 548 config_found(self, &ha, hpc_print, 549 CFARGS(.submatch = hpc_submatch)); 550 } 551 } 552 553 #if defined(BLINK) 554 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) 555 hpc_blink(sc); 556 #endif 557 } 558 559 /* 560 * HPC revision detection isn't as simple as it should be. Devices probe 561 * differently depending on their slots, but luckily there is only one 562 * instance in which we have to decide the major revision (HPC1 vs HPC3). 563 * 564 * The HPC is found in the following configurations: 565 * o Personal Iris 4D/3x: 566 * One on-board HPC1 or HPC1.5. 567 * 568 * o Indigo R3k/R4k: 569 * One on-board HPC1 or HPC1.5. 570 * Up to two additional HPC1.5's in GIO slots 0 and 1. 571 * 572 * o Indy: 573 * One on-board HPC3. 574 * Up to two additional HPC1.5's in GIO slots 0 and 1. 575 * 576 * o Challenge S 577 * One on-board HPC3. 578 * Up to one additional HPC3 on the IOPLUS board (if installed). 579 * Up to one additional HPC1.5 in slot 1 of the IOPLUS board. 580 * 581 * o Indigo2, Challenge M 582 * One on-board HPC3. 583 * 584 * All we really have to worry about is the IP22 case. 585 */ 586 static int 587 hpc_revision(struct hpc_softc *sc, struct gio_attach_args *ga) 588 { 589 590 /* No hardware ever supported the last hpc base address. */ 591 if (ga->ga_addr == HPC_BASE_ADDRESS_3) 592 return (0); 593 594 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20) { 595 uint32_t reg; 596 597 if (!platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 598 HPC1_BIGENDIAN), 4)) { 599 reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 600 HPC1_BIGENDIAN); 601 602 if (((reg >> HPC1_REVSHIFT) & HPC1_REVMASK) == 603 HPC1_REV15) 604 return (15); 605 else 606 return (1); 607 } 608 609 return (1); 610 } 611 612 /* 613 * If IP22, probe slot 0 to determine if HPC1.5 or HPC3. Slot 1 must 614 * be HPC1.5. 615 */ 616 if (mach_type == MACH_SGI_IP22) { 617 if (ga->ga_addr == HPC_BASE_ADDRESS_0) 618 return (3); 619 620 if (ga->ga_addr == HPC_BASE_ADDRESS_2) 621 return (15); 622 623 /* 624 * Probe for it. We use one of the PBUS registers. Note 625 * that this probe succeeds with my E++ adapter in slot 1 626 * (bad), but it appears to always do the right thing in 627 * slot 0 (good!) and we're only worried about that one 628 * anyhow. 629 */ 630 if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + 631 HPC3_PBUS_CH7_BP), 4)) 632 return (15); 633 else 634 return (3); 635 } 636 637 return (0); 638 } 639 640 static int 641 hpc_submatch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 642 { 643 struct hpc_attach_args *ha = aux; 644 645 if (cf->cf_loc[HPCCF_OFFSET] != HPCCF_OFFSET_DEFAULT && 646 (bus_addr_t) cf->cf_loc[HPCCF_OFFSET] != ha->ha_devoff) 647 return (0); 648 649 return (config_match(parent, cf, aux)); 650 } 651 652 static int 653 hpc_print(void *aux, const char *pnp) 654 { 655 struct hpc_attach_args *ha = aux; 656 657 if (pnp) 658 printf("%s at %s", ha->ha_name, pnp); 659 660 printf(" offset %#" PRIxVADDR, (vaddr_t)ha->ha_devoff); 661 662 return (UNCONF); 663 } 664 665 #if defined(BLINK) 666 static void 667 hpc_blink(void *arg) 668 { 669 struct hpc_softc *sc = arg; 670 register int s; 671 int value; 672 673 s = splhigh(); 674 675 value = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 676 HPC1_AUX_REGS); 677 value ^= HPC1_AUX_CONSLED; 678 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + 679 HPC1_AUX_REGS) = value; 680 splx(s); 681 682 /* 683 * Blink rate is: 684 * full cycle every second if completely idle (loadav = 0) 685 * full cycle every 2 seconds if loadav = 1 686 * full cycle every 3 seconds if loadav = 2 687 * etc. 688 */ 689 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 690 callout_reset(&hpc_blink_ch, s, hpc_blink, sc); 691 } 692 #endif 693 694 /* 695 * Read the eeprom associated with one of the HPC's. 696 * 697 * NB: An eeprom is not always present, but the HPC should be able to 698 * handle this gracefully. Any consumers should validate the data to 699 * ensure it's reasonable. 700 */ 701 static int 702 hpc_read_eeprom(int hpctype, bus_space_tag_t t, bus_space_handle_t h, 703 uint8_t *buf, size_t len) 704 { 705 struct seeprom_descriptor sd; 706 bus_space_handle_t bsh; 707 bus_size_t offset; 708 709 if (!len || len & 0x1) 710 return (1); 711 712 offset = (hpctype == 3) ? HPC3_EEPROM_DATA : HPC1_AUX_REGS; 713 714 if (bus_space_subregion(t, h, offset, 1, &bsh) != 0) 715 return (1); 716 717 sd.sd_chip = C56_66; 718 sd.sd_tag = t; 719 sd.sd_bsh = bsh; 720 sd.sd_regsize = 1; 721 sd.sd_control_offset = 0; 722 sd.sd_status_offset = 0; 723 sd.sd_dataout_offset = 0; 724 /* The cx56 driver swaps the meaning of DI and DO. */ 725 sd.sd_DI = HPC_AUX_EEPROM_DO; /* EEPROM -> CPU */ 726 sd.sd_DO = HPC_AUX_EEPROM_DI; /* CPU -> EEPROM */ 727 sd.sd_CK = HPC_AUX_EEPROM_SK; 728 sd.sd_CS = HPC_AUX_EEPROM_CS; 729 sd.sd_MS = 0; 730 sd.sd_RDY = 0; 731 732 if (read_seeprom(&sd, (uint16_t *)buf, 0, len / 2) != 1) 733 return (1); 734 735 bus_space_unmap(t, bsh, 1); 736 737 return (0); 738 } 739 740 #define CHIP hpc 741 #define CHIP_MEM /* defined */ 742 #define CHIP_ALIGN_STRIDE 2 743 #define CHIP_ACCESS_SIZE 4 744 #define CHIP_W1_BUS_START(v) 0x00000000UL 745 #define CHIP_W1_BUS_END(v) 0xffffffffUL 746 #define CHIP_W1_SYS_START(v) 0x00000000UL 747 #define CHIP_W1_SYS_END(v) 0xffffffffUL 748 749 #include <mips/mips/bus_space_alignstride_chipdep.c> 750
Indexes created Sun Oct 25 00:26:45 UTC 2026