Searched refs:CPU (Results 1 - 25 of 127) sorted by relevance

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/src/sys/arch/epoc32/stand/e32boot/ldd/
H A Dcpu.h28 class CPU { class
34 class ARM7 : public CPU {
40 class ARM7TDMI : public CPU {
46 class SA1100 : public CPU {
H A Depoc32.h32 CPU *cpu;
/src/sys/arch/sh3/include/
H A Dendian_machdep.h4 # error Define SH target CPU endian-ness in port-specific header file.
/src/sys/external/bsd/compiler_rt/dist/lib/xray/
H A Dxray_powerpc64.inc22 ALWAYS_INLINE uint64_t readTSC(uint8_t &CPU) XRAY_NEVER_INSTRUMENT {
23 CPU = 0;
H A Dxray_x86_64.inc22 ALWAYS_INLINE uint64_t readTSC(uint8_t &CPU) XRAY_NEVER_INSTRUMENT {
26 CPU = LongCPU;
H A Dxray_tsc.h29 ALWAYS_INLINE uint64_t readTSC(uint8_t &CPU) XRAY_NEVER_INSTRUMENT { argument
30 CPU = 0;
50 // or slower depending on CPU turbo or power saving mode. Furthermore,
68 ALWAYS_INLINE uint64_t readTSC(uint8_t &CPU) XRAY_NEVER_INSTRUMENT { argument
76 CPU = 0;
88 #endif // CPU architecture
H A Dxray_fdr_controller.h85 // buffer, associated with a particular thread, with a new CPU. For the
148 uint16_t CPU) XRAY_NEVER_INSTRUMENT {
149 if (UNLIKELY(LatestCPU != CPU || LatestTSC == 0)) {
150 // We update our internal tracking state for the Latest TSC and CPU we've
153 LatestCPU = CPU;
158 W.writeMetadata<MetadataRecord::RecordKinds::NewCPUId>(CPU, TSC);
162 DCHECK_EQ(LatestCPU, CPU);
183 uint16_t CPU) XRAY_NEVER_INSTRUMENT {
246 uint16_t CPU) XRAY_NEVER_INSTRUMENT {
251 auto PreambleStatus = recordPreamble(TSC, CPU);
147 recordPreamble(uint64_t TSC,uint16_t CPU) argument
182 rewindRecords(int32_t FuncId,uint64_t TSC,uint16_t CPU) argument
245 functionEnter(int32_t FuncId,uint64_t TSC,uint16_t CPU) argument
269 functionTailExit(int32_t FuncId,uint64_t TSC,uint16_t CPU) argument
294 functionEnterArg(int32_t FuncId,uint64_t TSC,uint16_t CPU,uint64_t Arg) argument
311 functionExit(int32_t FuncId,uint64_t TSC,uint16_t CPU) argument
334 customEvent(uint64_t TSC,uint16_t CPU,const void * Event,int32_t EventSize) argument
348 typedEvent(uint64_t TSC,uint16_t CPU,uint16_t EventType,const void * Event,int32_t EventSize) argument
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H A Dxray_fdr_logging.cc154 // Version 4 includes CPU data in the custom event records.
156 // and removes the CPU data in custom event records (similar to how
158 // metadata records for TSC wraparound and CPU migration).
162 // Test for required CPU features and cache the cycle frequency
414 unsigned char CPU = 0; member in struct:__xray::TSCAndCPU
419 // we've seen this CPU before. We also do it before we load anything else,
423 // Test once for required CPU features
430 Result.TSC = __xray::readTSC(Result.CPU);
439 Result.CPU = 0;
500 auto &CPU local in function:__xray::fdrLoggingHandleArg0
530 auto &CPU = TC.CPU; local in function:__xray::fdrLoggingHandleArg1
560 auto &CPU = TC.CPU; local in function:__xray::fdrLoggingHandleCustomEvent
590 auto &CPU = TC.CPU; local in function:__xray::fdrLoggingHandleTypedEvent
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H A Dxray_basic_logging.cc51 uint8_t CPU; member in struct:__xray::__anon93d8eca50110::StackEntry
173 uint8_t CPU = 0; local in function:__xray::InMemoryRawLog
174 uint64_t TSC = ReadTSC(CPU);
183 // When we encounter an entry event, we keep track of the TSC and the CPU,
187 E.CPU = CPU;
207 // - The CPU is the same as the most recent entry in the stack.
217 if (StackTop.FuncId == FuncId && StackTop.CPU == CPU &&
238 R.CPU
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/src/sys/external/bsd/compiler_rt/dist/lib/xray/tests/unit/
H A Dfdr_controller_test.cc85 uint16_t CPU = 1; local in function:__xray::__anon7b5049890110::TEST_F
86 ASSERT_TRUE(C->functionEnter(FId, TSC++, CPU));
87 ASSERT_TRUE(C->functionExit(FId, TSC++, CPU));
88 ASSERT_TRUE(C->functionEnterArg(FId, TSC++, CPU, 1));
89 ASSERT_TRUE(C->functionTailExit(FId, TSC++, CPU));
144 uint16_t CPU = 0; local in function:__xray::__anon7b5049890110::TEST_F
145 ASSERT_TRUE(C->functionEnter(1, TSC++, CPU));
146 ASSERT_TRUE(C->functionEnter(2, TSC++, CPU));
147 ASSERT_TRUE(C->functionExit(2, TSC++, CPU));
148 ASSERT_TRUE(C->functionExit(1, TSC += 1000, CPU));
169 uint16_t CPU = 0; local in function:__xray::__anon7b5049890110::TEST_F
196 uint16_t CPU = 1; local in function:__xray::__anon7b5049890110::TEST_F
223 uint16_t CPU = 1; local in function:__xray::__anon7b5049890110::TEST_F
257 uint16_t CPU = 1; local in function:__xray::__anon7b5049890110::TEST_F
321 uint16_t CPU = 1; local in function:__xray::__anon7b5049890110::TEST_F
337 uint16_t CPU = 1; local in function:__xray::__anon7b5049890110::TEST_F
354 uint16_t CPU = 1; local in function:__xray::__anon7b5049890110::TEST_F
375 uint16_t CPU = 1; local in function:__xray::__anon7b5049890110::TEST_F
402 uint16_t CPU = 1; local in function:__xray::__anon7b5049890110::TEST_F
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/src/sys/arch/hpc/hpc/
H A Dplatid.awk52 if (mode != MACH && mode != CPU) {
85 if (mode == CPU) {
101 if (mode == CPU) {
127 CPU = 1
137 mode_name[CPU] = "CPU"
140 shifts[CPU, 0] = "PLATID_CPU_ARCH_SHIFT"
141 shifts[CPU, 1] = "PLATID_CPU_SERIES_SHIFT"
142 shifts[CPU, 2] = "PLATID_CPU_MODEL_SHIFT"
143 shifts[CPU,
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/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/
H A Dr8a779a0-falcon.dts3 * Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
14 model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
H A Dr8a779a0-falcon-cpu.dtsi3 * Device Tree Source for the Falcon CPU board
14 model = "Renesas Falcon CPU board";
/src/sys/arch/mips/include/
H A Dendian_machdep.h29 # error Define MIPS target CPU endian-ness in port-specific header file.
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dimx6q-skov-revc-lt2.dts11 model = "SKOV IMX6 CPU QuadCore";
H A Domap3-cpu-thermal.dtsi2 * Device Tree Source for OMAP3 SoC CPU thermal
H A Domap4-cpu-thermal.dtsi2 * Device Tree Source for OMAP4/5 SoC CPU thermal
H A Dsunxi-bananapi-m2-plus-v1.2.dtsi11 * resistance on the CPU regulator's feedback pin.
H A Darmada-388-clearfog.dts19 /* CON2, nearest CPU, USB2 only. */
26 /* Port 2, Lane 0. CON2, nearest CPU. */
H A Dkirkwood-blackarmor-nas220.dts97 * pin 1 - TX (CPU's TX)
98 * pin 4 - RX (CPU's RX)
/src/sys/arch/arm/arm/
H A Dcpufunc_asm_pj4b.S58 dsb @ Erratum#ARM-CPU-4742
66 bic r0, r0, #(1 << 12) @ Erratum#ARM-CPU-6136
73 bic r0, r0, #(1 << 2) @ Erratum#ARM-CPU-6409
/src/sys/arch/hpcarm/hpcarm/
H A Dkloader_machdep.c101 #error No support KLOADER with specific CPU type.
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/hisilicon/
H A Dhi6220-coresight.dtsi378 /* CTI - CPU-0 */
391 /* CTI - CPU-1 */
404 /* CTI - CPU-2 */
417 /* CTI - CPU-3 */
430 /* CTI - CPU-4 */
443 /* CTI - CPU-5 */
456 /* CTI - CPU-6 */
469 /* CTI - CPU-7 */
/src/sys/external/bsd/compiler_rt/dist/include/xray/
H A Dxray_records.h79 // The CPU where the thread is running. We assume number of CPUs <= 256.
80 uint8_t CPU = 0; member in struct:__xray::XRayRecord
/src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/mti/
H A Dsead3.dts64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
253 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */

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