| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| issue113.s | 6 A0 = 0;
8 A0.x = R0;
13 R0.L = SIGNBITS A0;
|
| random_0016.S | 9 dmm32 A0.w, 0xe1a3909e;
10 dmm32 A0.x, 0xffffffff;
12 A0 = LSHIFT A0 BY R2.L;
13 checkreg A0.w, 0x3ff868e4;
14 checkreg A0.x, 0x00000000;
18 dmm32 A0.w, 0x72af1593;
19 dmm32 A0.x, 0xfffffffd;
21 A0 = LSHIFT A0 BY R2.L
[all...] |
| addsub_flags.S | 12 A0 = A1 = 0;
26 a0=r0;
27 r1=a0+a1, r3=a0-a1;
29 _dbg a0;
36 a0=r2;
38 r1=a1+a0, r3=a1-a0;
40 _dbg a0;
50 a0=r0
[all...] |
| random_0008.S | 17 dmm32 A0.w, 0x3c57e100;
18 dmm32 A0.x, 0xfffffff2;
21 A1 = -A0;
27 dmm32 A0.w, 0x4ca147ce;
28 dmm32 A0.x, 0xffffff9d;
31 A0 = -A1;
32 checkreg A0.w, 0xf1dacb47;
33 checkreg A0.x, 0x0000007a;
37 dmm32 A0.w, 0x7826f07d;
38 dmm32 A0.x, 0xffffffc2
[all...] |
| random_0011.S | 9 dmm32 A0.w, 0x1890bdbc;
10 dmm32 A0.x, 0x00000079;
11 A0 = A0 << 0x2;
12 checkreg A0.w, 0x6242f6f0;
13 checkreg A0.x, 0xffffffe4;
25 dmm32 A0.w, 0x00000000;
26 dmm32 A0.x, 0x00000000;
27 A0 = A0 << 0x1f
[all...] |
| random_0017.S | 8 dmm32 A0.w, 0x2771851d;
9 dmm32 A0.x, 0xffffffc9;
10 A0 = A0 >>> 0x1b;
11 checkreg A0.w, 0xfffff924;
12 checkreg A0.x, 0xffffffff;
|
| random_0018.S | 62 dmm32 A0.w, 0x32b127c8;
63 dmm32 A0.x, 0x0000001a;
64 A0 = A0 >>> 0x6;
65 checkreg A0.w, 0x68cac49f;
66 checkreg A0.x, 0x00000000;
|
| random_0019.S | 19 dmm32 A0.w, 0x1096b1c1;
20 dmm32 A0.x, 0xfffffff1;
23 A0 -= R6.L * R7.L (W32);
24 checkreg A0.w, 0x80000000;
25 checkreg A0.x, 0xffffffff;
29 dmm32 A0.w, 0x30c8f917;
30 dmm32 A0.x, 0xffffffc8;
33 A0 -= R3.L * R4.L (W32);
34 checkreg A0.w, 0x80000000;
35 checkreg A0.x, 0xffffffff
[all...] |
| s8.s | 1 // Test rl4 = VMAX r5 A0<<1;
2 // Test rl4 = VMAX r5 A0>>1;
9 // max value in high half, hence bit into A0 is one
10 A0 = 0;
17 R7 = A0.w;
20 R7.L = A0.x;
23 // max value in low half, hence bit into A0 is zero
26 A0.w = R0;
33 R7 = A0.w;
36 R7.L = A0.x
[all...] |
| c_dsp32shift_bitmux.s | 9 A0 = 0;
18 //r0, r0, a0 >>= bitmux; invalid now
19 BITMUX( R0 , R1, A0) (ASR);
20 BITMUX( R0 , R2, A0) (ASR);
21 BITMUX( R0 , R3, A0) (ASR);
22 BITMUX( R0 , R4, A0) (ASR);
23 BITMUX( R0 , R5, A0) (ASR);
24 BITMUX( R0 , R6, A0) (ASR);
25 BITMUX( R0 , R7, A0) (ASR);
35 R0 = A0.w
[all...] |
| c_dsp32shift_vmax.s | 18 A0 = R2;
|
| issue89.s | 15 A0 = 0;
16 A0.w = R7;
17 _DBG A0;
19 A0 = ROT A0 BY R2.L;
21 _DBG A0;
23 R4 = A0.w;
24 R5 = A0.x;
|
| random_0009.S | 9 dmm32 A0.w, 0x16ba2677;
10 dmm32 A0.x, 0x00000000;
12 A0 -= R4.H * R4.H (W32);
13 checkreg A0.w, 0x96ba2678;
14 checkreg A0.x, 0xffffffff;
18 dmm32 A0.w, 0xf170d0c7;
19 dmm32 A0.x, 0xffffffff;
21 A0 -= R2.H * R2.L (W32);
22 checkreg A0.w, 0x80000000;
23 checkreg A0.x, 0xffffffff
[all...] |
| random_0014.S | 9 dmm32 A0.w, 0xf53d356e;
10 dmm32 A0.x, 0xffffffff;
12 A0 = ASHIFT A0 BY R5.L;
13 checkreg A0.w, 0x56e00000;
14 checkreg A0.x, 0xffffffd3;
18 dmm32 A0.w, 0x1dfd2a85;
19 dmm32 A0.x, 0xffffffbe;
21 A0 = LSHIFT A0 BY R2.L
[all...] |
| s11.s | 5 // RL0 = CC = BXOR (A0 AND R1) << 1;
6 // RL0 = CC = BXOR A0 AND R1;
7 // A0 <<=1 (BXOR A0 AND A1 CC);
8 // RL3 = CC = BXOR A0 AND A1 CC;
16 // RL0 = CC = BXOR (A0 AND R1) << 1;
19 A0.w = R0;
21 A0.x = R0.L;
24 R2.L = CC = BXORSHIFT( A0 , R1 );
25 R0 = A0.w
[all...] |
| s30.s | 9 A1 = A0 = 0;
12 A0.w = R0;
14 A0.x = R0;
16 R5.L = SIGNBITS A0;
18 A0 = ASHIFT A0 BY R5.L;
19 _DBG A0;
21 R4 = A0.w;
22 R5 = A0.x;
27 A1 = A0 = 0
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| issue113.s | 6 A0 = 0;
8 A0.x = R0;
13 R0.L = SIGNBITS A0;
|
| random_0016.S | 9 dmm32 A0.w, 0xe1a3909e;
10 dmm32 A0.x, 0xffffffff;
12 A0 = LSHIFT A0 BY R2.L;
13 checkreg A0.w, 0x3ff868e4;
14 checkreg A0.x, 0x00000000;
18 dmm32 A0.w, 0x72af1593;
19 dmm32 A0.x, 0xfffffffd;
21 A0 = LSHIFT A0 BY R2.L
[all...] |
| addsub_flags.S | 12 A0 = A1 = 0;
26 a0=r0;
27 r1=a0+a1, r3=a0-a1;
29 _dbg a0;
36 a0=r2;
38 r1=a1+a0, r3=a1-a0;
40 _dbg a0;
50 a0=r0
[all...] |
| random_0008.S | 17 dmm32 A0.w, 0x3c57e100;
18 dmm32 A0.x, 0xfffffff2;
21 A1 = -A0;
27 dmm32 A0.w, 0x4ca147ce;
28 dmm32 A0.x, 0xffffff9d;
31 A0 = -A1;
32 checkreg A0.w, 0xf1dacb47;
33 checkreg A0.x, 0x0000007a;
37 dmm32 A0.w, 0x7826f07d;
38 dmm32 A0.x, 0xffffffc2
[all...] |
| random_0011.S | 9 dmm32 A0.w, 0x1890bdbc;
10 dmm32 A0.x, 0x00000079;
11 A0 = A0 << 0x2;
12 checkreg A0.w, 0x6242f6f0;
13 checkreg A0.x, 0xffffffe4;
25 dmm32 A0.w, 0x00000000;
26 dmm32 A0.x, 0x00000000;
27 A0 = A0 << 0x1f
[all...] |
| random_0017.S | 8 dmm32 A0.w, 0x2771851d;
9 dmm32 A0.x, 0xffffffc9;
10 A0 = A0 >>> 0x1b;
11 checkreg A0.w, 0xfffff924;
12 checkreg A0.x, 0xffffffff;
|
| random_0018.S | 62 dmm32 A0.w, 0x32b127c8;
63 dmm32 A0.x, 0x0000001a;
64 A0 = A0 >>> 0x6;
65 checkreg A0.w, 0x68cac49f;
66 checkreg A0.x, 0x00000000;
|
| random_0019.S | 19 dmm32 A0.w, 0x1096b1c1;
20 dmm32 A0.x, 0xfffffff1;
23 A0 -= R6.L * R7.L (W32);
24 checkreg A0.w, 0x80000000;
25 checkreg A0.x, 0xffffffff;
29 dmm32 A0.w, 0x30c8f917;
30 dmm32 A0.x, 0xffffffc8;
33 A0 -= R3.L * R4.L (W32);
34 checkreg A0.w, 0x80000000;
35 checkreg A0.x, 0xffffffff
[all...] |
| s8.s | 1 // Test rl4 = VMAX r5 A0<<1;
2 // Test rl4 = VMAX r5 A0>>1;
9 // max value in high half, hence bit into A0 is one
10 A0 = 0;
17 R7 = A0.w;
20 R7.L = A0.x;
23 // max value in low half, hence bit into A0 is zero
26 A0.w = R0;
33 R7 = A0.w;
36 R7.L = A0.x
[all...] |
