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    Searched defs:EMAC_WRITE (Results 1 - 2 of 2) sorted by relevancy

  /src/sys/arch/arm/at91/
at91emac.c 83 #define EMAC_WRITE(x, y) \
87 #define EMAC_WRITE(x, y) ETHREG(x) = (y)
144 EMAC_WRITE(ETH_CTL, 0); // disable everything
145 EMAC_WRITE(ETH_IDR, -1); // disable interrupts
146 EMAC_WRITE(ETH_RBQP, 0); // clear receive
147 EMAC_WRITE(ETH_CFG,
149 EMAC_WRITE(ETH_TCR, 0); // send nothing
152 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
156 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
200 /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*
    [all...]
  /src/sys/arch/powerpc/ibm4xx/dev/
if_emac.c 279 #define EMAC_WRITE(sc, reg, val) \
516 EMAC_WRITE(sc, EMAC_ISR, ISR_ALL);
640 EMAC_WRITE(sc, EMAC_ISR, status);
813 EMAC_WRITE(sc, EMAC_TMR0, TMR0_GNP0 | TMR0_TFAE_2);
953 EMAC_WRITE(sc, EMAC_IAHR, enaddr[0] << 8 | enaddr[1]);
954 EMAC_WRITE(sc, EMAC_IALR,
969 EMAC_WRITE(sc, EMAC_MR1, sc->sc_mr1);
975 EMAC_WRITE(sc, EMAC_RMR, RMR_IAE | RMR_RRP | RMR_SP | RMR_TFAE_2 |
987 EMAC_WRITE(sc, EMAC_TMR1,
993 EMAC_WRITE(sc, EMAC_TRTR, TRTR_256)
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