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    Searched defs:HHI_MPLL_CNTL7 (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/arch/arm/amlogic/
mesongxbb_clkc.c 57 #define HHI_MPLL_CNTL7 CBUS_REG(0xa6)
129 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */
130 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
131 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */
147 MESON_CLK_GATE(MESONGXBB_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14),
meson8b_clkc.c 64 #define HHI_MPLL_CNTL7 CBUS_REG(0xa6)
259 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */
260 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
261 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */
277 MESON_CLK_GATE(MESON8B_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14),
mesong12_clkc.c 142 #define HHI_MPLL_CNTL7 CBUS_REG(0xa5)

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