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    Searched defs:IsLoad (Results 1 - 16 of 16) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
ARCOptAddrMode.cpp 424 bool IsLoad = Ldst->mayLoad();
426 Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register();
  /src/external/apache2/llvm/dist/clang/include/clang/StaticAnalyzer/Core/
Checker.h 197 const SVal &location, bool isLoad, const Stmt *S,
199 ((const CHECKER *)checker)->checkLocation(location, isLoad, S, C);
555 bool IsLoad;
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXSwapRemoval.cpp 74 unsigned int IsLoad : 1;
342 SwapVector[VecIdx].IsLoad = 1;
348 SwapVector[VecIdx].IsLoad = 1;
359 SwapVector[VecIdx].IsLoad = 1;
669 else if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
680 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad ||
697 if (SwapVector[UseIdx].IsSwap && !SwapVector[UseIdx].IsLoad &&
727 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad ||
778 if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) {
1004 if (SwapVector[EntryIdx].IsLoad)
    [all...]
PPCISelLowering.cpp 2927 bool isLoad = true;
2939 isLoad = false;
2946 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
2963 else if (!isLoad) {
8924 bool IsLoad = false;
8944 IsLoad = true;
8948 (!IsLoad && !V->isOnlyUserOf(V->getOperand(i).getNode())))
8951 return !(IsSplat && IsLoad);
  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/
CheckerManager.cpp 318 bool IsLoad;
324 SVal loc, bool isLoad, const Stmt *NodeEx,
327 : Checkers(checkers), Loc(loc), IsLoad(isLoad), NodeEx(NodeEx),
335 ProgramPoint::Kind K = IsLoad ? ProgramPoint::PreLoadKind :
342 checkFn(Loc, IsLoad, BoundEx, C);
352 SVal location, bool isLoad,
356 CheckLocationContext C(LocationCheckers, location, isLoad, NodeEx,
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
InlineSpiller.cpp 753 bool IsLoad = InstrReg;
754 if (!IsLoad)
761 if (!IsLoad)
768 if (IsLoad) {
MachineScheduler.cpp 1537 bool IsLoad;
1541 const TargetRegisterInfo *tri, bool IsLoad)
1542 : TII(tii), TRI(tri), IsLoad(IsLoad) {}
1644 if (IsLoad) {
1684 if ((IsLoad && !SU.getInstr()->mayLoad()) ||
1685 (!IsLoad && !SU.getInstr()->mayStore()))
1723 (IsLoad ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 1320 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1325 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1421 bool IsLoad = fieldFromInstruction(insn, 22, 1);
1537 if (IsLoad && Rt == Rt2)
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 498 bool IsLoad =
503 if (IsLoad || IsStore) {
838 bool IsLoad = isi32Load(Opcode);
839 assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store");
840 unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8;
845 if (IsLoad) {
861 bool IsLoad = isLoadSingle(Opcode);
876 if (IsLoad) {
ARMExpandPseudoInsts.cpp 157 bool IsLoad;
533 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
644 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
743 if (TableEntry->IsLoad) {
768 if (!TableEntry->IsLoad)
793 if (TableEntry->IsLoad)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonExpandCondsets.cpp 823 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore();
824 if (!IsLoad && !IsStore)
HexagonConstExtenders.cpp 1145 bool IsLoad = MI.mayLoad();
1155 if (IsLoad || IsStore) {
HexagonVectorCombine.cpp 173 : Base(B), Main{AI.Inst}, IsHvx(Hvx), IsLoad(Load) {}
178 bool IsLoad; // Is this a load group?
654 if (Move.IsLoad) {
727 Instruction *TopIn = Move.IsLoad ? Move.Main.front() : Move.Main.back();
780 if (Move.IsLoad) {
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGAtomic.cpp 1292 bool IsLoad = E->getOp() == AtomicExpr::AO__c11_atomic_load ||
1315 if (IsLoad)
1321 if (IsLoad || IsStore)
1349 if (!IsLoad)
1351 if (!IsLoad && !IsStore)
1378 if (!IsLoad) {
1386 if (!IsLoad && !IsStore) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 3318 bool IsLoad = Opcode == Instruction::Load;
3385 (!IsLoad || Alignment.valueOrOne() < CurrOpSizeBytes) &&
3396 Cost += getShuffleCost(IsLoad ? TTI::ShuffleKind::SK_InsertSubvector
3413 Cost += getScalarizationOverhead(CoalescedVecTy, DemandedElts, IsLoad,
3414 !IsLoad);
3440 bool IsLoad = (Instruction::Load == Opcode);
3451 if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) ||
3464 getScalarizationOverhead(SrcVTy, DemandedElts, IsLoad, IsStore);
3490 return Cost + LT.first * (IsLoad ? 2 : 8);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
DAGCombiner.cpp 15036 bool &IsLoad, bool &IsMasked, SDValue &Ptr,
15052 IsLoad = false;
15070 IsLoad = false;
15087 bool IsLoad = true;
15090 if (!getCombineLoadStoreParts(N, ISD::PRE_INC, ISD::PRE_DEC, IsLoad, IsMasked,
15134 if (!IsLoad) {
15213 if (IsLoad)
15219 if (IsLoad)
15231 if (IsLoad) {
15282 SDValue NewOp2 = Result.getValue(IsLoad ? 1 : 0)
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