| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| VPlan.h | 99 /// vectors, where for the latter the lane index sometimes needs calculating
103 /// Kind describes how to interpret Lane.
105 /// For First, Lane is the index into the first N elements of a
108 /// For ScalableLast, Lane is the offset from the start of the last
110 /// example, a Lane of 0 corresponds to lane `(vscale - 1) * N`, a Lane of
117 unsigned Lane;
119 /// Indicates how the Lane should be interpreted, as described above.
123 VPLane(unsigned Lane, Kind LaneKind) : Lane(Lane), LaneKind(LaneKind) {
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| VPlan.cpp | 67 // Lane = RuntimeVF - VF.getKnownMinValue() + Lane
69 Builder.getInt32(VF.getKnownMinValue() - Lane));
71 return Builder.getInt32(Lane);
73 llvm_unreachable("Unknown lane kind");
233 .PerPartScalars[Def][Instance.Part][Instance.Lane.mapToCacheIndex(VF)];
239 assert(Instance.Lane.isFirstLane() && "cannot get lane > 0 for scalar");
243 Value *Lane = Instance.Lane.getAsRuntimeExpr(Builder, VF)
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| SLPVectorizer.cpp | 397 /// "shuffled out" lane would result in division by zero.
901 /// During operand reordering, we are trying to select the operand at lane
902 /// that matches best with the operand at the neighboring lane. Our
904 /// if the neighboring lane has a load, we need to look for a load that is
924 /// \returns the operand data at \p OpIdx and \p Lane.
925 OperandData &getData(unsigned OpIdx, unsigned Lane) {
926 return OpsVec[OpIdx][Lane];
929 /// \returns the operand data at \p OpIdx and \p Lane. Const version.
930 const OperandData &getData(unsigned OpIdx, unsigned Lane) const {
931 return OpsVec[OpIdx][Lane];
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| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| InterleavedAccessPass.cpp | 230 // Lane computes x's position in the Mask
231 unsigned Lane = J * Factor + I;
232 unsigned NextLane = Lane + Factor;
233 int LaneValue = Mask[Lane];
268 // StartMask defined by the last value in lane
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| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 68 const DebugLoc &DL, unsigned Reg, unsigned Lane,
74 unsigned Lane, const TargetRegisterClass *TRC);
88 unsigned Lane, unsigned ToInsert);
418 unsigned Lane, bool QPR) {
424 .addImm(Lane)
430 // Creates a SPR register from a DPR by copying the value in lane 0.
433 const DebugLoc &DL, unsigned DReg, unsigned Lane,
440 .addReg(DReg, 0, Lane);
478 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {
486 .addImm(Lane);
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| ARMExpandPseudoInsts.cpp | 140 // For quad-register load-lane and store-lane pseudo instructors, the
142 // OddDblSpc depending on the lane number operand.
162 uint8_t RegElts; // elements per D register; used for lane ops
728 // The lane operand is always the 3rd from last operand, before the 2
730 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
732 // Adjust the lane and spacing as needed for Q registers.
733 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
734 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
736 Lane -= RegElts
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| ARMBaseInstrInfo.cpp | 87 bool HasLane; // True if instruction has an extra "lane" operand.
4959 unsigned SReg, unsigned &Lane) {
4961 Lane = 0;
4966 Lane = 1;
4973 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4981 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4982 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4983 /// lane of the DPR).
4990 unsigned Lane, unsigned &ImplicitSReg) {
4991 // If the DPR is defined or used already, the other SPR lane will be chaine
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| ARMISelDAGToDAG.cpp | 215 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
273 /// used for 8, 16 and 32-bit lane sizes respectively, and each
280 /// array of 3 elements for the 8, 16 and 32-bit lane sizes.
1051 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
2388 unsigned Lane =
2410 default: llvm_unreachable("unhandled vld/vst lane type");
2470 Ops.push_back(getI32Imm(Lane, dl));
3091 // simplifies into a f32 lane move.
|
| ARMISelLowering.cpp | 1484 // a NEON instruction with an undef lane instead. This has a performance
7586 // just use VDUPLANE. We can only do this if the lane being extracted
7587 // is at a constant index, as the VDUP from lane instructions only have
7771 // Update the minimum and maximum lane number seen.
8210 // Look for full lane vmovs like <0,1,2,3> or <u,5,6,7> etc, (but not
8211 // <u,u,u,u>), returning the vmov lane index
8213 // Detect which mov lane this would be from the first non-undef element.
8351 int Lane = SVN->getSplatIndex();
8353 if (Lane == -1) Lane = 0
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64PostLegalizerLowering.cpp | 192 /// Second element is the destination lane for the G_INSERT_VECTOR_ELT.
301 static bool matchDupFromInsertVectorElt(int Lane, MachineInstr &MI,
304 if (Lane != 0)
340 static bool matchDupFromBuildVector(int Lane, MachineInstr &MI,
343 assert(Lane >= 0 && "Expected positive lane?");
345 // lane's definition directly.
350 Register Reg = BuildVecMI->getOperand(Lane + 1).getReg();
362 int Lane = *MaybeLane;
364 if (Lane < 0
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| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InterleavedAccess.cpp | 246 // only works on instructions with lane inside 256 registers. According to
258 // By computing the shuffle on a sequence of 16 elements(one lane) and add the
432 // {0, Stride%(VF/Lane), (2*Stride%(VF/Lane))...(VF*Stride/Lane)%(VF/Lane),
433 // (VF/ Lane) ,(VF / Lane)+Stride%(VF/Lane),...,
434 // (VF / Lane)+(VF*Stride/Lane)%(VF/Lane)
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIMachineFunctionInfo.h | 443 int Lane = -1;
446 SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
448 bool hasLane() { return Lane != -1;}
541 MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const {
544 : I->second.Lanes[Lane];
|
| SIRegisterInfo.cpp | 163 // a register as actually in use in another lane, so we need to save all
920 int Index, unsigned Lane,
926 MCPhysReg Reg = MFI->getVGPRToAGPRSpill(Index, Lane);
1162 unsigned Lane = RegOffset / 4;
1164 for ( ; Lane != LaneE; ++Lane) {
1167 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane)))
1169 auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill);
1172 if (NeedSuperRegDef || (IsSubReg && IsStore && Lane == 0)) {
1179 if (Lane + 1 != LaneE
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| SIISelLowering.cpp | 9163 // Select 0xc for each lane used from source operand. Zero has 0xc mask
9185 // Add 4 to each active LHS lane. It will not affect any existing 0xff
9260 // Select 0xc for each lane used from source operand. Zero has 0xc mask
9273 // Add 4 to each active LHS lane
10966 unsigned Lane = 0;
10983 // Work out which is the TFE/LWE lane if that is enabled.
11001 // Lane means which subreg of %vgpra_vgprb_vgprc_vgprd is used.
11002 // Note that subregs are packed, i.e. Lane==0 is the first bit set
11003 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
11005 Lane = SubIdx2Lane(I->getConstantOperandVal(1))
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 1380 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1388 // lane to 0 so that the splati.d instruction can be matched.
1391 // Having the index passed in a register, set the upper lane to the same
3167 // for lane 1 because it would require FR=0 mode which isn't supported by MSA.
3176 unsigned Lane = MI.getOperand(2).getImm();
3178 if (Lane == 0) {
3194 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3221 unsigned Lane = MI.getOperand(2).getImm() * 2;
3224 if (Lane == 0)
3251 unsigned Lane = MI.getOperand(2).getImm()
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| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 184 // Custom lower lane accesses to expand out variable indices
1636 // is a vector extract of an i8 or i16 lane. SIMD does not depend on sign
1701 auto GetSwizzleSrcs = [](size_t I, const SDValue &Lane) {
1703 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1705 const SDValue &SwizzleSrc = Lane->getOperand(0);
1706 const SDValue &IndexExt = Lane->getOperand(1);
1721 // If the lane is extracted from another vector at a constant index, return
1725 auto GetShuffleSrc = [&](const SDValue &Lane) {
1726 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
1728 if (!isa<ConstantSDNode>(Lane->getOperand(1).getNode())
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| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVISelLowering.cpp | 1719 const int Lane = SVN->getSplatIndex();
1720 if (Lane >= 0) {
1728 int Offset = Lane;
1780 assert(Lane < (int)NumElts && "Unexpected lane!");
1783 DAG.getConstant(Lane, DL, XLenVT), TrueMask, VL);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 4344 // the word lane which represent the v4i8 subvector. It optimizes the store
8240 // Update the minimum and maximum lane number seen.
8441 /// element width than the vector lane type. If that is the case the function
8442 /// returns true and writes the value of the DUP instruction lane operand into
8463 // lane indices of the duplicated block (i.e. [0, 1], [2, 3] and [4, 5, 6, 7]
8842 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64);
8843 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
8948 static SDValue constructDup(SDValue V, int Lane, SDLoc dl, EVT VT,
8967 // Update the lane value by offsetting with the scaled extract index.
8982 if (getScaledOffsetDup(V, Lane, CastVT))
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