| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
9 // This file implements an allocation order for virtual registers.
11 // The preferred allocation order for a virtual register depends on allocation
34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
49 assert(is_contained(Order, Hints[I]) &&
50 "Target hint is outside allocation order.");
52 return AllocationOrder(std::move(Hints), Order, HardHints);
|
| AllocationOrder.h | 1 //===-- llvm/CodeGen/AllocationOrder.h - Allocation Order -*- C++ -*-------===//
9 // This file implements an allocation order for virtual registers.
11 // The preferred allocation order for a virtual register depends on allocation
32 ArrayRef<MCPhysReg> Order;
33 // How far into the Order we can iterate. This is 0 if the AllocationOrder is
34 // constructed with HardHints = true, Order.size() otherwise. While
37 // avoid warnings and under the assumption that the size of Order is
54 /// Return the next physical register in the allocation order.
59 return AO.Order[Pos];
67 while (Pos >= 0 && Pos < AO.IterationLimit && AO.isHint(AO.Order[Pos])
[all...] |
| RegAllocBasic.cpp | 267 auto Order =
269 for (MCRegister PhysReg : Order) {
|
| BreakFalseDeps.cpp | 15 /// parallel in an out-of-order CPU.
40 /// List of undefined register reads in this block in forward order.
153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
154 for (MCPhysReg Reg : Order) {
|
| CriticalAntiDepBreaker.cpp | 402 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
403 for (unsigned i = 0; i != Order.size(); ++i) {
404 unsigned NewReg = Order[i];
556 // the anti-dependencies in an instruction in order to be effective.
|
| LocalStackSlotAllocation.cpp | 56 // Order reference instruction appears in program. Used to ensure
57 // deterministic order when multiple instructions may reference the same
59 unsigned Order;
63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {}
66 return std::tie(LocalOffset, FrameIdx, Order) <
67 std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order);
302 unsigned Order = 0;
330 FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++));
400 // Because the FrameRefs are in sorted order, and we've already
|
| /src/usr.sbin/ypserv/yptest/ |
| yptest.c | 54 int KeyLen, ValLen, Status, Order;
104 Status = yp_order(Domain, Map, &Order);
106 printf("%d\n", Order);
|
| /src/external/apache2/llvm/dist/llvm/tools/llvm-profgen/ |
| CSPreInliner.cpp | 44 std::vector<StringRef> Order;
47 // Now that we have a profiled call graph, construct top-down order
48 // by building up SCC and reversing SCC order.
53 Order.push_back(Node->Name);
57 std::reverse(Order.begin(), Order.end());
59 return Order;
|
| /src/games/mille/ |
| extern.c | 51 Order, /* set if hand should be sorted */
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 37 std::unique_ptr<MCPhysReg[]> Order;
42 return makeArrayRef(Order.get(), NumRegs);
96 /// getOrder - Returns the preferred allocation order for RC. The order
122 /// Get the minimum register cost in RC's allocation order.
|
| ScheduleDAG.h | 56 Order ///< Any other ordering dependency.
89 /// Additional information about Order dependencies.
124 : Dep(S, Order), Contents(), Latency(0) {
165 /// Tests if this is an Order dependence between two memory accesses
169 return getKind() == Order && (Contents.OrdKind == MayAliasMem
173 /// Tests if this is an Order dependence that is marked as a barrier.
175 return getKind() == Order && Contents.OrdKind == Barrier;
183 /// Tests if this is an Order dependence that is marked as
187 return getKind() == Order && Contents.OrdKind == MustAliasMem;
195 return getKind() == Order && Contents.OrdKind >= Weak
[all...] |
| /src/external/apache2/llvm/dist/libcxx/benchmarks/ |
| algorithms.bench.cpp | 35 enum class Order {
43 struct AllOrders : EnumValuesAsTuple<AllOrders, Order, 6> {
50 void fillValues(std::vector<T>& V, size_t N, Order O) {
51 if (O == Order::SingleElement) {
60 void fillValues(std::vector<std::pair<T, T> >& V, size_t N, Order O) {
61 if (O == Order::SingleElement) {
75 void fillValues(std::vector<std::tuple<T1, T2, T3> >& V, size_t N, Order O) {
76 if (O == Order::SingleElement) {
96 void fillValues(std::vector<std::string>& V, size_t N, Order O) {
97 if (O == Order::SingleElement)
[all...] |
| map.bench.cpp | 45 enum class Order { Sorted, Random };
46 struct AllOrders : EnumValuesAsTuple<AllOrders, Order, 2> {
236 template <class Mode, class Order>
243 Order::value == ::Order::Random ? Shuffle::Keys : Shuffle::None, 1000);
264 Order::value == ::Order::Random ? Shuffle::Keys
272 return "BM_Insert" + baseName() + Mode::name() + Order::name();
355 template <class Mode, class Order>
362 Order::value == ::Order::Random ? Shuffle::Keys : Shuffle::None, 1000)
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/Passes/ |
| StandardInstrumentations.h | 121 // unordered the order of successors is not tracked by the CFG. In other words
283 // Information that needs to be saved for a basic block in order to compare
308 // Return the names in the order they were saved
309 std::vector<std::string> &getOrder() { return Order; }
310 const std::vector<std::string> &getOrder() const { return Order; }
321 // \p Before and \p After. The order is based on the order in \p After
323 // occur in \p Before. This is used to present the output in an order
330 std::vector<std::string> Order;
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 148 unsigned Order;
162 Var(Var), Expr(Expr), DL(DL), Order(O), IsIndirect(IsIndirect),
216 /// Returns the SDNodeOrder. This is the order of the preceding node in the
218 unsigned getOrder() const { return Order; }
244 unsigned Order;
248 : Label(Label), DL(std::move(dl)), Order(O) {}
256 /// Returns the SDNodeOrder. This is the order of the preceding node in the
258 unsigned getOrder() const { return Order; }
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAGHVX.cpp | 92 // the opposite order.
107 Coloring(ArrayRef<Node> Ord) : Order(Ord) {
126 ArrayRef<Node> Order;
134 Node Num = Order.size();
165 // Add Order[P] and Order[conj(P)] to Edges.
166 for (unsigned P = 0; P != Order.size(); ++P) {
167 Node I = Order[P];
170 Node PC = Order[conj(P)];
176 for (unsigned I = 0; I != Order.size(); ++I)
[all...] |
| /src/external/apache2/llvm/dist/llvm/tools/verify-uselistorder/ |
| verify-uselistorder.cpp | 9 // Verify that use-list order can be serialized correctly. After reading the
19 // 2. Visit every Value in a deterministic order.
21 // 3. Assign a random number to each Use in the Value's use-list in order.
23 // 4. If the numbers are already in order, reassign numbers until they aren't.
91 /// here. The order needs to be deterministic, but it's unnecessary to match
183 // The current mapping order makes it easier to debug the tables. It happens
355 report_fatal_error("use-list order changed");
407 SmallDenseMap<const Use *, short, 16> Order;
409 [&Order](const Use &L, const Use &R) { return Order[&L] < Order[&R]; }
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| Instruction.h | 50 /// Relative order of this instruction in its parent basic block. Used for
52 mutable unsigned Order = 0;
322 /// has three operands (including name string), swap the order of the
|
| /src/external/apache2/llvm/dist/llvm/lib/IR/ |
| BasicBlock.cpp | 500 unsigned Order = 0;
502 I.Order = Order++;
504 // Set the bit to indicate that the instruction order valid and cached.
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| MergeICmps.cpp | 100 // We want to order BCEAtoms by (Base, Offset). However we cannot use
102 // To make sure that the sort order is stable, we first assign to each atom
103 // base value an index based on its order of appearance in the chain of
120 // A class that assigns increasing ids to values in the order in which they are
128 const auto Insertion = BaseToIndex.try_emplace(Base, Order);
130 ++Order;
135 unsigned Order = 1;
168 // We need to make sure that we can do comparison in any order, so we
464 // instructions that do other work in program order, i.e. within the
814 // last block and reconstruct the order
[all...] |
| StructurizeCFG.cpp | 251 SmallVector<RegionNode *, 8> Order;
369 /// Build up the general order of nodes, by performing a topological sort of the
373 Order.resize(std::distance(GraphTraits<Region *>::nodes_begin(ParentRegion),
375 if (Order.empty())
381 // A list of range indices of SCCs in Order, to be processed.
383 unsigned I = 0, E = Order.size();
393 // and a possible additional node. Therefore, it is already in order, and
399 // Add the SCC nodes to the Order array.
402 Order[I++] = N.first;
407 // If there are no more SCCs to order, then we are done
[all...] |
| /src/sys/external/bsd/acpica/dist/include/ |
| acbuffer.h | 59 * this decision was a design error in C. Ritchie could have picked an order
144 UINT8 Order;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMLowOverheadLoops.cpp | 116 SmallVector<MachineBasicBlock*, 4> Order;
123 return Order;
140 Order.push_back(MBB);
146 append_range(Order, ExitBlocks);
154 Order.push_back(MBB);
1648 // FIXME: For some reason, the live-in print order is non-deterministic for
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 188 // Add sub-registers to OSet following a pre-order defined by the .td file.
200 // Get the list of super-registers in topological order, small to large.
225 // List of register units in ascending order.
295 // Allocation orders. Order[0] always contains all registers in Members.
428 // The order of registers is the same as in the .td file.
429 // No = 0 is the default allocation order, No = 1 is the first alternative.
456 // the topological order used for the EnumValues.
467 // Lexicographical order of (Members, RegSizeInfoByHwMode).
519 unsigned Order = 0; // Cache the sort key.
574 // Give each register unit set an order based on sorting criteria
[all...] |
| RegisterInfoEmitter.cpp | 309 PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order);
1042 ArrayRef<Record*> Order = RC.getOrder();
1053 for (Record *Reg : Order) {
1062 for (Record *Reg : Order) {
1228 ArrayRef<Record*> Order = RC.getOrder();
1231 AllocatableRegs.insert(Order.begin(), Order.end());
1285 assert(RC.EnumValue == EV && "Unexpected order of register classes");
1389 << " const ArrayRef<MCPhysReg> Order[] = {\n"
1398 << ");\n return Order[Select];\n}\n"
[all...] |
