| /src/external/gpl3/binutils/dist/opcodes/ |
| s390-opc.c | 65 #define R_28 (R_24 + 1) /* GPR starting at position 28 */
67 #define R_CP16_28 (R_28 + 1) /* GPR starting at position 28 */
343 #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
345 #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
356 #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
357 #define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */
359 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
360 #define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */
364 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */
365 #define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr *
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| s390-opc.c | 65 #define R_28 (R_24 + 1) /* GPR starting at position 28 */
67 #define R_CP16_28 (R_28 + 1) /* GPR starting at position 28 */
343 #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
345 #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
356 #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
357 #define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */
359 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
360 #define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */
364 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */
365 #define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr *
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| s390-opc.c | 65 #define R_28 (R_24 + 1) /* GPR starting at position 28 */
67 #define R_CP16_28 (R_28 + 1) /* GPR starting at position 28 */
343 #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
345 #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
356 #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
357 #define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */
359 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
360 #define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */
364 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */
365 #define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr *
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| s390-opc.c | 65 #define R_28 (R_24 + 1) /* GPR starting at position 28 */
67 #define R_CP16_28 (R_28 + 1) /* GPR starting at position 28 */
343 #define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */
345 #define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
356 #define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
357 #define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */
359 #define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
360 #define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */
364 #define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */
365 #define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr *
[all...] |
